Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
4.1 Transmitter Introduction
4.2.1 The Proposed D-BPSK Transmitter
The proposed architecture of the DPSK transmitter, as shown in Fig. 4-3, is composed of a single-to-differential buffer, a multiplexer (MUX), a pulse generator, an
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
44
injection-locked ring oscillator (ILO), a PA, and a baseband circuit for D-BPSK encoding.
The single-to-differential buffer produces multi-phase information for MUX.
Before injecting to the ILO, the signal is passing through the pulse generator for optimizing injection strength. The baseband circuit generates digital data to drive MUX and select correct phase signal. Therefore, the sub-harmonically injection-locked ring oscillator performs phase modulation. That is the the phase of ILO depends on the phase of injected signal as discussed in Chapter 4.1.2. Finally, power amplifier transmitted the modulated RF signal to output.
Matching
Fig. 4-3 Proposed DPSK Transmitter with Sub-harmonic Injection-Locked Modulation
4.2.2 Design Specifications of the Proposed Transmitter
Error vector magnitude (EVM) is defined as the deviation of the constellation points from their ideal positions [11].
The magnitude deviation ( A M
D ) is small enough to be neglected when comparing
with phase deviation in this work, the relationship between EVM and phase error can be expressed in (4-5) according to [32].
4.2 System Architecture sub-harmonically injection-locked technique. As analyzed in Chapter 4.1.2, there’s no phase error if the free-running frequency of oscillator is equal to N times input frequency of injected signal in ideal environment. However, the frequency mismatch due to the non-ideal effect in real circuit will induce the periodic phase error.
Equation (4-6) shows the connection between EVM and frequency deviation Df, center frequency f0 and N is the sub-harmonic injection ratio which affects the performance of EVM significantly [31].
2The improvement of EVM is by setting N as small as possible. However, it means that most circuit blocks operating at higher frequency, which consumes more power.
That is to say, there is a trade-off lying between power and EVM. Therefore, the sub-harmonic injection ratio N is designed to be 9 in this proposed architecture.
To substitute the design parameter f0 = 430 MHz, N is 9 and assume the worst frequency deviation Df is 100 kHz , the EVM is smaller than 1% which obeys the specification for this target.
The injection spurs resulting from sub-harmonic injection-locked technique are discussed at [31], and (4-7) shows the connection to design parameter. The performance of spurs also depends on the sub-harmonic injection ratio.
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
Another significant specification is maximum data rate which is dominated by locking range L as discussed in Chapter 3.2.2. According to (3-14), the locking range
L of ILO must be larger than 2*6.366 MHz if maximum data rate is 10 Mbps. This requirement of locking range for ring oscillator isn’t a tight specification for transmitter.
The injection strength not only depends on the amplitude of injected signal but also the pulse width. In this system, the pulse width is only the designed parameter because the amplitude is rail to rail swing which is limited by voltage supply (0.5V).
Equation (4-8) shows the Fourier transform for a pulse with pulse width W=
D T INJ, which D is duty cycle for injected signal whose period is TINJ, and KN represents the injection strength.
( )
N, the sub-harmonic injection ratio is 9, and the maximum injection strength K9 is obtained by setting duty cycle D is 1/18. It is the optimum value of pulse width for sub-harmonic injection oscillator.
To sum up, the maximum data rate determines the locking range of sub-harmonic injected oscillator. Not only EVM but also spur is affected by the sub-harmonic injection ratio mainly. Moreover, the injected pulse width is required to be designed carefully for maximum injection strength. Above analysis provides insights into the design of TX system. Finally, the specification of this work is shown in Table 4-1.
4.3 Circuit Implementation
Table 4-1 Designing Specifications of D-BPSK Transmitter
Process TSMC 0.18-m CMOS
Supply Voltage 0.5 V
Operating Frequency 414 ~ 457 MHz
Max Data Rate 10 Mbps
Pout >-10 dBm
Modulation D-BPSK
Power Consumption < 0.3 mW Energy Efficiency < 30 pJ/b
4.3 Circuit Implementation
4.3.1 Pulse Generator
CKINJ
CK’
VINJ
t Vbody
Time delay Circuit
CKINJ VINJ
CK’
CKDelay
CKDelay
Fig. 4-4 Pulse Generator
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
48
A pulse generator which is depicted in Fig. 4-4 is adopted for generating optimum injected pulse width from an external clock reference (CKINJ) as mentioned in Chapter 4.2.2. The pulse width of the pulse generator can be tuned through modifying the time delay circuit with body-bias technique, and Fig. 4-5 displays the tuning range of pulse width, and the range is from 400 ps to 2.3 ns at different corner conditions.
SS80
Fig. 4-5 The pulse width tuning range
4.3.2 Sub-harmonically Injection-Locked Ring DCO
Fig. 4-6 displays a 3-stage sub-harmonically single-ended injection-locked ring DCO in this work. The injection-locking technique is realized by shorting one of the stages to ground through an NMOS, and this would make the transition edge of VOSC
align with that of VINJ. The output phase noise performance of a ring DCO can be improved effectively with sub-harmonic injection-locked technique as discussed in Chapter 4.1.2.
4.3 Circuit Implementation
VINJ
Vosc
C<2:0>
Digital Control
Vbody Analog Control
Fig. 4-6 Single-ended Sub-harmonic Injection-Locked Ring Oscillator
Fig. 4-7 Simulated Phase Noise of Ring Oscillator (Carrier@430MHz)
Fig. 4-7 displays the simulated phase noise of the single-ended injection-locked ring DCO under free-run conditions, and it is simulated under TT corner with 27°
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
50
temperature. As the figure shows, the phase noise for free-run DCO is -18.58 dBc/Hz, -47.5 dBc/Hz, -75.4 dBc/Hz, and -99.57 dBc/Hz at frequency offset of 10 kHz, 100 kHz,1 MHz, and 10MHz. Table 4-2 summaries the simulated characteristic of the DCO.
Table 4-2 Simulated characteristics of the DCO @ TT27 o
Item Value
Supply Voltage 0.5 V
Current 198 A
Oscillation frequency 435 MHz Phase Noise at 1 MHz -99 dBc/Hz
Digital Control bits 3 bits
Total Tuning Range 70 MHz
4.3.3 Power Amplifier
To achieve low-power operation, the class-E power amplifier is adopted in ultra-low power supply (0.5V). An inverter inserted between DCO and PA acts as a buffer for the purpose of isolation. The detailed circuit implementation with the output impedance transformation is shown in Fig. 4-8.
The output 50-ohm matching at TXOUT is accomplished by the tapped matching work which is composed of the choke inductor L and capacitors C1, C2.. Assume the quality factor Q of inductor L is larger than 10, then the following approximation establishes the impedance transformation in equation (4-9), where RL is output loading whose value is usually 50-ohm.
4.3 Circuit Implementation
Fig. 4-8 Class-E Power Amplifier and Output Impedance Transformation Network
L
The tapped output matching network is simplified as a LC tank. The DC current (IPA) required for a certain PA output power can be approximately estimated as
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
52
-40dBm as discussed in Chapter 4.1.2. Table 4-3 summaries the simulated characteristic of the PA.
Fig. 4-9 PA Output Spectrum with injected signal Table 4-3 Simulated characteristics of the PA @ TT27 o
Item Value
Supply Voltage 0.5 V
Current 295 A
Oscillation frequency 435 MHz
Max Pout -9.7dBm
Efficiency 62.5%
4.4 System Simulation Results
4.4 System Simulation Results
The system simulation results displayed in Fig. 4-10 verifies the sub-harmonic injected-locked modulation technique.
Fig. 4-10 Timing diagram of Proposed TX
4.5 Experimental Results
4.5.1 Die Photo
This chip is fabricated in TSMC 0.18-μm CMOS 1P6M process and occupies a core area of 0.8 mm2. As shown in Fig. 4-11, the whole system is divided into several blocks: baseband circuit, injection-locked DCO, a pulse generator, and a power amplifier for transmitting TX output signal. The supply voltage for all blocks is 0.5 V.
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
B: Pulse generator & DCO C: PA
Fig. 4-11 Die Photo of the Proposed TX
4.5.2 Measurement Environment Setup
The measurement environment setup is depicted in Fig. 4-12. LDO regulators stabilize dc voltages which provided by Agilent E3646A power supply. Then, a R & S SML03 signal generator generates the 44.45 MHz injection signal, and an Agilent 33250A waveform generator provides the 10 MHz baseband data clock. Finally, signal analyzer (Agilent N9020A) measures the performance of the PA output signal.
PCB
Fig. 4-12 Measurement Environments
4.5 Experimental Results
4.5.3 PCB Design
A PCB is fabricated for testing and verifying the function of the proposed D-BPSK transmitter as shown in Fig. 4-13. The 3-bit controlling signal with analog voltage tunes DCO free-run frequency. AC input/output signals, such as PA output signal, input clock signal, and baseband signal, are connected through SMA terminals.
The PA matching network, composed of shunt capacitors and series inductor, is also welded on board.
Fig. 4-13 PCB for Testing
4.5.4 Measured Results
Fig. 4-14 shows the measured TX output spectrum at 410 MHz, and the system output power is -18 dBm. Moreover the adjacent spur tone is less than -70 dBm. The relationship between frequency and output power is depicted in Fig 4-15. It indicate the output power remain -18 to -22dBm from 360MHz to 420MHz.
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
Fig. 4-15 TX Output Power versus Frequency
4.5 Experimental Results
TX free-running output waveform is displayed in Fig. 4-16. The peak to peak swing is about 74.4 mV. With output loading of 50-ohm, the output power is about -18dBm, which is similar value to that measured one by signal analyzer.
Fig. 4-16 TX free-running transient waveform
TX output phase noise under free-run ring DCO, injection-locked ring DCO is displayed in Fig. 4-17. This graph reveals that the phase noise of TX output carrier signal is dominated by injection-locked technique. However, this measurement indicates the injected strength is not enough, so the improvement of the phase noise is limited.
The phase modulation in this work is achieved by sub-harmonic injection-locked technique. In other word, the injection-locked step must be completed before performing phase modulation. However, the measurement in Fig. 4-17 shows that the injection does not function properly.
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
Fig. 4-17 Measured TX Output Phase Noise
Table 4-4 displays the detailed power breakdown of the proposed transmitter. The voltage supply is 0.5V for all blocks. Most power consumption is contributed by the power amplifier and DCO because those blocks operating at RF frequency.
Nevertheless, the single-ended ring topology for oscillator and class-E PA reduce the total power consumption significantly. The measured value is only 331 μW.
Table 4-5 summarizes the simulated results of the proposed TX and the comparison to related works.
Table 4-4 Power Breakdown of the D-BPSK TX
Circuit Power (μW)
Baseband Circuit 56
DCO 128
PA 147
Total 331
4.5 Experimental Results
Table 4-5 Comparison Table of the Proposed TX
Reference [21]
JSSC’11
[32]
TMTT’12
[18]
JSSC’11
Simulated Result
Measured Result Technology
(nm) 130 180 180 180 180
Supply
(V) 1.2 1.4 0.7 0.5 0.5
Modulation BFSK QPSK BFOK D-BPSK D-BPSK
Freq. Band
(MHz) 400 915 920 414 ~ 454 414 ~ 454
Data Rate
(Mbps) 0.2 100 5 10 N/A
Power Con.
(μW) 90 5600 700 294 331
Pout
(dBm) -17 -3 -10 -9.7 -18
Energy/bit
(pJ/bit) 450 560 140 29.4 N/A
5.1 Conclusions
Chapter 5 Conclusions and Future Works
5.1 Conclusions
This thesis introduces ultra-low-voltage wireless transceiver for wearable applications. The dynamic phase-to-amplitude conversion by injection-locked oscillator diminishes power consumption of receiver. Furthermore, the transmitter with the sub-harmonically injection-locked ring oscillator performs phase modulation without power-hungry blocks such as multi-phase carrier generation.
Both transmitter and receiver adopt injection-locked technique and operate at 0.5 V for the purpose of high energy-efficient communication. The forward body bias skill is used for reducing threshold voltage in ultra-low-voltage environment. Besides, this technique can be utilized for the current tuning of transistor. Not only time-delay circuit but also voltage-controlled oscillators require body-bias skill.
5.2 Future Works
Recalling from the experimental results in chapter 3.5, the sensitivity of receiver does not meet the design of specification. To address the degraded sensitivity, a direct-tail injected oscillator with differential injected path can be adpoted.
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