Chapter 2 Basic Concepts in RFIC Design
3.2 Low Noise Amplifier Architecture Analysis
Cgs
Figure 3-7 Equivalent noise model of Figure 3-1 In Figure 3-7, the input impedance can be expressed as
gs
as shown in equation (3.9), the input impedance is equal to the multiplication of cutoff
frequency of the device and source inductance at resonant frequency. Therefore it can be set to 50 ohm for input matching while resonant frequency is designed to be equal to the operating frequency.
According to prior introduction, the equivalent noise model of common-source LNA with inductive source degeneration can be expressed as Figure 3-7, where is the parasitic resistance of the inductor and is the gate resistance of the device.
Note that the overlap capacitance C
Rl
Rg
gd has also been neglected in the interest of simplicity. Then the noise figure can be obtained by computing the total output noise power and output noise power due to input source. To find the output noise, we first evaluate the trans-conductance of the input stage. With the output current proportional to the voltage no Cgs and noting that the input circuit takes the form of series-resonant network, the transconductance at the resonant frequency can be expressed as
s
where Qin is the effective Q of the amplifier input circuit. So the output noise power density due to the source can be expressed as
2
Furthermore, channel current noise of the device is the dominant noise contributor, and its noise power density associated with the correlated portion of the gate noise can be expressed as
, 2
The last noise term is the contribution of the uncorrelated portion of the gate noise, and its output noise power density can be expressed as
, 2 resonant frequency can be expressed as
⎟⎟⎠
where
) 1 5 (
| 5
| 2
1+ c QL 2 + 2 +QL2
= γ
δα γ
χ δα (3.19)
From equation (3.19), we observe that χ includes the terms which are
constant, proportional to , and proportional to . It follows that equation (3.19) will contain terms which are proportional to as well as inversely proportional to
. A minimum noise figure, therefore, exits for a particular .
QL QL2
QL
L L
Q Q
Chapter 4
UWB CMOS LNA Design
---
4.1 Design Procedures
This architecture is for an Ultra-Wideband CMOS LNA with Current-Reused Technique for 3.1 to 10.6 GHZ. It has an advantage of high gain, low power consumption, low noise performance and small size. We utilize three-stage amplifier to get a flat gain at high frequency. The first stage introduces the band pass filter for input matching, it includes two inductances, one capacitor and one inductance at gate. The second stage introduces a current-reuse cascaded common-sources structure to lower power consumption. The last stage introduces LC in shunt connection to improve gain and bandwidth for high frequency. The current buffer configuration is used for output matching. Its circuit diagram is shown in Figure 4.1 and chap layout is shown in Figure 4-2.
Figure 4-1 Circuit diagram
Figure 4-2 Chip layout
4.1.1 Analysis of Input Matching
In input part, we adopt a common-source amplifier, by introducing matching components to let the frequency resonate at which we want. We also simplify the first stage as in Figure 4-3, and the circuit can be viewed form point A to
1
In addition, we put a shunt-LC resonance in input part, following with the equivalent circuit Z1, to make it have a good resonance in the imagine part, and get
real part impedance-matching (Rs=gm1Ls1/Cgs1) at the same time. Form figure 4-4 we can get the input matching impedance Zin in equation (4.2).
1
We can also keep a very low noise to procure a band-pass amplifier for an entire Ultra-Wideband.
A
Z1
Figure 4-3 simplification of the first stage
Figure 4-4 the input impedance Zin
4.1.2 Analysis of Output Matching
The current buffer configuration is used for output matching as shown in Figure4-5，and make the entire frequency matching to 50 Ω.In this circuit, M3 is the source follower, and the steady current of M3 is provided by M4.We only need to control the supply voltage and the size of the transistor, and then a good output matching will be obtained as equation below.
3 4
3
|| 1 1
m o
m
out
r g
Z = g ≈
(4.3)
Figure 4-5 the current buffer
4.1.3 Gain Analyzing
Figure 4-6 Current-reused two stage cascade amplifier with series inter-stage resonance
Figure 4-7 Small signal equivalent representation of the circuit from node X to Y
In Figure 4-6 is the Current-reused two stage cascade amplifier with series inter-stage resonance, and the Small signal equivalent representation of the circuit from node X to Y is in Figure 4-7. If we divide id2 to id1, we can get the gain
and. If provides high impedance, then, we can get
4.1.4 Bandwidth Analyzing:
In order to get a low power consumption low noise amplifier LNA, we cascade the second amplifier M2 on the first amplifier M1 to use the same dc current to achieve the goal of power saving. Besides we also utilize substrate bias at M1 to enhance the gain, at the same time reduce the power consumption.
For gain and the bandwidth, we utilize three-stage amplifier to achieve a high gain and the flat bandwidth design. In the circuit, the requirement of the current-reused structure is Coupling capacitor (C2) which is connected to the output of the first stage amplifier (at drain) and also connected to the input of the stage second stage amplifier (at gate) .Therefore it can provide signal coupling between the two stages and the Bypass capacitor (Cbypass) functions as an ac ground at the source of transistor M2, for avoiding the coupling effect to the first stage. Aside from, we join the shunt-LC resonance CB and LB, by this LC resonance the bandwidth and the gain can be improve a lot in order to get a high gain Ultra-Wideband circuit. In Figure 4-8, we can see the gain combined by the three state amplifiers.
Figure 4-8 the gain of the circuit
4.2 Simulation Results
Figure 4-9 shows the Return loss Simulation. S11 is lower than -9.4dB between 3.1 and 10.6GHz. The output buffer achieves excellent matching such that S22 is lower than -11dB from 3.1GHz to 10.6 GHz in Figure 4-10. Figure 4-11 is the power gain versus frequency, the gain at 3.1GHz is 13.567dB and at 10.6GHz is 13.319, so the different between the wideband is only 0.25dB.The reverse isolation S21 is lower than -38dB shown in Figure 4-12. The noise figure (NF) of this UWB LNA is shown in Figure 4-13.The NF at 3.1GHz is 2.686dB, at 10.6GHz is 2.842dB and the minimum noise figure (NFmin) at 5.7GHz is 2.146dB. The stability factor (MuPrime1, Mu1) both are greater than 1, implying that have a stable circuit in Figure
4-14.The third-order intermodulation distortion(IIP3) is -3dBm and shown in Figure 4-15 ,the test is performed at 4 GHz. These results imply excellent linearity of our LNA. The proposed UWB LNA dissipates 10.3mW with a power supply of 1.8V.
Figure 4-9 Simulated S11
Figure 4-10 Simulated S22
Figure 4-11 Simulated S21
Figure 4-12 Simulated S12
Figure 4-13 Simulated Noise Figure
Figure 4-14 Simulated stability
Figure 4-15 simulated IIP3
4.3 Measurements and Conclusions
The following Figure4-16 ~ Figure4-21 are the measurement result which are slightly different from simulation. Which imply good accuracy of simulation and good circuit design. But the gain dropping at high frequency (in Figure 4-16) is due to TSMC model at high frequency is not accurate.
The bandwidth of this work with considering matching and gain is from 3.1 to 10.6 GHz, while the average gain is about 10dB. Figure 4-17 and Figure 4-18 show the measurement results of S11 and S22. Input and output matching are achieved very well from 3.1 to 10.6 GHz, so S11 can bellow -9dB and the S22 can bellow -11dB.S12 below up to -33dB in Figure 4-19. The noise figure is about 3.6 shown in Figure 4-20.The noise performance is very flat and the minimum noise figure is 2.85dB at 5GHz. The noise figure can be better if we solve the resistor parasitic. The linearity of the third-order intermodulation distortion(IIP3) is -3dBm as measurement and shown in Figure 4-21. Figure 4-22 shows the die photo of this circuit. Total power consumption is 10.3 mW which the Vdd is 1.8V.In the chip, the apply Vb is 0.1V, Vg1 is 0.61V and Vg2 is 0.61V. Table 4.1 is the measurement result summary. By the band pass filter, the current buffer configuration, the shunt-LC resonance, Current-Reused Technique we proposed, a good input and output matching, broadband, a low power consumption LNA is developed for UWB system applications.
3 4 5 6 7 8 9 10
2 11
0 5 10
-5 15
freq, GHz
dB(S(2,1))
Figure 4-16 Measured S21
3 4 5 6 7 8 9 10
2 11
-25 -20 -15 -10
-30 -5
freq, GHz
dB(S(1,1))
Figure 4-17 Measured S11
3 4 5 6 7 8 9 10
2 11
-22 -20 -18 -16 -14
-24 -12
freq, GHz
dB(S(2,2))
Figure 4-18 Measured S22
3 4 5 6 7 8 9 10
2 11
-38 -36 -34
-40 -32
freq, GHz
dB(S(1,2))
Figure 4-19 Measured S12
0 5 10 15
2 3 4 5 6 7 8 9 10 11
Freq,GHZ
NF(dB)
Figure 4-20 Measured noise figure
Input Power (dB)
-40 -30 -20 -10 0
Output Power (dB)
-100 -80 -60 -40 -20 0
OP3 OP1
-3 - 3
Figure 4-22 Die photo
B.W (GHz)
Gain (dB)
NF (dB)
S11 (dB)
S22 (dB)
IIP3 (dBm)
Pdc (mW) 3.1~10.6 10 3.6 < -9 < -13 -3 10.3
Table 4.1 Measured results summary
Chapter 5
Summary
---By the Current-Reused Technique for 3.1 to 10.6GHZ we proposed, a good input and output matching, broadband, a low power consumption amplifier is developed for UWB system applications.
Table 5.1 is the comparison of broadband LNA performance. We can find out by this table, by using Current-Reused Technique and shunt-LC resonance, can pull to being wide very big arrival 3.1~10.6GHz frequently. All the advantages are important for UWB system considerations.
specifications This work Ref. [14] Ref. [15] Ref. [16] Ref. [17]
Process 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm Frequency (GHz) 3.1~10.6 2.4~9.5 2~4.6 2~6.5 3.1~10.6
S11 (dB) <-9 <-9 <-9 <-7.8 <-8
S22 (dB) <-13 <-20 <-10 <-16 ----
Gain (dB) 10 9.3 9.8 11.9 13.5~16
NF (dB) 2.85~4.5 4~9 2.3~6 4.1~4.6 3.1-6
IIP3 (dBm) -3 -6.7 -7 4 -7
Pdiss (total) (mW) 10.3 18 12.6* 27 11.9
Die size (mm2) 0.89 1.1 0.9 0.88 1.2
Table 5.1 Comparison of broadband LNA performance (*Only core LNA)
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Vita
姓名：李富國 性別：男
出生年月日：民國 69 年 4 月 29 日 籍貫：雲南 龍陵
住址：新竹市 寶山路 93 巷 3 弄 11 號 學歷：國立交通大學電子工程學系 (91 年 9 月~95 年 6 月)
國立交通大學微電子奈米工程研究碩士班 (95 年 9 月~97 年 6 月)
論文題目：
電流重複用之超寬頻金氧半低雜訊放大器應用於3.1-10.6GHZ
An Ultra-Wideband CMOS LNA with Current-Reused Technique for 3.1 to 10.6GHZ