電流重複用之超寬頻金氧半低雜訊放大器應用於3.1-10.6GHZ

國

立

交

通

大

學

電機學院微電子奈米科技產業研發碩士班

碩

士

論

文

電流重複用之超寬頻金氧半低雜訊放大器應用於

3.1-10.6GH

_Z

An Ultra-Wideband CMOS LNA with Current-Reused Technique

for 3.1 to 10.6GH

研 究 生：

李富國

指導教授 ：

荊鳳德

教授

電流重複用之超寬頻金氧半低雜訊放大器應用於3.1-10.6GH

An Ultra-Wideband CMOS LNA with Current-Reused Technique for

3.1 to 10.6GH

研 究 生：李富國 Student: Fu-Kuo Li

指導教授：荊鳳德 博士 Advisor: Dr. Albert Chin

國 立 交 通 大 學

電機學院微電子奈米科技產業研發碩士班

碩 士 論 文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master In

Industrial Technology R & D Master Program on Microelectronics and Nano Sciences

June 2008

Hsinchu, Taiwan, Republic of China

電流重複用之超寬頻金氧半低雜訊放大器

應用於

3.1-10.6GH

學生: 李富國

指導教授: 荊鳳德 博士

國立交通大學電機學院產業研發碩士班

摘

要

本論文研製之一個電流重複使用低雜訊放大器，此低雜訊放大器具有高

增益、低功率、低雜訊且小面積之優點。我們採用三級方式有別於一般電流重複

使用低雜訊放大器，來擴充高頻的頻寬，使增益更為平坦，在第一級部分，我們

是利用帶通慮波器來做input matching，接著第二級部分，利用疊接方式來達到

電流重複使用，以降低功率消耗，最後我們採用一個LC並聯共振電路方式，來增

強高頻部份的增益並增加頻寬作為第三級，在輸出部分則是利用current buffer

的方式來達到output matching。供應電壓V

為 1.8 伏特時，整個電路功率消耗

約為 10.3mW，及包含pad的情況下整個電路大小約為 0.89 mm

。本研究的低雜訊

放大器所量測的規格，平均順向增益(S

)在 3.1~10.6GHz時為 10dB，逆向隔離(S

)

為-33dB以下，S11 為-9dB以下，S22 約為-11dB以下，而平均雜訊指數約為 3.6dB。

An Ultra-Wideband CMOS LNA

with Current-Reused Technique for 3.1 to 10.6GH

Student: Fu-Kuo Li Advisor: Dr. Albert Chin

Industrial Technology R &

D Master Program of

Electrical and Computer Engineering College

National Chiao Tung University

ABSTRACT

A procedure

is for an Ultra-Wideband CMOS LNA with Current-Reused

Technique for 3.1 to 10.6GH

. It has an advantage of high gain, low power

consumption, low noise performance and small size. We utilize three-stage amplifier

to get a flat gain at high frequency. The first stage introduces the band pass filter for

input matching, the second stage introduces a current-reused cascaded

common-sources structure to lower power consumption. The last stage introduces

shunt-LC resonance to improve gain and the bandwidth. The current buffer

configuration is used for output matching. The total power dissipation of the chip is

about 10.3 mW at power supply 1.8 volt. The chip size included pad is 0.89 mm

. The

measurement result of this study expect that the average forward S

is 10dB at

3.1~10.6GHz, the reverse isolation S

is under -33dB, the magnitude of S

is under

誌

謝

本篇碩士論文順利完成，首先感謝指導老師荊鳳德教

授，老師熱誠的態度與對研究的敏銳度感染了實驗室每位同學，在老

師的指導下順利完成學業，讓我學習到很多。在此致上我最深的尊敬

與感謝。

感謝交通大學 ED633 實驗室的全體同學，感謝高瑄苓愽士，張

慈愽士，李佩諭學姐 給予我的建議與關心，提供我許多寶貴經驗。

感謝同屆同學陳膺任，劉思麟 在學業上一起經歷這兩年，一起修課，

一起寫作業，一起接受嚴厲考試的試煉;在生活互相砥礪，在研究中

有討論的同伴，一起經歷了美好的日子。還有感謝實驗室所有學長姐

和學弟妹們所給予我實驗室的新鮮有活力的研究風氣。還要感謝我的

家人，我的努力的動力，我不敢忘記家裡的需要與父母的辛苦，是你

們讓我能有美好的環境，有機會挑戰自我的理想。

最後感謝新竹，感謝交大，感謝那些幫助我關心我的人。

Contents

Abstract (in Chinese)

Abstract (in English)

Contents

Figure Captions

Chapter 1 Introduction

1.1 UWB CMOS Receivers

1.2 Motivation

Chapter 2 Basic Concepts in RFIC Design

2.1 Noise Sources in MOSFETs

2.1.1Drain Current Noise ……….………4

2.1.2Substrate Thermal Noise………...5

2.1.3 Drain Induced Gate Noise……….6

2.2 Noise Analysis

2.2.1 The Concept of Noise Figure………9

2.2.2 Linearity in RF Circuits………...11

2.2.3 Third-Order Intercept point and The 1-dB Compression Point…………...13

Chapter 3 General Consideration in LNA Circuit Design

3.1 Low Noise Amplifier Basic

3.1.1 Impedance Matching Network………20

3.1.2 Stability………...25

3.2 Low Noise Amplifier Architecture Analysis

Chapter 4 UWB CMOS LNA Design

4.1

Design Procedures

4.1.1 Analysis of Input Matching ………32

4.1.2 Analysis of Output Matching………..34

4.1.3 Gain Analyzing………35

4.1.3 Bandwidth Analyzing………..36

4.2 Simulation Results

4.3 Measurements and Conclusions

Chapter 5 Summary

References

Figure Captions

Chapter 1 Introduction

Chapter 2 Basic Concepts in RFIC Design

Figure 2-1 Substrate thermal noise………5

Figure 2.2 Drain induced gate noise………..6

Figure 2.3 Equivalent circuits………7

Figure 2-4 Definition of the 1-dB compression point ……….17

Figure 2-5 Plot of input output power of fundamental and IM3 versus input power..17

Figure 2-6 Cascaded nonlinear stages………..26

Chapter 3 Basic LNA Design

Figure 3-2 Circuit embedded in a 50 ohm system………22

Figure 3-3 Circuit embedded in a 50 ohm system with matching circuit………22

Figure 3-4 Example of a very sample matching circuit network……….22

Figure 3-5 The eight possible impedance-matching networks with two reactive components……….23

Figure 3-7 Equivalent noise model of Figure 3-1………26

Chapter 4 UWB CMOS LNA Design

Figure 4-2 Chip layout……….32

Figure 4-3 simplification of the first stage………...33

Figure 4-4 the input impedance Zin………..33

Figure 4-5 the current buffer………34

Figure 4-6 Current-reused two stage cascade amplifier with series inter-stage resonance………..35

Figure 4-7 Small signal equivalent representation of the circuit from node X to Y…35 Figure 4-8 the gain of the circuit………..37

Figure 4-9 Simulated S11……….38

Figure 4-10 Simulated S22………...39

Figure 4-11 Simulated S21………...39

Figure 4-12 Simulated S12………...40

Figure 4-13 Simulated NF………40

Figure 4-14 Simulated stability………41

Figure 4-15 simulated IIP3………...42

Figure 4-17 Measured S11………..44

Figure 4-18 Measured S22………...45

Figure 4-19 Measured S12………..45

Figure 4-20 Measured noise figure………..46

Figure 4-21 Measured linearity………46

Chapter 1

Introduction

---

1.1 UWB CMOS Receivers

UWB (Ultra Wideband) is a new wireless technology capable of

transmitting data over a wide frequency bands with low power and high data rates. It

communicates with short pulses on the order of nanoseconds, thus spreading the

energy of the radio signal over a very wide bandwidth. Compared to traditional

narrow band communication systems, UWB technology has the promising ability to

provide high data rate at low cost with relatively low power consumption.

The FCC has allocated 7.5 GHZ of spectrum for unlicensed use of UWB devices in

the 3.1 to 10.6 GHZ frequency band. The low noise amplifier needs to amplify the

received UWB signal with sufficient gain and as little as possible. From Shannon’s

equation C = B log (1+

BNo BSo

= ) for the channel capacity, we know that a UWB

wireless network, the bandwidth will likely be much higher than the data rate, so that

the system can operate at very low signal to noise ratio[1].

The majority implementation of the RF integrated circuit used for wireless

devices are encounter with various possibilities: CMOS, Bi CMOS, and GaAs

We just focus on the CMOS technology, CMOS process reduce the minimum channel

length from the present years, so the unity gain cut off frequency (ft ) is increasing.

For example, a deep sub-micron prototype CMOS technology has realized devices

with ft exceeding 100 GHz [2] and minimum noise figures less than 0.5-dB at 2 GHz.

The more commercially available sub-micron CMOS technologies have display ft’sof

20GHz and minimum noise figures of 1.6-dB at 2 GHZ [3]. The VLSI capabilities of

CMOS make it proper to very high levels of mixed signal radio integration while

increasing the functionality of a single chip radio to cover multiple RF standards [4].

Due to the advancement of circuit design technology, circuit size is small and cost

down consideration. With low cost and low power devices of RF front-end system

implemented by CMOS technology, the prospect of a single chip CMOS system has

received considerable interest. Even the SOC is difficult and hard to implement at this

time, but a set of separate chips in the same CMOS technology may bring significant

1.2 motivation

For portable wireless communication devices has given great push to the

development of a next generation of low power radio frequency integrated circuits

(RFIC) product. Such as wireless phones, cordless and cellular, global positioning

satellite (GPS), pagers, wireless modems, wireless local area network (LAN), and RF

ID tags, etc., require more low cost, low noise and high power efficiency solutions to

supply the demand for low-price product [6].

Chapter 2 discusses the basic concepts in RF design. Chapter 3 presents

the basic low-noise amplifiers design for UWB. Chapter 4 discusses the design

procedures of this circuit by using of the band pass filter , the current buffer

configuration, the shunt-LC resonance, Current-Reused Technique to get a good

input and output matching, broadband, a low power consumption, and also reveals

Chapter 2

Basic Concepts in RFIC Design

---2.1 Noise Sources in MOSFETs

2.1.1 Drain Current Noise

There are three main sources which contribute the thermal noise of

MOSFETs [7]. And the dominate noise source of RF MOSFETs is the drain current

noise which is expressed as:

i

=

KT

g

Δ

f

2

₄

_γ

(2.1) where gd0 is the drain-source conductance at zero VDS. The coefficient γ has a vale of

unity at zero VDS and, in long channel devices, decrease toward a value of 2/3 in

saturation [8]. Some measurements show that short-channel devices exhibit noise

considerably in excess of values predicted by long-channel theory, sometimes by an

order of magnitude in extreme cases. Some of the literature attributes this excess noise

to carrier heating by the large electric fields commonly encountered in such devices.

In this view, the high fields produce carriers with abnormally high energies. No longer

in quasi-thermal equilibrium with the lattice, these hot carriers produce abnormal

amount of noise. But in contrast to other groups, we find only a moderate

measurements.

2.1.2 Substrate Thermal Noise

substrate

C

R

drain

source

gate

substrate

C

R

drain

source

gate

Figure 2-1 Substrate thermal noise

Figure 2-1 shows a simplified picture of how the thermal noise associated

with the substrate resistance can produce measurable effect at the main terminals of

the devices. At frequencies low enough that we may ignore Ccb (open), the thermal

noise of Rsub modulates the potential of the back gate, contributing some noisy drain

current:

i

_nd

2

_,

_sub

=

4

KTR

_sub

g

_mb

2

Δ

f

effective substrate resistance and size of the back-gate transconductance – the noise

the ordinary channel charge. In this regime, layout strategies that reduce the substrate

resistance have a noticeable and beneficial effect on noise.

At frequencies well above the pole formed by Ccb and Rsub, however,

the substrate thermal noise becomes unimportant, as is readily apparent from

inspection of the physical structure and the corresponding frequency-dependent

expression for the substrate noise contribution[8]:

f

C

R

g

KTR

i

=

₊

Δ

)

(

1

4

ω

The characteristics of many IC processes are such that this pole is often around 1 GHz.

Excess noise produced by this mechanism consequently will be most noticeable

below about 1 GHz.

2.1.3 Drain Induced Gate Noise

2 ng

i

drain

source

gate

i

drain

source

gate

2 ng

i

g

C

i

g

C

Figure 2.3 Equivalent circuits

In addition to drain noise, the thermal agitation of channel charge has

another important consequence: gate noise. The fluctuating channel potential couples

capacitively into the gate terminal, leading to a noisy gate current (see Figure 2-2).

Noisy gate current may also be produced by thermally noisy resistive gate material.

But this noise source will be separately discussed later, even though it is more and

more important in nano-scale devices. Although the drain-induced-gate-noise is

negligible at low frequencies, it can dominate at radio frequencies. Van der Ziel has

shown that the drain-induced-gate-noise may be expressed as:

i

=

4

KT

δ

g

Δ

f

0 2 2

5

g

C

g

=

ω

channel devices [8].

connected between gate and source, shunted by a noise current source (see Figure 2-3).

This noise current clearly has a spectral density that is not constant. In fact, it

increases with frequency, so perhaps it ought to be called “blue noise” to continue the

optical analogy. Because the drain thermal current noise and the

drain-induced-gate-noise do share a common origin, they are correlated. That is, there

is a component of the gate noise current that is proportional to the drain noise current

on an instantaneous basis.

Although the noise behavior of long-channel devices is fairly well

understood, the precise behavior of δ and γ in the short-channel regime is still

unknown at present. That’s why we have to do more research on the thermal noise of

MOSFETs. Thermal noise of deep sub-micrometer MOSFETs has received

considerable attention lately, which is mainly triggered by publications that report a

severe enhancement of the thermal noise with respect to long-channel theory [9]-[10].

In the earliest of these publications [9], thermal noise was found to be enhanced by a

factor up to 12 in n-channel devices with 0.7μm gate length and hot electrons were

proposed to explain these results. Evidently, the reported noise enhancements would

seriously limit the viability of RF CMOS and a detailed study is called for. Therefore,

in this paper, we perform an extensive study of the RF noise in 0.18μm RF CMOS

2.2 Noise Analysis

2.2.1 The Concept of Noise Figure

Noise is usually generated by the random motions of charges or charge carriers

in devices and materials. Because the noise process is random, one cannot identify a

specific value of voltage at a particular time, and the only recourse is to characterize

the noise with statistical measures, such as the mean-square or root-mean-square

values. Because of having various noise sources in the circuit, we need to simplify

calculation of the total noise at the output [11]. Obviously, the output-referred noise

does not allow a fair comparison of the performance of different circuits because it

depends on the gain. According the circuit theory, we can use the input-referred noise

of circuits to represent the noise of behavior in the circuits.

The signal-to-noise ratio (SNR), defined as the ratio of the signal power to the

total noise power, is an important parameter. In RF circuit, most of the front-end

receiver blocks are characterized in terms of their “noise figure” rather than the

input-referred noise. Noise figure has many different definitions. The most commonly

accepted definition is noise figure

out in SNR

SNR

= , (2.6)

Noise figure is a measure of how much the SNR degrades as the signal passes through

a circuit. If a circuit has no noise source, the SNRout = SNRin, regardless of the gain.

input. Thus, for reliable detection, the previously calculated minimum detectable

signal level must be modified to include the noise from the active circuitry. Noise

from the electronics is described by noise factor F, which is a measure of how much

the signal-to-noise ratio is degraded through the system. We note that

S

G

S

where is the input signal power, is the output signal power, and is the

power gain

i

S S_o G

i o S

S . We derive the following equation for the noise factor:

) ( ) ( 0 ) ( ) ( source i total total o o source i i o i

N

G

N

N

S

N

S

SNR

SNR

F

⋅

=

=

=

where is the total noise at the output. If is the noise at the output

originating at the source, and is the noise at the output added by electronic

circuitry, then we can write:

) (total o N N_o(source) ) (added o N ) ( ) ( )

(total o source o added

o

N

N

N

=

+

Noise factor can be written in several useful alternative forms:

) ( ) ( ) ( ) ( ) ( ) (

1

N

N

N

N

N

G

N

F

=

=

+

⋅

=

This shows that the minimum possible noise factor, which occurs if the

electronics add no noise, is equal to 1.Noise figure NF is related to noise factor F by

F

NF

=

10

log

an electronic system that adds no noise has a noise figure of 0 dB.

In the receiver chain, for components with loss (such as switches and filters),

the noise figure is equal to attenuation of the signal. For example, a filter with 3 dB of

loss has a noise figure of 3 dB. This is explained by noting that output noise is

approximately equal to input noise, but signal is attenuated by 3 dB. Thus, there has

degradation of SNR by 3 dB [12].

2.2.2 Linearity in RF Circuits

Mathematically, any nonlinear transfer function can be written as series

expansion of power terms unless the system contains memory. While many RF

circuits can be approximated with a linear model to obtain their response to small

signals, nonlinearities often lead to interesting and important phenomena. For

simplicity, we assume that:

...

+

+

+

+

=

k

k

v

k

v

k

v

v

One common way of characterizing the linearity of a circuit is called the

two-tone test. In this test, an input consisting of two sine waves is applied to the

circuit. 2 1 2 2 1 1

cos

t

v

cos

t

X

X

v

v

=

ω

+

ω

=

+

number of terms:

(

)

_

(

)

_

(

)



X

X

k

X

X

k

X

X

k

k

v

=

+

+

+

+

+

+

(

)

(

)

(

)

3

3

2

X

X

X

X

X

X

k

X

X

X

X

k

X

X

k

k

v

+

+

+

+

+

+

+

+

+

=

These terms can be further broken down into various frequency components.

For instance, the term has a zero frequency (dc) component and another at the

second harmonic of the input:

2 X₁

(

v

t

)

v

(

t

X

1

cos

2

2

cos

ω

=

+

ω

=

)

N

The second-order terms can be expands as follows:

(

)

_N

2

X

X

X

X

X

X

+

+

=

+

_

where second-order terms are composed of second harmonics HD2, and mixing

components, here labeled IM2 for second-order intermodulation. The mixing

components will appear at the sum and difference frequencies of the two input signals.

Note also that second-order terms cause an additional dc term to appear.

The third-order terms can be expanded as follows:

(

)

_N

_N

3

3

X

X

X

X

X

X

X

X

+

+

+

=

+

_

_

Third-order nonlinearity results in third harmonics HD3 and third-order

intermodulation IM3. Expansion of both the HD3 and IM3 terms shows output signals

appearing at the input frequencies. The effect is that third-order nonlinearity can

change the gain, which is seen as gain compression. This is summarized in Table 2.1.

Note that in the case of an amplifier, only the terms at the input frequency are

desired. Of all the unwanted terms, the last two at frequencies 2ω1−ω2 and

1 2

2ω −ω are the most troublesome, since they can fall in the band of desired output if

1

ω is close in frequency to ω and therefore cannot be easily filtered out. These two 2

tone are usually referred to as third-order intermodulation terms (IM3 products)

2.2.3 Third-Order Intercept point and The 1-dB Compression Point

One of the most common ways to test the linearity of a circuit is to apply

two signals at the input, having equal amplitude and offset by some frequency, and

plot fundamental output and intermodulation output power as function of input power

as show in Figure 2-5. From the plot, the third-order intercept point (IP3) is

determined. The third-order intercept point is a theoretical point where the amplitudes

of the fundamental tones at 2ω1−ω2 and 2ω2−ω1 are equal to the amplitudes of

the fundamental tones at ω and 1 ω . 2

fund= 1 3 3

4

9

k

v

v

k

+

The linear component of (2.19) given by

fund=

k

v

IM3= 3 3

4

3

v

k

The small , the fundamental rise linearity (20dB/decade) and that the

IM3 terms rise as the cube of the input (60dB/decade). A theoretical voltage at

which these two tones will be equal can be defined:

i v

1

4

3

=

v

k

v

k

This can be solved for v_IP3 :

3 1 3

3

2

k

k

v

=

That (2.23) gives the input voltage at the third-order intercept point. The

input power at this point is called the input third-order intercept point (IIP3). If IP3 is

specified at the output, it is called the output third-order intercept point (OIP3).

The third-order intercept point cannot actually be measured directly, since

it is useful to describe a quick way to extrapolate it at a given power level. Assume

that a device with power gain G has been measured to have an output power of at

the fundamental frequency and a power of at the IM3 frequency for a given input

power of , as illustrated in Figure 2-5. On a log plot of and versus , the

IM3 terms have a slope of 3 and the fundamental terms have a slope of 1. Therefore,

1 P 3 P i P P₃ P₁ Pi

1

3

3

₌

−

−

P

IIP

P

OIP

3

3

3

₌

−

−

P

IIP

P

OIP

since subtracation on a log scale amounts to division of power.

Also note that

i

P

P

IIp

OIP

G

=

3

−

3

=

−

These equations can be solved to given

[

]

[

]

2

1

2

1

3

P

P

P

G

P

P

P

IIP

=

+

−

−

=

+

−

In addition to measuring the IP3 of a circuit, the 1-dB compression point

(Figure 2-4) is another common way to measure linearity. This point is more directly

measurable than IP3 and requires only one tone rather than two. The 1-dB

compression point is simply the power level, specified at either the input or the output,

where the output power is 1dB less than it would have been in an ideally linear device.

2.3 Cascaded Nonlinear Stages

Since in RF systems, signals are processed by cascaded stages, it is

important to know how the nonlinearity of each stage is referred to the input of the

cascade. Consider two nonlinear stages in cascade, as shown in Figure2-6. Assuming

that the input-output relationship is

(

)

(

)

(

)

(

)

t

x

t

x

t

x

t

y

=

α

+

α

+

α

(

)

(

)

(

)

(

)

t

y

t

y

t

y

t

y

=

β

+

β

+

β

Substitute (2.28) into (2.29) results in the relation

)

(

)

2

(

)

(

)

(

t

x

t

x

t

y

=

α

β

+

α

β

+

α

α

β

+

α

β

If we consider only the first- and third-order terms, then

3 3 1 2 2 1 1 3 1 1 3

2

3

4

β

α

β

α

α

β

α

β

α

+

+

=

A

From equation (2.31) can be simplified if the two sides are inverted and squared:

2 , 3 2 2 1 2 2 1 , 3 2 3 2 1

2

3

1

1

A

A

A

α

β

β

α

₊

+

=

where AIP3,1 and AIP3,2 represent the input IP3 points of the first and second stages,

respectively. From the above result, we note that as α increases, the overall IP1 3

decreases. This is because with higher gain in the first stage, the second stage senses

Figure 2-4 Definition of the 1-dB compression point

1 3,

IIP

IIP

Figure 2-6 Cascaded nonlinear stages

Table 2.1

Frequency Component Amplitude

dc

₍

₎

Chapter 3

General Consideration in LNA Circuit Design

---

3.1 Low Noise Amplifier Basic

Low noise amplifier is the first gain stage in the receive path so its noise

figure directly adds to that of the system. Therefore, there are several common goals

in the design of LNA. These include minimizing noise figure of the amplifier,

providing enough gain with sufficient linearity and providing a stable 50 ohm input

impedance to terminate an unknown length of transmission line which delivers signal

from antenna to the amplifier [9]. Among LNA architectures, inductive source

degeneration is the most popular method since it can achieve noise and power

matching simultaneously, as shown in Figure 3-1. The following analysis in 3.2 is

based on this architecture. The LNA basic considerations are introduced as follows.

3.1.1 Impedance Matching Network

The need for impedance matching network becomes more important. In order to

deliver maximum power to a load, it must be properly terminated at both the input and

the output ports. The input impedance of a circuit can be any values in order to have

the best power transfer into the circuit. It is necessary to match this impedance to the

impedance of the source driving the circuit. The output impedance also must be

similarly matched in order to deliver maximum power to the 50 ohm load, it must

have the terminations ZS and ZL. The input matching network is designed to

transforms the generator impedance to the source impedance ZS, and the output

matching network transforms the 50 ohm termination to the load impedance ZL.

Consider the RF system shown in Figure 3-2. Here the source and load terminations

are 50ohm, as the transmission lines leading up to the circuit for optimum power

transfer, prevention of ringing and radiation, and good noise behavior. For example,

we needs the circuit input and output impedances matched to the system. In general,

some matching circuit must almost always be added to the circuit, as shown in Figure

3-3.Typically, reactive matching circuits are used because they are lossless, adding no

noise to the circuit, and will only be matched over a range of frequencies and not at

others. If a broadband matching is required, then other techniques may need to be

in Figure 3-4. The series inductance adds an impedance of jωL to cancel the input

capacitive impedance. Note that, in general, when the impedance is complex

(

)

jX R+

(

)

The input, output impedance of a circuit is very common in using reactive

components to achieve impedance transformation, as they will not absorb any power

or add any noise. Thus, series or parallel inductance or capacitance can be added to

the circuit to provide an impedance transformation. Series components will move the

impedance along a constant resistance circle on the Smith Chart. Parallel components

will move the admittance along a constant conductance circle. Table 3.1 summarizes

the effect of each component.

With the proper choice of two reactive components, any impedance can be

moved to a desired point on the Smith Chart. There are eight possible

two-components matching networks, also known as Ell networks, as shown in Figure

3-5. Each will have a region in which a match is possible and a region in which a

Figure 3-2 Circuit embedded in a 50 ohm system

Figure 3-3 Circuit embedded in a 50 ohm system with matching circuit

Figure 3-5The eight possible impedance-matching networks with two

Table 3.1

Component Added Effect Description of Effect

Series inductor z→ z+ jωL Move clockwise along a resistance

circle

Series capacitor z → z− j ωC

Smaller capacitance increases impedance

(

)

counterclockwise along a conductance circle

Parallel inductor y → y− j ωL

Smaller inductance increases admittance

(

)

counterclockwise along a conductance circle

Parallel capacitor y→ y+ jωC

Move clockwise along a conductance circle

3.1.2 Stability

The stability of an amplifier is a very important consideration in a design and

can be determined from the S parameters, the matching networks, and the

terminations. A two-port network to be unconditionally stable can be derived from

(3.1) to (3.4) .

1

<

Γ

1

<

Γ

1

1

₋

_Γ

<

Γ

+

=

Γ

S

S

S

S

1

1

₋

_Γ

<

Γ

+

=

Γ

S

S

S

S

The two-port network is shown in Figure 3-6. For unconditional stability any

passive load or source in the network must produce a stable condition. The solution of

(3.1) to (3.4) gives the required conditions for the two-port network to be

unconditionally stable [4]. 21 2 1 2 2 2 2 2 11

2

1

S

S

S

S

k

=

−

−

+

Δ

S

S

S

S

−

=

Δ

unconditional stability is

k

>

1

1

<

Δ

E

Z

Γ

Γ

Z

T w o - p o r t

n e tw o r k

Γ

Γ

Z

Z

Figure 3-6 Stability of two-port networks

3.2 Low Noise Amplifier Architecture Analysis

gs C 2 ngu i vgs gmvgs i_nd2 2 Rg v -+ 2 ngc i g R l R g L s L s R 2 Rl v 2 s v 2 out i

Figure 3-7 Equivalent noise model of Figure 3-1

In Figure 3-7, the input impedance can be expressed as

gs s g o s T s gs m s gs m gs s g in C L L at L L C g L C g sC L L s Z ) ( 1 1 ) ( + = = ≈ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + + = ω ω ω (3.9)

frequency of the device and source inductance at resonant frequency. Therefore it can

be set to 50 ohm for input matching while resonant frequency is designed to be equal

to the operating frequency.

According to prior introduction, the equivalent noise model of common-source

LNA with inductive source degeneration can be expressed as Figure 3-7, where

is the parasitic resistance of the inductor and is the gate resistance of the device.

Note that the overlap capacitance C

l

R

g

R

gd has also been neglected in the interest of

simplicity. Then the noise figure can be obtained by computing the total output noise

power and output noise power due to input source. To find the output noise, we first

evaluate the trans-conductance of the input stage. With the output current proportional

to the voltage no Cgs and noting that the input circuit takes the form of series-resonant

network, the transconductance at the resonant frequency can be expressed as

s o T s T s gs o m in m m R L R C g Q g G ω ω ω ω ( + ) = 2 = = (3.10)

where Qin is the effective Q of the amplifier input circuit. So the output noise power

density due to the source can be expressed as

2 2 2 2 . , ) 1 ( 4 ) ( s s T s o T eff m Rs o Rs a R L R kT G S S _ω ω ω ω + = = (3.11)

2 2 2 2 , , ) 1 ( ) ( 4 ) ( s s T s o T l g o R R a R L R R R kT S l g ω ω ω ω + + = (3.12)

Furthermore, channel current noise of the device is the dominant noise

contributor, and its noise power density associated with the correlated portion of the

gate noise can be expressed as

2 , , ) 1 ( 4 ) ( s s T do o i i a R L g kT S ngc nd ω γκ ω + = (3.13)

where γ is the coefficient of channel thermal noise, α =g_m/g_d0 and

2 2 2 5 2 1 5 ⎥_⎦ ⎤ ⎢ ⎣ ⎡ + + = γ δα γ δα κ c cQ_L (3.14) gs s o L C R Q ω 1 = (3.15)

The last noise term is the contribution of the uncorrelated portion of the gate

noise, and its output noise power density can be expressed as

2 , ) 1 ( 4 ) ( s s T do o i a R L g kT S ngu ω γξ ω + = (3.16) where ) 1 )( 1 ( 5 2 2 2 L Q c + − = γ δα ξ (3.17)

According to equations (3.11), (3.12), (3.13) and (3.16), the noise figure at the

resonant frequency can be expressed as

⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + + + = T o L s g s l Q R R R R F ω ω α γχ 1 (3.18)

where ) 1 ( 5 5 | | 2 1+ c Q_L 2 + 2 +Q_L2 = γ δα γ δα χ (3.19)

From equation (3.19), we observe that χ includes the terms which are

constant, proportional to , and proportional to . It follows that equation (3.19)

will contain terms which are proportional to as well as inversely proportional to

. A minimum noise figure, therefore, exits for a particular .

L Q Q_L2 L Q L L Q Q

Chapter 4

UWB CMOS LNA Design

---

4.1 Design Procedures

This architecture is for an Ultra-Wideband CMOS LNA with

Current-Reused Technique for 3.1 to 10.6 GHZ. It has an advantage of high gain, low

power consumption, low noise performance and small size. We utilize three-stage

amplifier to get a flat gain at high frequency. The first stage introduces the band pass

filter for input matching, it includes two inductances, one capacitor and one

inductance at gate. The second stage introduces a current-reuse cascaded

common-sources structure to lower power consumption. The last stage introduces LC

in shunt connection to improve gain and bandwidth for high frequency. The current

buffer configuration is used for output matching. Its circuit diagram is shown in

Figure 4-2 Chip layout

4.1.1 Analysis of Input Matching

In input part, we adopt a common-source amplifier, by introducing

matching components to let the frequency resonate at which we want. We also

1 1 1 1 1 1 1

1

L

C

g

)

L

s(L

sC

Z

=

+

+

+

In addition, we put a shunt-LC resonance in input part, following with the

equivalent circuit Z1, to make it have a good resonance in the imagine part, and get

real part impedance-matching

(R

=g

L

/C

)

we can get the input matching impedance Zin in equation (4.2).

1 2 2 1 2 2 ) 1 // ( ) 1 // ( Z sC sL Z sC sL Z_in + = (4.2)

We can also keep a very low noise to procure a band-pass amplifier for an entire

Ultra-Wideband.

A

Z1

Figure 4-3 simplification of the first stage

4.1.2 Analysis of Output Matching

The current buffer configuration is used for output matching as shown in

Figure4-5，and make the entire frequency matching to 50 Ω.In this circuit, M3 is the

source follower, and the steady current of M3 is provided by M4.We only need to

control the supply voltage and the size of the transistor, and then a good output

matching will be obtained as equation below.

3 4 3

1

||

1

g

r

g

Z

=

≈

4.1.3 Gain Analyzing

Figure 4-6 Current-reused two stage cascade amplifier with series inter-stage resonance

Figure 4-7 Small signal equivalent representation of the circuit from node X to Y

In Figure 4-6 is the Current-reused two stage cascade amplifier with

series inter-stage resonance, and the Small signal equivalent representation of the

circuit from node X to Y is in Figure 4-7. If we divide id2 to id1, we can get the gain as in equation (4.4). (4.4) 2 2 2 2 / _S R id +

so we can see that resonates with at high frequency

2 2 2 2 1 2 ) / 1 1 ( _{g gs LS} gs m sL sC sC L L sC g id + + + × = g g sC 2 L_S 1/sC ₂ +1/ _s2

and. If provides high impedance, then, we can get 1 2 id id as below. 2 L L₂ >>R_LS2 ω ωT gs m sC g id id ≅ ≅ 2 2 1 2 (4.5)

where is M2’s cutoff frequency, is the operation frequency. ωT ω

4.1.4 Bandwidth Analyzing:

In order to get a low power consumption low noise amplifier LNA, we

cascade the second amplifier M2 on the first amplifier M1 to use the same dc current

to achieve the goal of power saving. Besides we also utilize substrate bias at M1 to

enhance the gain, at the same time reduce the power consumption.

For gain and the bandwidth, we utilize three-stage amplifier to achieve a

high gain and the flat bandwidth design. In the circuit, the requirement of the

current-reused structure is Coupling capacitor (C2) which is connected to the output of

the first stage amplifier (at drain) and also connected to the input of the stage second

stage amplifier (at gate) .Therefore it can provide signal coupling between the two

stages and the Bypass capacitor (Cbypass) functions as an ac ground at the source of

transistor M2, for avoiding the coupling effect to the first stage. Aside from, we join

the shunt-LC resonance CB and LB, by this LC resonance the bandwidth and the gain

can be improve a lot in order to get a high gain Ultra-Wideband circuit. In Figure 4-8,

4.2 Simulation Results

Figure 4-9 shows the Return loss Simulation. S11 is lower than -9.4dB

between 3.1 and 10.6GHz. The output buffer achieves excellent matching such that

S22 is lower than -11dB from 3.1GHz to 10.6 GHz in Figure 4-10. Figure 4-11 is the

power gain versus frequency, the gain at 3.1GHz is 13.567dB and at 10.6GHz is

13.319, so the different between the wideband is only 0.25dB.The reverse isolation

S21 is lower than -38dB shown in Figure 4-12. The noise figure (NF) of this UWB

LNA is shown in Figure 4-13.The NF at 3.1GHz is 2.686dB, at 10.6GHz is 2.842dB

and the minimum noise figure (NFmin) at 5.7GHz is 2.146dB. The stability factor

4-14.The third-order intermodulation distortion(IIP3) is -3dBm and shown in Figure

4-15 ,the test is performed at 4 GHz. These results imply excellent linearity of our

LNA. The proposed UWB LNA dissipates 10.3mW with a power supply of 1.8V.

Figure 4-10 Simulated S22

Figure 4-12 Simulated S12

Figure 4-15 simulated IIP3

4.3 Measurements and Conclusions

The following Figure4-16 ~ Figure4-21 are the measurement result which

are slightly different from simulation. Which imply good accuracy of simulation and

good circuit design. But the gain dropping at high frequency (in Figure 4-16) is due to

The bandwidth of this work with considering matching and gain is from

3.1 to 10.6 GHz, while the average gain is about 10dB. Figure 4-17 and Figure 4-18

show the measurement results of S11 and S22. Input and output matching are

achieved very well from 3.1 to 10.6 GHz, so S11 can bellow -9dB and the S22 can

bellow -11dB.S12 below up to -33dB in Figure 4-19. The noise figure is about 3.6

shown in Figure 4-20.The noise performance is very flat and the minimum noise

figure is 2.85dB at 5GHz. The noise figure can be better if we solve the resistor

parasitic. The linearity of the third-order intermodulation distortion(IIP3) is -3dBm

as measurement and shown in Figure 4-21. Figure 4-22 shows the die photo of this

circuit. Total power consumption is 10.3 mW which the Vdd is 1.8V.In the chip, the apply Vb is 0.1V, Vg1 is 0.61V and Vg2 is 0.61V. Table 4.1 is the measurement result summary. By the band pass filter, the current buffer configuration, the shunt-LC

resonance, Current-Reused Technique we proposed, a good input and output matching,

broadband, a low power consumption LNA is developed for UWB system

3 4 5 6 7 8 9 10 2 11 0 5 10 -5 15 freq, GHz d B (S (2 ,1 )) Figure 4-16 Measured S21 3 4 5 6 7 8 9 10 2 11 -25 -20 -15 -10 -30 -5 freq, GHz d B (S (1 ,1 )) Figure 4-17 Measured S11

3 4 5 6 7 8 9 10 2 11 -22 -20 -18 -16 -14 -24 -12 freq, GHz d B (S (2 ,2 )) Figure 4-18 Measured S22 3 4 5 6 7 8 9 10 2 11 -38 -36 -34 -40 -32 freq, GHz d B (S (1 ,2 )) Figure 4-19 Measured S12

0 5 10 15 2 3 4 5 6 7 8 9 10 11

Freq,GHZ

NF(dB)

Figure 4-20 Measured noise figure

Input Power (dB)

Output Power (dB)

--

3

3

Figure 4-22 Die photo

B.W

(GHz)

Gain

(dB)

NF

(dB)

S11

(dB)

S22

(dB)

IIP3

(dBm)

Pdc

(mW)

3.1~10.6

10

3.6

< -9

< -13

-3

10.3

Chapter 5

Summary

---By the Current-Reused Technique for 3.1 to 10.6GHZ we proposed, a good

input and output matching, broadband, a low power consumption amplifier is

developed for UWB system applications.

Table 5.1 is the comparison of broadband LNA performance. We can find out

by this table, by using Current-Reused Technique and shunt-LC resonance, can pull to

being wide very big arrival 3.1~10.6GHz frequently. All the advantages are important

for UWB system considerations.

specifications This work Ref. [14] Ref. [15] Ref. [16] Ref. [17] Process 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm Frequency (GHz) 3.1~10.6 2.4~9.5 2~4.6 2~6.5 3.1~10.6 S11 (dB) <-9 <-9 <-9 <-7.8 <-8 S22 (dB) <-13 <-20 <-10 <-16 ---- Gain (dB) 10 9.3 9.8 11.9 13.5~16 NF (dB) 2.85~4.5 4~9 2.3~6 4.1~4.6 3.1-6 IIP3 (dBm) -3 -6.7 -7 4 -7 Pdiss (total) (mW) 10.3 18 12.6* 27 11.9 Die size (mm2) 0.89 1.1 0.9 0.88 1.2 Table 5.1 Comparison of broadband LNA performance (*Only core LNA)

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