Measurement Results of Electrical SOA

In this work, electrical SOA (eSOA) is measured by 100-ns TLP pulses when giving a DC voltage for gate bias. The gate bias is varied from 0 V to 5 V. The breakdown voltage (BV_DSS) of the test devices are summarized in Table 3.1. Fig. 3.6 shows the measured eSOA of nLDMOS_S with W = 320μm and X = 0.14μm, 5μm, and 10 μm, respectively. The tests Devices with I_DS from low to high are measured under gate biases of 0, 1, 3, and 5 V. The region of eSOA is slightly extended with a wide drain region when using large distance X. The breakdown voltage for nLDMOS_S is about 77 V. Next, the eSOA of nLDMOS_A and nLDMOS_B are shown in Fig. 3.7 and Fig. 3.8, respectively. Their eSOA can be obviously extended with large distance X. The breakdown voltage for nLDMOS_A and nLDMOS_B is about 53 V and 74 V, respectively. According to the comparison of different eSOA with nLDMOS_S, nLDMOS_A, and nLDMOS_B in Fig. 3.9, the eSOA of nLDMOS_A is the greatest; in contrast, the eSOA of nLDMOS_S is the worst. The nLDMOS_B with slotted DPW structure can have a better eSOA than nLDMOS_S.

Although the breakdown voltage of nLDMOS_A is lower than 60 V, its eSOA is the widest region.

TABLE 3.1

The measured breakdown voltage (BVDSS) with different test devices

(a)

(b)

(c)

(d)

Fig. 3.6 The I-V characteristics of nLDMOS_S with different distance X of (a) 0.14μm, (b) 5μm, and (c) 10 μm, respectively, measured by 100-ns TLP system. (d) The eSOA of nLDMOS_S with different distance X.

(a)

(b)

(c)

(d)

Fig. 3.7 The I-V characteristics of nLDMOS_A with different distance X of (a) 0.14μm, (b) 5μm, and (c) 10 μm, respectively, measured by 100-ns TLP system. (d) The eSOA of nLDMOS_A with different distance X.

(a)

(b)

(c)

(d)

Fig. 3.8 The I-V characteristics of nLDMOS_B with different distance X of (a) 0.14μm, (b) 5μm, and (c) 10 μm, respectively, measured by 100-ns TLP system. (d) The eSOA of nLDMOS_B with different distance X.

(a)

(b)

(c)

Fig. 3.9 The comparison of measured eSOA with nLDMOS_S, nLDMOS_A, and nLDMOS_B.

3.3.2TLP-Measured Results and ESD Robustness

The following is the ESD experimental results of different test devices. Fig. 3.10

~ 3.12 show the TLP-measured results under the same condition of V_GS = 0 V. The solid line presents the TLP-measured I-V curves while the dotted line is the leakage current which is measured after every TLP stress pulse. The data of trigger voltage (Vt1), trigger current (It1), holding voltage (Vhold), and secondary breakdown current (It2) are extracted from TLP-measured I-V curves, as shown in Table 3.2. According to the TLP-measured I-V characteristics, no snapback region is observed in these test devices. The tests devices immediately failed as the snapback happened. As a result, the data of trigger voltage and trigger current are not available. The test device nLDMOS_S has ESD levels of 0.3 kV ~ 0.5 kV in HBM tests, below 50 V ~ 50V in MM tests, and It2 of 0.085 A ~ 0.15 A in TLP measurement with different distance X.

Next, the test device nLDMOS_A has ESD levels of 0.5 kV ~ 0.8 kV in HBM tests, 50 V ~ 100V in MM tests, and It2 of 0.16 A ~ 0.27 A in TLP measurement with different distance X. Moreover, the test device nLDMOS_B has ESD levels of 0.5 kV

~ 0.7 kV in HBM tests, 50 V ~ 100V in MM tests, and It2 of 0.14 A ~ 0.25 A in TLP measurement with different distance X. The ESD performance of test devices can be improved with a large distance X of 10 μm. Compared with the measured results in Table 3.2, the ESD performance of nLDMOS_A is the greatest; on the contrary, nLDMOS_B is the worst.

Fig. 3.10 TLP-measured I-V characteristics of nLDMOS_S with different distance X of 0.14μm, 5μm, and 10 μm.

Fig. 3.11 TLP-measured I-V characteristics of nLDMOS_A with different distance X of 0.14μm, 5μm, and 10 μm.

Fig. 3.12 TLP-measured I-V characteristics of nLDMOS_B with different distance X of 0.14μm, 5μm, and 10 μm.

TABLE 3.2

The TLP-measured results and ESD robustness with different test devices

Device

As shown in Fig. 3.13, the similar report showed that a 50-V RESURF nLDMOS had increased TLP-measured It2 with a deep drain profile engineering [17]. In the deep drain case, a deep n+ sinker was implanted below the drain junction and overlaps it so that the connection from NBL to drain was accomplished internally.

The effective drift length of the deep drain device was the same as the shallow drain case. The breakdown voltage for the deep drain device showed a slightly degraded tradeoff compared with the shallow drain case. In the deep drain structure, the parasitic BJT current could flow vertically into the NBL region. The vertical bipolar current was spread almost along the entire length of the device cross section, resulting in a significant reduction of the power density. The sharp localized temperature increase near the drain junction was thus avoided. Hence, the TLP-measured It2 of a deep drain device that was higher than in the shallow drain device could be obtained.

Shallow Drain Deep Drain

(a)

(b)

Fig. 3.13 (a) The cross-sectional view and (b) TLP-measured I-V characteristics of RESURF LDMOS device with shallow drain and deep drain [17].

In this work, the parasitic BJT of 60-V nLDMOS still cannot be turned on even if the DPW structure is totally erased in the test results of nLDMOS_A. The most likely reason for the difficulty of turn-on issue is the extremely low base resistance in parasitic BJT path. The base resistance is reduced dramatically with the HVPB structure. As a result, the parasitic BJT path cannot be turned on efficiently after breakdown happens.

3.4.2 Summary

The test devices for study of self-protected HV MOSFET have been investigated with the modified DPW structure in a 60-V BCD process. According to the measurement results, nLDMOS_B with slotted DPW structure can maintain high breakdown voltage and get win-win solution for wide SOA and better ESD robustness at the same time. However, the ESD robustness still cannot be improved effectively in this work due to the lack of parasitic BJT path. To protect the HV devices against ESD stresses, the extra ESD clamp circuit should be additionally added outside the internal circuits.

Chapter 4

Study of ESD Protection Circuits and