TLP-Measured Results and ESD Robustness

ESD robustness of the ESD clamp circuit is measured by TLP, HBM, and MM tests. A pulse width of 100 ns and a rise time of 10 ns are used in the TLP measurement setup. The failure criterion for It2 measurement is determined by leakage current which is greater than 1μA under voltage bias of 16 V. The voltage steps of TLP test are applied with 1 V. The TLP It2 of M_ESD is measured with 3 samples for double-check. The HBM and MM levels of the ESD clamp circuit are measured by the ESD tester, and the failure criterion is defined as the leakage current which is greater than 1 μA under voltage bias of 16 V. The voltage step of HBM test is 500 V, and the voltage step of MM test is 50 V. The HBM level and the MM level of MNESD are measured with 3 samples, respectively.

The experimental results are summarized in Table 2.1, including TLP, HBM, and MM tests. The ESD clamp circuit has ESD levels of over 8 kV in HBM and ~600 V in MM tests. The TLP-measured It2 is around 3.1 ~ 3.58 A. From the correlation equation of 3.58 A × 1.5 kΩ = 5.37 kV, the TLP-measured It2 with 1-V voltage step

has the estimated HBM level of 5.37 kV, which is lower than the ESD level (> 8kV) verified from the HBM ESD tester. The test results have an obvious deviation between TLP and HBM tests.

TABLE 2.1

TLP-measured results and ESD robustness of the gate-driven ESD clamp circuit

With a large deviation between the measured results of TLP test and HBM test, the unusual phenomenon should be studied. Therefore, different voltage steps of TLP tests in identical test circuit of the fabricated ESD clamp circuit are investigated. Fig.

2.4(a), 2.4(b), and 2.4(c) show the TLP-measured I-V characteristics of the gate-driven ESD clamp circuit with different voltage steps of 1 V, 5 V, and 10 V, respectively.Based on the TLP-measured results, the TLP-measured currents of the same ESD clamp circuit are ~1A before the HVM_NESD enters the snapback region. After the snapback occurs, the TLP-measured current is increased greatly when the applied TLP voltage is increased. However, the leakage current after snapback is also slightly increased (before the secondary breakdown point). When a 1-V voltage step is applied in the TLP test, the It2 is 3.58 A. When the voltage step is increased to 5 V, the It2 is increased to 7 A. Finally, with a 10-V voltage step, the It2 can be further increased up to 11.7 A.

The dependency of TLP- measured It2 on the voltage step of TLP test is shown in Fig.

2.5. The TLP-measured It2 was increased when the voltage steps increasing.

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(b)

(c)

Fig. 2.4 TLP-measured I-V characteristics of the gate-driven ESD clamp circuit with different voltage steps of (a) 1 V, (b) 5 V, and (c) 10 V.

Fig. 2.5 Dependency of TLP-measured It2 on the voltage step of TLP test applied to the same ESD clamp circuit.

In the technical literature, a study was ever reported that the GGNMOS in a 43-V CMOS process had different TLP-measured It2 when different stress steps were used on two identical devices [13]. Fig. 2.6 shows the cross-sectional view of 43-V GGNMOS with symmetric structure. As shown in Fig. 2.7, the TLP-measured It2 of 43-V GGNMOS was increased with different pulse density. Low pulse density means large voltage step, and high pulse density means small voltage step. During high-current bipolar operation, the impact ionization hot-spot was located at the N+

diffusion (high injection mode) closely to the FOX bird’s beak. This behavior was also called kirk effect or base-push-out effect [14], [15]. As shown in Fig. 2.6, the red spots were used to represent charge trapping in the field oxide (FOX) at the bird’s beak under ESD stress. Therefore, this leakage increase reflected gradual device degradation when the parasitic BJT operated under high current conditions and was caused by a locally reduced junction breakdown voltage due to charge trapping in the field oxide. In addition, Fig. 2.8(a) showed the simplified TLP-measured I-V characteristics after repeated TLP measurement on the same test device. The trigger voltage was reduced with more and more repeated time. It was attributed to the charge trapped in field oxide which reduced the breakdown voltage locally, represented by the black spot in Fig.

2.8(b). As a result, the ESD stress current was localized at the black spot, preventing uniform conduction through the whole finger of test device and lowering the trigger voltage.

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S D

Fig. 2.6 The cross-sectional view of HV GGNMOS with symmetric structure [13].

Fig. 2.7 The TLP-measured It2 of GGNMOS in a high-voltage CMOS process with different pulse density [13].

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ESD stress current

(b)

Fig. 2.8 (a) The TLP-measured I-V characteristics with decreased trigger voltage in repeated TLP measurement. (b) The top view of charge trapping in the field oxide locally and the distribution of ESD stress current in repeated TLP measurement [13].

Based on the similar concept of the past study, the repeated TLP measurement is applied. The repeated TLP measurement setup is repeating TLP test until snapback without damaging circuit (TLP voltage from 0 V to 50 V in this case). The repeated TLP-measured results are shown in Fig. 2.9. The trigger voltage (Vt1) variation after repeated TLP measurement applied to the same ESD clamp circuit is recorded in Fig.

2.10. It is found that the trigger voltage (Vt1) is slightly decreased from 22 V to 20 V with more and more repeated time. According to the past study, the increased leakage current may reflect the charge trapping in gate oxide. Therefore, leakage current is measured in repeated TLP measurement. As shown in Fig. 2.11, the leakage is increasing with more and more repeated time. After TLP measurement with repeated time of 12, the test device is heated with 10 hours at 200 degrees Celsius to erase the trapped charge in gate oxide. However, the measured leakage current after annealing is increased. It means that the leakage current increasing is not caused by trapped charge. To further investigate this phenomenon, the failure analysis is applied in next part.

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(b)

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Fig. 2.9 TLP-measured I-V characteristics of the gate-driven ESD clamp circuit with different repeated time of (a) 1, (b) 5, and (c) 10.

Fig. 2.10 Vt1 variation after repeated TLP measurement applied to the same ESD clamp circuit.

Fig. 2.11 Leakage current variation after repeated TLP measurement applied to the same ESD clamp circuit.