Motivation

In the age of 1960’s, due to the high cost, large volume, and high power consumption of the magnetic-core memory, the electronic industries urgently needed a new kind of memory device to replace the magnetic-core memory. In 1967, D. Kahng and S. M. Sze invented the first floating-gate (FG) nonvolatile semiconductor memory at Bell Labs [4.1]. To date, the stacked-gate FG device structure continues to be the most prevailing nonvolatile-memory implementation, and is widely used in both standalone and embedded memories. The invention of FG memory impacts more than the replacement of magnetic-core memory, and creates a moment of portable electronic systems. The most widespread memory array organization is the so-called Flash memory, which has a byte-selectable write operation combined with a sector

“flash” erase.

Although a huge commercial success, conventional FG devices have their limitations. The most prominent one is the limited potential for continued scaling of the device structure. This scaling limitation stems from the extreme requirements put on the tunnel oxide layer. On the one hand, the tunnel oxide has to allow quick and efficient charge transfer to and from the FG. On the other hand, the tunnel oxide needs to provide superior isolation under retention and disturbed conditions in order to maintain information integrity over periods of up to a decade. When the tunnel oxide

is thinner for the first consideration, the retention characteristics may be degraded.

And when the tunnel oxide is made thicker to take the isolation into account, the speed of the operation will be slower. Therefore, there is a tradeoff between speed and reliability and the thickness of the tunnel oxide is compromised to about 8-11 nm, which is barely reduced over more than five successive generations of the industry [4.2].

To overcome the scaling limits of the conventional FG structure, Tiwari et al. [4.3]

for the first time demonstrated the Si nanocrystal floating gate memory device in the early nineties. Also, the nanocrystal memory device can maintain good retention characteristics when tunnel oxide is thinner and lower the power consumption [4.3-4.5]. In this letter, we proposed a Ge nanocrystal memory device with 4.5nm-thick tunnel oxide and a low operating voltage of 5V, and a significant threshold-voltage shift due to the charge trapping in the Ge dots is observed.

4.2 Experimental procedures

First, the 6-in Si wafer was cleaned with standard RCA recipes, followed by a thermal oxidation process to form 4.5nm-thick dry SiO2 layer as a tunnel oxide in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Right after the growth of tunnel oxide, poly-Si0.8Ge0.2 was formed on the oxide immediately by low pressure chemical vapor deposition (LPCVD). The deposition of Si0.8Ge0.2 was kept at 550℃ and the pressure was controlled to be 460 mTorr. The flow rate of the reaction gas of SiH4 and GeH4 was 60 and 8 sccm, respectively, and the Ge fraction was analyzed to be around 0.2 by Auger electron spectroscopy (AES). Subsequently, the Si0.8Ge0.2 layer was wet oxidized in an APCVD reactor and the Ge atoms would be segregated downward until they reach the tunnel oxide surface [4.6-4.8]. Then, a rapid

thermal annealing (RTA) at 950℃ in N2 ambient was performed to form the Ge nanocrystals. The melting point of Ge was ~938℃. Therefore, the N2 RTA at 950℃

transformed the Ge layer to liquid phase and the Ge nanocrystals formed after cooling down. In addition, it was well known that during the oxidation of SiGe, GeO2, a weakly bonded molecule, was created. The 950℃ N2 RTA would reduce the Ge atoms and the nanocrystals grew based on the Ostwald ripening mechanism [4.9], in which the larger dots grew at the expense of the smaller dots. From the analysis of transmission electron microscopy (TEM), the control oxide capped on the Ge nanocrystals was estimated to be about 40nm. Also, the sample without Ge nanocrystals was fabricated as a control sample. It is fabricated by depositing a poly-Si layer on the tunnel oxide, followed by the wet oxidation of poly-Si layer, the same process done as the silicon germanium layer. The thickness of the oxide fabricated by oxidizing the poly-Si is measured by n&k analyzer, and fine-tuned to be 40 nm. Finally, the Al electrode was patterned and sintered. The metal-insulator-semiconductor (MIS) structure with Ge nanocrystals embedded between tunnel and control oxide was fabricated. In this work, the formation of Ge nanocrystals is only by one step of oxidation of the silicon-germanium layer, which is simpler than the previous research [4.5] and high-throughput and low cost potentially for industrial consideration.

4.3 Results and discussions

A cross-sectional TEM of an oxide/Ge dots/oxide stacked structure is shown in Fig.

4-1. It is clearly shown the Ge nanocrystals are embedded between tunnel oxide and control oxide, which are oxidized from the Si0.8Ge0.2, and are separated from each other. The insert schematically shows the gate stack arrangement in this study. The

size of the dots is estimated to be about 5.5nm by TEM. She et al. [4.10] made a conclusion on Ge nanocrystal memory device that nanocrystal size around 5nm is preferred to achieve fast programming speed and longer retention time, and the size should not be scaled below that. The quantum confinement effect for Ge nanocrystals smaller than 5nm is very significant so that the retention time is shorter and the programming time is longer. In this work, the fabricated Ge dots satisfy the demand.

Figure 4-2 shows the hysteresis curves of capacitance-voltage (C-V) measurements after a bias sweeping from –5V to 5V. It is found that a low operating voltage, 5V, causes a significant threshold-voltage shift up to ~0.42V, which is enough to be defined as 1 or 0 for the circuit design. Due to the discrete distribution of the Ge dots and Coulomb blockade effect, the capacitance coupling of the nanocrystal memory device is lower than that of the conventional floating gate memory device. If the capacitive coupling is low to the Ge nanocrystals, the threshold-voltage shift may come from the oxide traps. To distinguish the blur, C-V measurement of sample without Ge dots was preformed (not shown therein). It is found after 5-V write operation that there is almost no Vt shift (lower than 0.01V) for the sample without Ge dots. The threshold-voltage shift resulted from oxide traps is thereby negligible. The density of Ge dots can be electrically calculated through the threshold-voltage shift,

∆Vt, by the following expression:

where εox is the permittivity of SiO2, tcontrol the thickness of the control oxide, and Qt is the density of the trapped charge (C/cm² in unit) in Ge nanocrystals. Setting tcontrol = 40nm, ∆Vt = 0.42V, and εox = 3.9×8.85×10^-14 F/cm, the number of electrons trapped in the Ge nanocrystals was calculated to be 2.3×10¹¹ cm^-2. Due to Coulomb Blockade effect, presumably only one electron was trapped in each Ge nanocrystal [4.3, 4.11];

Qt

hence, the aerial density of the Ge dots is about 2.3×10¹¹ cm^-2.

Figure 4-3 (a) shows the leakage current of the gate dielectric with and without Ge nanocrystals under substrate and gate injection bias. It is clearly shown that under substrate injection bias the leakage of the gate oxide stack with Ge nanocrystals is lower than that without Ge dots. It can be deduced that when the first electron enters into the nanocrystal, the effect of Coulomb blockade [4.11] prevents further injection and storage of more electrons and decreases the leakage current. The reduction in leakage current makes the storage of charges more robust and fault-tolerant. That is, therefore, one of the reasons that nanocrystal memory devices exhibit more rugged retention characteristics than conventional FG ones [4.4]. As considering the leakage current under gate injection bias, there is only little difference between the samples with and without Ge dots due to the lack of Coulomb blockade effect. The conduction mechanism among the gate-dielectric stack with Ge dots is inferred from Fowler-Nordheim (F-N) tunneling [4.12] which can be expressed as follows:

where E is the electric field which is defined as the applied voltage divided by total thickness of the tunnel and control oxide, m* the electron effective mass, h the Planck’s constant, φB the energy barrier at the injecting interface (3.1eV for Si-SiO2), and ln(J/E²) is proportional to (1/E). In Fig. 4-3 (b), after the transformation of Fig.

4-3 (a), it is clearly found there is a linear region in high field, which proves the conducting mechanism with Ge dots embedded in the oxide stack is F-N tunneling.

The layer without Ge dots embedded also creates a well-fitted F-N plot at high field, which is not shown therein. Also, the insert exhibits the band diagrams of F-N tunneling for writing and erasing operation in this study.

In addition, to realize the retention characteristics of the structure, a stricter test

⎥⎥

environment of 150 ℃ is conducted [4.13, 4.14]. In Fig. 4-4, the threshold-voltage shift is measured with different periods of time when the sample is heated at 150 ℃.

It is found that the oxide stack with Ge dots embedded retains a good retention property without a significant decline of the memory window, ∆Vt, up to 15 hours, which is robust in the Flash nonvolatile memory technology.

4.4 Conclusion

A nonvolatile memory device embedded with Ge nanocrystal dots is fabricated by the thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing at 950℃

in N2 gas. The tunnel oxide in the nonvolatile memory is controlled to be 4.5 nm-thick and embedded with 5.5-nm Ge nanocrystals. A low operating voltage, 5V, is implemented and a significant threshold-voltage shift, 0.42V, is observed. When the electrons are trapped in the Ge nanocrystals, the effect of Coulomb blockade prevents the injection and storage of more electrons and decreases the leakage current. Also, the retention characteristics are tested to be robust.

A distributed charge storage with GeO

nanodots

Due to the high cost, large volume, and high power consumption of the magnetic-core memory, the electronic industries urgently needed a new kind of memory device to replace the magnetic-core memory in the age of 1960’s. In 1967, D.

Kahng and S. M. Sze invented the first floating-gate (FG) nonvolatile semiconductor memory at Bell Labs. To date, the stacked-gate FG device structure continues to be the most prevailing nonvolatile-memory implementation, and is widely used in both standalone and embedded memories. The invention of FG memory impacts more than the replacement of magnetic-core memory, and creates an era of portable electronic

systems. The most widespread memory array organization is the so-called Flash memory, which has a byte-selectable write operation combined with a sector “flash”

erase.

Although a huge commercial success, conventional FG devices have their limitations. The most prominent one is the limited potential for continued scaling of the device structure. This scaling limitation stems from the extreme requirement put on the tunnel oxide layer. On the one hand, the tunnel oxide has to allow quick and efficient charge transfer to and from the FG. On the other hand, the tunnel oxide needs to provide superior isolation under retention and disturbed conditions in order to maintain information integrity over periods of up to a decade. When the tunnel oxide is thinner for the first consideration, the retention characteristics may be degraded.

And when the tunnel oxide is made thicker to take the isolation into account, the speed of the operation will be slower. There is, therefore, a tradeoff between speed and reliability and the thickness of the tunnel oxide is compromised to about 8-11 nm, which is barely reduced over more than five successive generations of the industry. To overcome the scaling limits of the conventional FG structure, two candidates are mostly mentioned, SONOS and nanocrystal nonvolatile memory devices. As for SONOS, the nitride layer is used as the charge-trapping insulator. The intrinsic distributed storage takes an advantage of the SONOS device over the FG device, its improved endurance, since a single defect will not cause the discharge of the memory.

Tiwari et al. for the first time demonstrated the Si nanocrystal floating gate memory device in the early nineties. Also, the nanocrystal memory device can maintain good retention characteristics when tunnel oxide is thinner and lower the power consumption. In this contribution, we proposed a GeO2 nano-dot memory device with 4.5nm-thick tunnel oxide and a low operating voltage of 5V. Insulating nano-dots are utilized as the storage elements rather than the semiconducting counterparts. The

concepts of SONOS and nanocrystal memories are combined and explored for the first time. A significant memory effect due to the charge trapping in the GeO2 dots is observed.

First, the 6-in Si wafer was cleaned with standard RCA recipes, followed by a thermal oxidation process to form 4.5nm-thick dry SiO2 layer as a tunnel oxide in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Right after the growth of tunnel oxide, poly-Si0.8Ge0.2 was formed on the oxide immediately by low pressure chemical vapor deposition (LPCVD). The deposition of Si0.8Ge0.2 was kept at 550℃ and the pressure was controlled to be 460 mTorr. The flow rate of the reaction gas of SiH4 and GeH4 was 60 and 8 sccm, respectively, and the Ge fraction was analyzed to be around 0.2 by Auger electron spectroscopy (AES). Subsequently, the Si0.8Ge0.2 layer was oxidized in an APCVD reactor at 950℃ and the Ge atoms would be segregated downward until they reach the tunnel oxide surface. The Ge dots grew based on the Ostwald ripening mechanism, in which the larger dots grew at the expense of the smaller dots. After the Si elements of the Si1-xGex layer are completely oxidized, the Ge nanocrystals tend to be oxidized into GeO2 nano-dots as the oxidation process is not ceased. From the analysis of transmission electron microscopy (TEM), the control oxide capped on the GeO2 nano-dots was estimated to be about 40 nm and the GeO2 nano-dots were confirmed via x-ray absorption near-edge structure (XANES). Finally, the Al electrode was patterned and sintered.

Electrical measurements were performed on the metal-insulator-semiconductor (MIS) structures with GeO2 nano-dots embedded between tunnel and control oxide.

A cross-sectional TEM micrograph of an oxide/GeO2 nano-dots/oxide stacked structure is shown in Fig. 4-5. It is clearly observed the GeO2 nano-dots are embedded between the tunnel oxide and control oxide, oxidized from the Si1-xGex layer, and are separated from each other. The insert schematically shows the gate stack arrangement

in this study. The mean size and aerial density of the dots are estimated to be about 5.5 nm and 4.3×10¹¹ cm^-2, respectively, by TEM.

To confirm the existence of the composition of the GeO2 nano-dots, x-ray absorption near-edge structure (XANES) is performed [4.15-4.17]. In XANES, a core electron is excited to higher bound or quasi-bound states, which contain information about coordination geometry and electronic aspects of the absorbing atom. Among most of the XANES studies, the standard materials with known valence is utilized as references, and compared with the unknown samples. Therefore, the measurements are frequently qualitatively-analyzed, not quantitatively. In this work, we used Ge powder, GeO2 powder, and Si0.8Ge0.2 epitaxial layer on Si as the standard materials and our investigated sample with nano-dots observed as the unknown sample. The x-ray source is extracted from the National Synchrotron Radiation Research Center.

As shown in Fig. 4-6, the shift of absorption edge (roughly the center of the intensity jump) is an index of the Ge oxidation state. The obvious edge shift from the Ge edge and the high degree of similarity between the XANES results of the sample with nano-dots and GeO2 standard reveal that Ge is oxidized. Its oxidation state is very close to GeO2.

Figure 4-7 shows the capacitance-voltage (C-V) hysteresis after the bidirectional bias sweeps between 5 V and (-5) V. It is found that a low operating voltage, 5 V, causes a significant threshold-voltage shift up to ~0.45 V, which is sufficient to be defined as “1” or “0” for the logic-circuit design. It is worth noting that the hysteresis is counterclockwise which is due to substrate injection from the electrons of the deep inversion layer and holes of the deep accumulation layer of the Si substrate.

Figure 4-8 demonstrates the band diagrams of the operation of the novel distributed charge storage with GeO2 nano-dots. The “write” and “erase” operation with different gate polarities of the memory device are exhibited. When the device is written or

programmed, the electrons directly tunnel from the Si substrate through the tunnel oxide, and are trapped in the GeO2 nano-dots. When the device is erased, the electrons may tunnel back to the deep accumulation layer of Si substrate. The control oxide is utilized to prevent the carriers of gate electrode from injecting into the GeO2

nano-dots by Fowler-Nordheim (F-N) tunneling. It is believed that during the oxidation process of the Ge nanocrystals into GeO2 nano-dots, there are defects or traps created in the interfaces between GeO2 dots and tunnel and control oxide. When the device is under programming, the injected electrons will be captured in the interfacial traps of the GeO2 dots and contribute to a threshold voltage shift (memory window). It is concerned about that if the storage of GeO2 nano-dots is as reliable as other insulating thin films. The reliability issues such as endurance and retention of the memory device should be taken into account and are currently under investigation.

In summary, we have demonstrated the novel distributed charge storage with GeO2

nano-dots. The mean size and aerial density of the dots are estimated to be about 5.5 nm and 4.3×10¹¹ cm^-2, respectively. The composition of the GeO2 dots is confirmed by the XANES measurements. In electrical analyses, a significant memory effect is observed with a threshold voltage shift of 0.45 V under 5-V operation. Also, a physical model is proposed to explain the charge storage via the interfacial traps of GeO2 nano-dots. Further works about the research on the reliability issues are currently under investigation.

(Supplement)

In addition to the fabrication method of forming Ge nanocrystals demonstrated in this chapter, a more flexible and direct approach is proposed in the supplement. Figure 4-9 illustrates the process flow of fabricating Ge nanocrystals by rapid thermal oxidation. After the p-type Si wafer was RCA cleaned, a 5nm-thick dry oxide was

thermally grown as the tunnel oxide at 925 ℃ in an atmospheric pressure chemical vapor deposition furnace. Subsequently, a 7nm-thick SiGe layer was deposited at 450

℃ by low pressure chemical vapor deposition, followed by a rapid thermal oxidation at 925 ℃. During the oxidation process, the oxidation of SiGe will be conducted faster along the grain boundary than that of the grain of the SiGe layer and the oxidation mechanism of SiGe is as described as the beginning of this chapter. After the oxidation of SiGe was performed, a 35nm-thick TEOS oxide is capped as the control oxide, followed by the process of steam densification to densify the control oxide. In this approach, the rapid oxidation of SiGe was intended to fabricate SiGe nanodots embedded in silicon dioxide after the oxidation along the grain boundary of

℃ by low pressure chemical vapor deposition, followed by a rapid thermal oxidation at 925 ℃. During the oxidation process, the oxidation of SiGe will be conducted faster along the grain boundary than that of the grain of the SiGe layer and the oxidation mechanism of SiGe is as described as the beginning of this chapter. After the oxidation of SiGe was performed, a 35nm-thick TEOS oxide is capped as the control oxide, followed by the process of steam densification to densify the control oxide. In this approach, the rapid oxidation of SiGe was intended to fabricate SiGe nanodots embedded in silicon dioxide after the oxidation along the grain boundary of