U NBALANCE B INARY S EARCH A LGORITHM

The design considerations of the lock-in controller include lock time, lock range

and area requirement. In order to balance these considerations, a binary search based lock-in controller may be the most suitable for the all-digital DLL. However, the conventional binary search based controller has narrow operating frequency. Figure 41 shows the false lock, when the operating frequency over the lock range.

Ref

256 384 448 416 432 440 444 446 447 o

22 reference cycles

Unlocked Harmonic

Figure 41 Conventional binary search based controller

Several different binary search algorithms were discussed in [5] and Section 4.2.

In order to maximize the effective sampling rate, the DLL is desired to lock the delay which is equal to one clock period. To avoid false lock (or harmonic locking [section 4.1]), the DCDL should always operate under the delay range [12], as

REF DCDL REF

0.5 T? T <1.5 T□ (4.1)

where TREF means the reference clock period, and TDCDL means the delay time of the delay line. With TINITIAL representing the initial delay time of the DLL, the relationship in equation (4.2) should be satisfied. However, the locking range of conventional binary search mechanism is restricted by equation (4.2).

DCDL_MIN INITIAL

The proposed unbalance binary search algorithm in this circuit is to choose an appropriate T_INITIAL instead of always choosing the middle point of the DCDL. Figure 42 describes the flow chart of the 3-bit unbalance binary search algorithm. In the beginning (step 0), the delay time of the delay line is adjust to the minimum and then a judge circuit exams whether the reference clock period leads twice of the minimum

delay of the delay line. If so, the next operation will go to the step1. If not, the next operation will bypass the step 1 and go to the step 2. After the step 0, no matter how the operation is, it will perform the conventional binary search until all the control bits are determined.

Figure 42 3-bit unbalance binary search algorithm.

For example, Figure 43 shows the difference between the conventional binary search (BS) algorithm and the proposed unbalance binary search (UBS) algorithm, where Ttarget means the targeted delay time and Tinitial_i means the initial delay time of the delay line. For the conventional binary search, the initial delay time is always set to the Tinitial_1 which is equal to the average of TDCDL_MIN and TDCDL_MAX. Substitute the Tinital_1 into equation (4.2), the locking range is limit to (4.3).

DCDL_MAX DCDL_MIN) Target DCDL_MAX

(T + T ) / 3< T < T

When the targeted delay time is out of the range of equation (4.3), the conventional binary search will fail without any hardware for the harmonic detection.

However, the proposed UBS algorithm has two distinct initial delay time, Tinitial_1 and Tinitial_2. When the Ttarget does not fulfill equation (4.3), it will choose the Tinitial_2 which is equal to the quarter of TDCDL_MIN and TDCDL_MAX to be the initial delay time of delay line. Therefore, the false lock problem can be avoided. In addition, to avoid false locking in the PVT variation, the limited ranges should be overlapped and equation 4.4 should be satisfied

. T_{DCDL_MIN} > (2 / 3) T□ _{INITIAL_ 2}

Figure 43 Comparison with conventional BS and UBS algorithm

Comparison with the conventional binary search, the proposed unbalance binary search algorithm has two advantages: one is avoiding the harmonic locking problem;

the other is the improvement of the divison ratio. When a wide operating range over a binary search based DLL, the minimum division ratio of two is not allowed [5].

However, it increases the locking time. On the other hand, in the proposed UBS algorithm, the division ratio could be set to two to achieve fastest lock-in time because T_DCDL is always fit in with equation (4.1). Assume the total control word of DCDL is n-bit and the division ratio is the minimum of two. The lock time for the DLL based on the UBS algorithm is given as.

{

2 (n+2) if T 2 T

lock,UBS 2 (n+2-s) if T 2 T

T = ^{斐 >} (4.5)

提 □

Where T_{DCDL_MIN} means the minimum delay time of the DCDL, and integer, S means the skip step number. The extra 2*2 cycles are the require time to evaluate the initial state. If the reference clock period is smaller than twice of minimum delay of the delay line, it can save two reference clock cycles to lock. For example, assume that the control word needs be determined with 9-bit resolution, and the maximum and minimum delay time of the delay line is 10ns and 2ns, respectively. The TINITIAL_1 is set to the middle of the provided delay range, assume 6ns in this case. The limited-range-1 can achieve 4ns to 12ns. The TINITIAL_2 is set to 3ns and limited-range-2 can achieve to 2ns to 6ns. For the TINITIAL_2, the step controller can skip two steps to achieve fast-lock. The lock time is 2× (9+2-2) =18 cycles and 2× (9+2)

=22 cycles when the reference clock period, TREF, is below and over 4 ns, respectively.

Figure 44 illustrates the simulated lock time for the counter based, SAR based, VSAR based and the UBS based schemes. The proposed UBS algorithm achieves the shortest lock cycles for the most cases.

Figure 44 Simulation lock time versus the operation range.