S IMULATION R ESULT

The proposed all-digital self-calibrated multiphase DLL is simulated in UMC 90 nm standard CMOS technology. A. The operation frequency range is 300MHz – 1.08GHz. The locking procedure takes 12 and 14 reference clock cycles for over 480MHz and below 480MHz, respectively. The proposed delay-locked loop provides 8-bit resolution, and the LSB resolution is 4ps. The total power consumption is 1.1mW at 300MHz, and 2.16mW at 1.08GHz.

The process mismatch is provided by capacitance added within delay element.

Figure 73 shows the waveform for the lock-in stage when the operating frequency is 500MHz. The signal RN and RN1 reset the system, after that the lock-in unit base on the signal LEAD that is generated from PD to change the control word, C[4:0], and traces the reference clock. The total locking cycles is 14 reference cycles and the signal LOCKED pulls up to start the calibration stage.

Figure 72 The operation of lock-in stage.

When the DLL is into the calibration stage, the calibration loops will adjust the relative phase error of output signals. The total calibration cycles is unpredictable, but in this case is 15 reference cycles. Figure 74 shows the waveform for the calibration stage.

Figure 73 The operation of calibration stage

When the DLL operates at 500MHz, a maximum 20.9ps (or 3.76^o=20.9/2000

*360) phase error is occurred in one delay stage. After rapid self-calibration algorithm is applied, the maximum phase error could be reduced to 4.5ps (or 0.81^o=4.5/2000

*360). The phase error of each delay stage is shown in Figure 75(a). A comparison with TSMC 1.2V 130nm COMS technology model is also shown in Figure 75(b). The total simulation result of chip implementation summary and a comparison result under the UMC 90nm CMOS technology are shown in Table 3.

Phase Error (ps)

Delay Cell 5 Delay Cell 5

Delay Cell 5 Delay Cell 5

Phase Error (ps)

Figure 74 The phase error of each delay stage (a) 90nm (b) 130nm

Table 3 Summary of the ADSCM-DLL

The performance comparisons among previous works and this wok are given in Table 4. Due to the finite digital quantization error, the calibrated phase error is larger than analog approach. However, this work proposed all-digital self-calibration architecture allows cost-effective integration with other circuits or portable with process.

Table 4 Comparison among previous works

CHAPTER 6 CONCLUSION AND FUTURE WORK

6.1 C

A novel 300MHz-1.08GHz all-digital self-calibrated multiphase delay-locked loop is proposed. An unbalance binary search algorithm extends the delay element operating frequency range by setting different initial delay time of delay line. Linear approximate delay element is implemented to harmonize with the modified binary search algorithm. The linear delay time increment is achieved, and solves the false lock problem. Meanwhile, the locking range is extended to entire delay line. Less than 14 reference clock cycles is needed for the locking procedure. A novel rapid self-calibration algorithm is also presented to overcome the delay element timing error caused by process variation. The calibration unit provides the maximum phase error to less than 4.5ps (0.81 degrees), which makes precise multiphase output with good PVT variation immunity possible. The proposed all-digital self-calibrated multiphase delay-locked loop is suitable for multi-core SoC applications.

6.2 F

W

In the recent year, low power is more and more important issue in circuit design, especially for the portable devices which require ultra-low power consumption.

Lowing supply voltage is a key focus in digital integrated circuit design [37].Previous research demonstrates the functionality of logic circuits at 200mV using low threshold devices [38]. Furthermore, multiple independent clocks are in great demand for power management unit the multi-core systems [39]. Hence, in our future work, we look for a low power and multiple clock outputs with dynamic frequency scaling ability DLL based clock generated. We can take advantage of the multi-Vt CMOS (MTCMOS)

technique to increase the reliability while operating at low supply voltage such as 300mV. Beside, it also obtains low leakage and high speed at the same time.

Figure 75 ADSCM-DLL based dual clock output generator

Figure 75 shows the idea of 300mV ADSCM-DLL based dual clock output generator. It includes an ADSCM-DLL, Current-Mirror-based Phase Blender (CMPB), and edge combiner (EC) [31]. The ADSCM-DLL reduces the mismatch effect and PVT variation, and then generates precise penta-phase outputs for the CMPB. It not only generates octal-phase signal from self-calibrated penta-phase signal, but also provides sufficient driving strength for EC. Each EC has independent programmability to choose desired frequency and phase by the control word Si[C:0].

As this arrangement, the power-efficient multiphase dual clock output generator is suitable for autonomous long lifetime portable devices.

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