A PPLICATION OF M ULTIPHASE DLL

In this section, we will introduce the application of multiphase DLL in detail. In these applications the multiphase DLL is used to replace the PLL. The choice of DLL rather than PLL is due to the fact that they do not exhibit the jitter accumulation characteristic and there is no need for frequency multiplication of some applications.

I. Frequency Synthesizer

Figure 23 The block diagram of conventional DLL-based frequency synthesizer.

A DLL can operate as PLL, which uses delay line to replace VCO. Fig. 23 shows the simplified block diagram of DLL-based frequency synthesizer. When the loop is locked, the output phases of every delay stage are evenly spaced one reference clock period Tref. Each phase difference of two delay stage has a delay of Tref/N and the edge combiner can generates a transition for each phase output transition, hence the output frequency is the N times the reference frequency Tref.

A multiplying DLL overcomes the drawbacks of PLL such as jitter accumulation, high sensitivity to supply, and substrate noise. For this reason, it represents a good performance for phase noise.

II. Dynamic Frequency Scaling

In recent years, the power and energy consumption has become a critical design issue in the embedded systems, especially for the mobile systems and portable systems. Dynamic Voltage Frequency Scaling (DVFS) has been more important for saving energy on mobile embedded systems. Figure 24 illustrates the diagram of the voltage/frequency transition that proposed in [36]. The voltage changes from high to low and goes back to high in this example. In the conventional frequency scaling, the clock must be stopped during voltage transition. Therefore, performance overhead occurs by the frequency scaling. For the proposed frequency scaling, the voltage/frequency selectors are introduced to achieve no performance overhead as indicated in the third line of the figure.

Figure 24 The operation of DVFS scheme

Notice, there are two issues need to be consideration for changing the frequency without stopping the running programs. First, the data transfer from modules operating in different frequency must be handled by the main bus. Second, the transition in supply voltage skews the clock tree.

A DVFS scheme is also proposed in [35]. A frequency adjuster circuit unit calculates the optimum clock frequency based on the activity value derived from the activity monitor to reserve the required number of inactive margin cycles within the monitoring period and indicates the next clock frequency to the clock generator. The dynamic frequency is selected by the clock thinning circuit which collects several different frequency input. Therefore, it can operate continuously without PLL relock or system.

In order not to make performance overhead, the relock time is an important issue for the DFS. All the previous mentioned DVFS schemes utilize multiple existing frequencies to generate the desired frequency. However, it increases the consumption for the useless frequency. A multiphase DLL based clock generator for dynamic frequency scaling was proposed in [31]. With plain digital logic for frequency adjustment, the multiplication factor can be changed with fast lock time. For the specific case, it only takes one-cycle to lock during frequency scaling.

III. Transmitter [48]

In the digital communication application, the multiphase DLL can apply to a data cannel compression transceiver. The architecture of the transceiver is shown in Figure 25. The transmitter’s output, TX_DATA and TX_CLK, are sent to the receiver’s inputs, RX_DATA and RX_CLK, respectively. In the transmitter, the generated seven-phase clock signals are used to transfer 7-bits data (DATA [6:0]) into one data channel (TX_DATA), and the TX_CLK is also sent to the receiver. The receiver shown in Figure 25(b) recovers the received data stream (RX_DATA) back to original 7-bits data (DATA_OUT [6:0]). The two-phase ADMCG shown in Figure 25(b) is used to estimate the accurate delay of TREF/14. It aligns two adjacent phases of the seven-phase DLL outputs (i.e., P6 and P0) to measure the delay, and the received data stream will first be delayed by and then sampled by the seven-phase multiphase clock signals. Thus, those multiphase clock signals can sample the received data stream in the center of the bit symbol boundary, and this maximizes the timing margin of the receiver circuit

Figure 25 7:1 Data channel compression transceiver. (a) Transmitter circuit. (b) Receiver circuit.

IV. DDR SDRAM controller application [10]

In [10], the calculations for timing budget show that the optimal value for tSD is approximately 20 percent of an input clock period as shown in Figure 26. Since the input clock frequency range from 100MHz to 200MHz (DDR-200/266/333/400), the tSD value varies from 2ns (=10nsX0.2) to 1ns (=5nsX0.2). Therefore, a five-phase all-digital DLL was proposed in [10] to generate the desired tSD delay for DQS signal.

Figure 26 Read operation timing budget

The block diagram of the five-phase all-digital DLL for DDR SDRAM controller application is shown in Figure 27. Like most of DLL-based multi-phase clock generators, the DLL has a multi-stage delay line with the same control word to

generate equally spaced multi-phase clock output. It uses the time-to-digital (TDC) scheme to lock whole loop. Hence, a design consideration should be noticed is that sometimes it is difficult to meet the minimum delay constraint when using standard cell to build up a high resolution delay cell. Therefore, the DLL in this design is lock to two periods of the reference clock period by using TDC scheme. After DLL is locked, the phase spacing of each delay stage should be 2*T_FREF/5, where T_FREF means the clock period of the reference clock. Hence the minimum delay constraint for each delay stage is extended twice as original. The total delay from DQS to DQSD becomes 1.2xT_FREF, which means the phase shift between DQS and DQSD is still 0.2xT_FREF. As a result, the desired tSD delay can be generated by the multiphase DLL

Figure 27 The block diagram of multiphase DLL for DDR SDRAM application