OBJECTIVES

Consider the components of a typical media processing system, shown in Fig. 1-1.

Here, an input source presents a data stream to a processor’s input interface, where it is manipulated appropriately and sent to a memory subsystem. The processor core(s) then interact with the memory subsystem in order to process the data, generating intermediate data buffers in the process. Ultimately, the final data buffer is sent to its destination via an output subsystem.

Input Subsystem

Core Processing

Output Subsystem

Memory Subsystem

Input Source Destination

Fig. 1-1. Components of a typical media processing system.

Multimedia processing is that the actual work done by the media processor core. The input data varies widely in its bandwidth requirements. Raw audio might be measured in tens of kilobits/second (kb/s), and raw video could entail tens of megabytes per second (Mbytes/s).

Then, it is clear that the media processor needs to handle different input formats in different ways

The computational requirements of multimedia processing are dominated in the first place by the signal processing tasks, requiring complex operations to be performed on large data volumes at high sample rates. Typically, real-time constraints arise from the need to satisfy human sound perception demands. Having to deal with multiple streams of different data types further complicates the processing task. State-of-the-art multimedia architectures employ a number of architectural measures in order to exploit the computational characteristics of speech and audio processing algorithms in particular. So far, the design focus has been on efficient implementation of the computation-intensive low-level parts of the algorithms-as dominating in frame-based schemes. Depending on the targeted application field, dedicated and programmable approaches can be distinguished.

The design of dedicated VLSI implementations for selected multimedia processing schemes is driven by the need for inexpensive, highly integrated systems targeting the consumer market. This goal is achieved by deep adaptation of modules to special

algorithms and algorithm classes. Programmable architectures, on the other hand, provide a more general platform, offering the flexibility to allow various algorithms being executed on the same hardware by only software modifications.

To achieve computing performance, the application-driven necessity to provide processors with both microprocessor and DSP functionality enforces new architectures and approaches. Simply using two cores—a microprocessor and a DSP core—is multitasking-effective as resources are often doubled. The 24-bit architecture presented here provides general purpose micro-processing as well as DSP functionality through a single-core and a unified architecture, respectively. The optimal solution is an application-oriented processor core [69], [70], having a lower cost than a general-purpose DSP. The parallel architecture of DSP can efficiently execute vector and matrix operations without extra overhead. In order to implement an application-driven DSP, we use a methodology for hardware/software (HW/SW) co-verification [71] and optimize the processor architecture and instruction sets. High flexibility in use, small area on silicon, high data throughput, and fast portability to a wide range of technologies are our main targets in the core development.

The modern embedded system has moved toward the target of system integration and implementation. Reuse [50] is done at the chip level called intellectual property (IP) core which represents the functions of specification domains like multimedia applications.

These modules are integrated into System-on-Chip (SoC) [72] which is a typical architecture. We investigate architectural techniques to facilitate analysis and integration for heterogeneous and general/complex SoC applications in this thesis. We use a microcontroller and digital signal processor application to validate the embedded platform prototype. The concept of platform refers to a family of architectures satisfying ARM defined constraints [54], and allowing customizations and substantial re-use of hardware

and software modules. We developed a base architecture with customization or parameterization options to speed-up derivative implementations while reducing the HW/SW overhead. The definition of the SoC platform IP is the result of a trade-off process involving reusability, overall SoC integration effort [67], performance [68] and power optimizations [77]. Our focus is on efficiency of the hardware and software resources in the context of a self-adapting architecture with autonomic features. The motivation for developing such IP is to facilitate integration of SoCs. Because the platform is meant to be easily customized, it is essential to meet stated resource-efficiency goals.

The SoC integrated platform provides multi-function system backbone for various multimedia applications. The new proposed SoC integrated platform which combines microprocessor, digital signal processor (DSP), memory, and other functional modules such as GPIO (General-Purpose Input/Output), I²S (Inter-IC Sound), and communication (UART) into a single IC is popular recently. To verify these functions of the proposed platform for audio and speech processing, the FPGA (Field Programmable Gate Array) rapid prototype approach will be used. FPGA were primarily used for prototyping and lower volume applications in years and custom ASICs were used for high volume, cost-sensitive designs. In the thesis, we will describe the proposed platform, IP reuse design experiment based on a methodology in [66].

The contribution of this thesis is to propose a multimedia SoC platform, which can integrate 3C consumer products, for sound processing. The platform can solve low-cost consideration and construct quickly the components of multimedia signal processing in the standard bus. The platform using two cores, a microprocessor and a DSP core, can promote computational performance. Especially DSP, it is designed as the sound signal processor for the consideration of architecture and instruction set, and has low-power characteristics with gated-clock technology [37]. Due to their high capacitive load which makes them a

major contributing factor to the overall power consumption of the SoC device, we take advantage of instruction or control types to decide which component needs to be disabled.

In addition, bus encoding techniques [77] can reduce the power consumption on a bus by mapping the information conveyed on the bus to a form which has less transition activity than the original. This is to reduce the consumption of the electric current. Due to cross-platform design which is not limited by any synthesis tool or FPGA, this method can be easily verified and fabricated as ASIC.