CHAPTER 5 THE INTEGRATED PLATFORM FOR MULTIMEDIA PROCESSING
5.4 SYSTEM PROTOTYPE
The proposed SoC platform design for audio applications has been synthesized on the Altera FPGA. In particular, the EP1C20F400 Cyclone FPGA has been employed to carry out all the synthesis and place-and-route processes. The synthesis results are shown in Table 5-3. By using Altera QuartusII, it is mapped, placed, and routed in less than a minute.
The basic system occupies 1 block RAM about 65536 bits, 837 logic cells, 470 registers, 452 LUTs (look-up table), and 100 available pins. The SoC platform consumes just 5% of the logic resources, one of the smallest devices in that product family. LASP24 and reverberator consume618 registers and 3,796 LEs. These two IPs can be performed on 100MHz frequency.
Table 5-3. The FPGA synthesis results of audio SoC design.
Results Components
FSM (states)
Registers Sizes (LEs)
Operating frequency 8051 wrapper (AHB) 40 125 322 40 MHz above
I2S (APB) ×3 - 231 264 3.072 MHz
GPIO (APB) 3 29 97 20 MHz
UART (APB) 10 53 92 Fixed baud rate: 9.6k bps
SSRAM controller (AHB)
4 15 29 40MHz for read and write operations
Interrupt controller (APB)
- 8 17 20MHz
Clock generator for I2S design
(Independent module)
- 9 16 Input clock: 18.432 MHz Bit clock: 3.072 MHz Sampling rate: 48 KHz
LASP24 17 1,835 22,747 Up to 100MHz
Reverberator (APB) 25 287 7,049 Up to 100MHz
The operating frequency of the AMBA system and 8051 is at 40 MHz and 12 MHz, respectively. The 8051 transducer (1251 cycles) allows fetching the wrapper data and providing these data to each component in AMBA. In other words, it executes the 8051
simple handshake enable. The dual-port memory contains 4096 with 16-bit width 6-channel audio streaming data, and the data format is shown in Fig. 5-10(a). The sync signal is used as an interrupt to trigger DSP. It is important for the synchronous problem of audio data. When the microprocessor receives audio data via an interrupt, data is then written into the dual-port SRAM shown in Fig. 5-10(b) by using Fig. 5-10(a) format.
(a)
(b)
Fig. 5-10. Share memory: (a) The data format and control of audio streaming and (b) simulation results of processing three-channel data in the dual-port SRAM.
As a result, we can be able to test quickly the prototyping system (Fig. 5-1) in the development kit environment. The SoC system can perform with accuracy and control DSP operations of optimized audio algorithms as well as high-quality sound in real-time.
The development environment and the final demo board for audio processing are shown in Fig. 5-11.
FPGA Test PinsFPGA Test Pins
I Dual-Dual-port SSRAMport SSRAM Cyclone FPGA Dual-Dual-port SSRAMport SSRAM Cyclone FPGA
Fig. 5-11. (a) The final Demo board and (b) the initial development environment.
CHAPTER 6
CONCLUSIONS AND FUTURE WORKS
This thesis has proposed a new low-cost application-specific processor (LASP24) for sound processing in multimedia. High performance is achieved by vector and matrix operations that are not usually supported by general-purpose DSPs. The LASP24 has precise 24-bit floating-point arithmetic units. This processor makes the speech coding algorithms ready to run in real-time operations. In addition to the LPC calculation and pitch estimation built-in to the LASP24 core, the other algorithms such as a codebook search can also be implemented in the designed processor. Furthermore, a technique of gated clocks on power optimization of sequential circuits was involved in this design to reduce power dissipation. Based on these features, LASP24 can share huge calculations in real-time speech coding. It can also reduce power consumption: 25.75% at 100MHz, 12.75 at 80MHz, 31.1% at 40 MHz, 27.6% at 33 MHz, and 62.75% at 25 MHz. The performance of LASP24 was about 4.75 times higher than TMS320C30 and about 3.2 times higher than TMS320C31. Several experimental tests have been done, and the performance comparisons to a series of TMS320C3x processors are also presented in the thesis. As these testing results, we can find that LASP24 for sound processing has a very satisfactory performance, and it has also verified all the designed functions.
Finally, a SoC platform design for digital sound processing by using FPGA development environment is presented. Through the 8051 embedded microcontroller, we can easily program two audio processing and completely control all actions of the audio system. The platform has been verified and performed in the Altera Cyclone FPGA, and it can control the DSP processor to execute speech coding such as MELP and audio
enhancement such as Reverberation as well. The proposed SoC integration platform offers outstanding performance and flexibility at very low cost for a wide range of multi-channel audio applications. In the future, the DSP processor for audio processing will be developed such that it can be integrated into the proposed SoC platform design to perform a complete audio SoC system. Under FPGA verification and testing, on average the whole performance obtains 80MIPS and 90mW power consumption. Due to a cross-platform implemented method, it can be applies into an embedded and portable multimedia system and can also be integrated to a single silicon chip.
The modern day computing technology ought to be one supporting interactive and intelligent processing [74] that transforms and transfers information ubiquitously and in real-time speed. The future computing must provide both economic bandwidth utilization and efficient information extraction. More importantly, the industry must be prepared for the inevitable trend that (1) computing (2) control and (3) users will be separated by long distances. As a result, the users can anticipate the near-future convergence of computing and communication. A truly integrated media system must connect with individual users and content addressable multimedia databases. This new trend bring about a great technological challenge as
● Future multimedia technologies will need to handle information with an increasing level of intelligence, i.e., automatic extraction, recognition, interpretation, and interactions of multimodal signals, and the ability to seamlessly handle different representations. This will lead to what can be called intelligence multimedia processing technology, and integrated into the SoC platform.
● We envision a major impact by integrating adaptive neural processing into the state-of-the-arts multimedia technologies. The main power of neural networks
taught to interpret possible variations of the same object or pattern, e.g., scale, orientation, and perspective.
● The system integration will also be a challenging task as it involves complex tradeoff in integrating subsystems into a functional SoC system. For example, we need to estimate the necessary storage space for application codes (such as adaptive on-the-fly incremental training). The objective is to have the total system implemented under the specified power, size, weight, and cost constraints.
In the future, General-purpose workstations and PCs are already equipped with powerful programmable microprocessors; these processors, however, have not been able to perform image and video processing tasks efficiently as the special algorithm characteristics are not exploited. Therefore, a special class of programmable multimedia processors [64] has evolved that incorporate architectural enhancements to increase their multimedia processing capabilities. These enhancements include as follows.
● Subword parallelism: A number of lower-precision data items are processed in parallel on the same ALU (split-ALU). This enables to exploit data parallelism in highly regular low-level algorithms involving identical operations executed on large data volumes.
● Very long instruction word (VLIW) [82]: Several operations are specified within a single instruction word for concurrent execution on multiple function units.
Instruction level parallelism available in image and video algorithms can thus be exploited. Code scheduling has to be performed statically by the compiler.
● Coprocessor architecture: By incorporating one or more separate modules adapted to specific tasks, highly regular program parts with high processing requirements can be executed on dedicated hardware, while more irregular but less
computationally intensive control tasks can be performed on a programmable processor core.
● Memory system design: Due to the high data volumes encountered particularly in video processing, the memory system has a significant impact on overall performance. Stream caches have been proposed that employ prefetching techniques to access shortly needed data in advance. Data structures of static nature, such as filter coefficients or look-up tables, can be placed into on-chip SRAMs where they are always accessible within shortest times. For instruction memory design, conventional cache strategies may prove useful for speeding up instruction access, provided the cache is large enough and mutual code replacement can effectively be prevented.
The architectural enhancements of current multimedia processors alone, targeting almost exclusively audio enhanced algorithms, will not be sufficient for the emerging multimedia applications. With increasing sophistication of multimedia algorithms and less predictable program flow, new concepts are required.
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APPENDIX A
LASP24 Instruction Set and Examples
Notice that the symbol { } represents an optional set. In the set, only choose a term as operand.
Operand：
z R{0..7}, R{0..7}
z R{0..7}, RAM{0, 1}[#direct]
z RAM{0, 1}[#direct], R{0..7}
z R{0..7}, {EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}], RAM{0, 1}[{R, J, R+J, J-R}]}
z {FIL[{R_FIL ， R_FIL+R, R_FIL+J, R_FIL-R}], EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}], RAM{0, 1}[{R, J, R+J, J-R}]}, R{0..7}
z RAM{0, 1}[{R, J, R+J, J-R}], EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}]
z EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}], RAM{0, 1}[{R, J, R+J, J-R}]
z WIN[R], RAM{0, 1}[{R, J, R+J, J-R}]
z WIN[R], EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}]
z FIL[{R_FIL, R_FIL+R, R_FIL+J, R_FIL-R}], RAM{0, 1}[{R, J, R+J, J-R}]
z FIL[{R_FIL, R_FIL+R, R_FIL+J, R_FIL-R}], EXT[{R_EXT, R_EXT+R, R_EXT+J, R_EXT-R}]
MOV
Description:
z The operation “MOV R1, R3” is to copy data from R1 to R3.
z The operation “MOV RAM0[10], R4” shows that data of RAM bank 0 with the address 10 is copied to R4.
z The operation “MOV FIL[R_FIL], RAM0[R]” is to copy data from Filter ROM with the address R_FIL to RAM0 with the address R.
z R, J, R_EXT, and R_FIL are all auxiliary registers. It is used as the address index.
z R, J, R_EXT, and R_FIL are all auxiliary registers. It is used as the address index.