3.3 P ERFORMANCE A NALYSIS
3.3.4 Overall System Performance
In this section, we will show the performance of the overall system. The quasi-error free condition which corresponds to 2x10-4 BER after Viterbi decoder will be the performance target of this section. In order to evaluate the influence of the proposed CFO synchronization scheme to the overall scheme, the most critical operation mode which includes 2k mode and GI=1/32 is considered in the following simulation results. Besides, in the integral CFO
acquisition stage, we exploit the proposed guard band based approach to verify if its performance is acceptable for all kinds of conditions. For separating fixed reception from portable reception, we divide the overall system performance into two parts: static channel and mobile channel.
The overall system performance in three types of static channel model is shown as from Fig. 3.22 to Fig. 3.24. The simulation environment is 2k mode, GI=1/32, code rate=2/3, SCO=20ppm, and CFO=10.33 (92.14ppm), respectively. The solid line means the synchronization of CFO is perfect, and the dashed line means the result that utilizes the proposed CFO synchronization scheme. As we can see the frequency selective fading of multipath channel brings unavoidable performance degradation compared with the AWGN condition. Compared with the AWGN channel, the SNR loss of ideal case is about 2dB in Ricean channel and 8dB in Rayleigh channel.
4 6 8 10 12 14 16 18 20 10-6
10-5 10-4 10-3 10-2 10-1
SNR (dB)
BER
QPSK,ideal QPSK 16-QAM,ideal 16-QAM 64-QAM,ideal 64-QAM
Fig. 3.22 Overall system performance in Gaussian channel
5 10 15 20 10-6
10-5 10-4 10-3 10-2 10-1
SNR (dB)
BER
QPSK, ideal QPSK 16-QAM, ideal 16-QAM 64-QAM, ideal 64-QAM
Fig. 3.23 Overall system performance in Ricean channel
12 14 16 18 20 22 24 26 28 10-5
10-4 10-3 10-2
SNR (dB)
BER
QPSK, ideal QPSK 16-QAM, ideal 16-QAM 64-QAM, ideal 64-QAM
The overall system performance in mobile channel is evaluated and simulated as shown in Fig. 3.25. The simulation environment is 2k mode, GI=1/32, code rate=2/3, SCO=20ppm, CFO=10.33, and Rayleigh channel with Doppler spread 70Hz, respectively. We can see that the performance degradation of the time-varying channel is more serious than the static condition. Compared with the AWGN channel, the SNR loss of ideal case is about 10dB in mobile Rayleigh channel. The SNR loss due to the proposed CFO synchronization scheme is as shown in Table 3-4.
Table 3-4 SNR loss due to synchronization in different channel models
Gaussian Ricean Rayleigh Rayleigh+fd=70Hz
QPSK 0.17 0.12 0.07 0.20
16-QAM 0.08 0.15 0.18 0.08
64-QAM 0.03 0.08 0.10 0.10
12 14 16 18 20 22 24 26 28
10-5 10-4 10-3 10-2
SNR (dB)
BER
QPSK, ideal QPSK 16-QAM, ideal 16-QAM 64-QAM, ideal 64-QAM
Fig. 3.25 Overall system performance in mobile Rayleigh channel
Chapter 4 .
Architecture and Implementation
In this chapter, the platform based design methodology will be introduced first. Then the architecture of the implemented DVB-T/H receiver will be illustrated. The architecture of the proposed CFO synchronization design, hardware synthesis information and chip summary will be shown in the following sections.
4.1 Design Methodology
The trend of IC technology is towards to System-on-Chip (SoC). System-level simulation becomes very important in today’s design flow. Our design methodology from system simulation to hardware implementation can be shown in Fig. 4.1. First, the system platform and channel modals should be established according to the system specification with MATLAB language, which ensures the design in the practical condition. Algorithm research and architecture development of each function block should be verified in the system platform to ensure the whole system performance. Fixed-point simulation is applied before hardware implementation to make the trade-off between system performance and hardware cost. In hardware implementation, the Verilog HDL modules are verified with the test benches dumped from the equivalent Matlab blocks to ensure the correctness. Finally, once the verification between HDL modules and fixed-point MATLAB platform is finished, the HDL based platform will be synthesized and translated to circuit level by place and route (P&R) tools.
System platform built-up Channel model
Algorithm developement
Fixed-point simulation Wordlength analysis
Verilog HDL coding
Gate level synthesis
Circuit level implementation
Verilog test pattern
Circuit level test pattern MATLAB Platform
Fig. 4.1 Platform-based design methodology
4.2 Architecture of the DVB-T/H Baseband Receiver
Based on the proposed low complexity CFO synchronization scheme and other low power designs such as high speed FEC decoder and dynamic scheduling FFT processor [24], a DVB-T/H baseband receiver is implemented and tapped out in Jun. 2005. The architecture and corresponding clock rate of the DVB-T/H baseband receiver is shown in Fig. 4.2. As we can see the received data is oversampled at 2 times of the original sampling rate and then interpolated by resampler to recovery sampling clock drift. The clock rate of the main datapath within inner receiver is raised up to four times of the original data rate to meet continuous symbol reception because the required operation time of the FFT processor is about four times of the symbol duration. After the de-QAM constellation, the clock rate is
raised up to six times of the original data rate to satisfy the bit-level calculation. In DVB-T/H system, different channel bandwidths will correspond to different clock rates. The highest clock rate of the received data is about 9MHz when the 8MHz channel bandwidth is utilized.
In order to assure that the implemented chip can work in such condition properly, the basic clock rate of the synthesis result is set at 11MHz. The detailed architecture of the proposed CFO synchronization scheme and the chip summary will be illustrated in later sections.
Resampler/ interpolator Channel estimator Channel equalizer
Zero Padding remove Symbol deinterleaver Soft DeQAM memory size:126 P/S 4xÆ6x
s1
i1 i2 i3 i4 i5 i6 4x clock region
s2 f1 f2 f3
memory size: K/2memory size: K/2 memory size: K/2memory size: K/2 memory size: K/2memory size: K/2
CFO Compensation Time Sync
Pre-FFT CFO estimation t1memory size: N
FFT Core t2memory size: Nmemory size: Cmemory size: C
memory size:126 memory size:126 memory size:126 memory size:126 memory size:126
Post-FFT CFO estimation
CFO Tracking Viterbi DecoderOuter DeInterleaverRS decoder
ADC 6x clock region
2x clock region
Fig. 4.2 Architecture of the DVB-T/H baseband receiver
4.3 Architecture of Carrier Frequency Offset Synchronization
In this section, the detailed architecture of each functional block of the CFO synchronization scheme will be illustrated. The synthesis result will also be listed based on the implemented DVB-T/H receiver chip which is tapped out in Jun. 2005.
4.3.1 Fractional Carrier Frequency Offset Synchronization
The hardware architecture of the proposed fractional CFO estimator is shown in Fig. 4.3.
The correlation between R and l n, Rl n N, − is calculated by a complex multiplier and a size N memory. The accumulation length is controlled by the controller based on the number of discarded samples y and the actual length of the guard interval that detected by the mode/GI detector. In our inner receiver design, the coarse symbol synchronization is accomplished by the normalized maximum correlation (NMC) algorithm and exploits the correlation between
,
R and l n , too [21]. The operations would not overlap because the synchronization of symbol bound and fractional CFO are both in acquisition stage. Hence the complex multiplier and size N memory can be combined with the coarse symbol synchronizer together.
,
Combine with coarse symbol sync.
^
ε
FFig. 4.3 Architecture of fractional CFO estimator
The objective of the arc-tangent component is to calculate the phase of the complex correlation result. In our proposed fine CFO estimator, the arc-tangent component is combined with the constant multiplier that multiplies the calculated phase value by 1/ 2π to
save the additional hardware resource for the constant multiplication. The architecture of the conventional arc-tangent approaches can be divided into a direct-TLU method and a division-based TLU method [25]. The former requires a large look-up table when the input wordlength is longer, and the later consumes a divider that costs large hardware area and long latency, respectively. Hence in our proposed fractional CFO estimator, a logarithm-based TLU arc-tangent method is utilized for the phase calculation to achieve low power and high speed consideration [26]. By adopting this technique, the size of look-up table can be reduced effectively and a division free architecture can be obtained by using only combinational addition and subtraction. The synthesis result of the proposed fine CFO estimator in a 0.18µm cell library with clock rate equals to 11MHz is shown in Table 4-1.
Table 4-1 Synthesis result of the fractional CFO estimator
Gate Count
Combinational 11260 Non-Combinational 692
Total 11952
4.3.2 Integral Carrier Frequency Offset Synchronization
In order to achieve low power consideration, the proposed 2-stage guard band based algorithm is utilized in our DVB-T/H receiver system design. The hardware architecture of the first stage of the proposed integral CFO estimator is shown in Fig. 4.4. As we can see the signal power of the receiving data is calculated by two integral squarers instead of real multipliers to save the hardware implementation cost. The memory element is used to store the signal power of the l-th symbol and can be shared with the deinterleaver. Once the summation of the signal power within the left and right window is calculated, the comparator result can determine the shifted direction caused by integral CFO is positive or negative.
2
Fig. 4.4 Architecture of the first stage of the proposed integral CFO estimator
The hardware architecture of the second stage of the proposed integral CFO estimator is as shown in Fig. 4.5. As previous mentioned, two squarers are also exploited to calculate the signal power and can be shared with the first stage to save implementation cost. The signal power within search range of the l-1-th and the l-2-th symbol is stored in two memory elements that are shared with the deinterleaver. By the aid of a FIFO whose length is equal to the width of the moving window, the summation of signal power of the moving window can be obtained. An additional memory element is utilized for storing the summation of the signal power within the moving window in left-hand side of the guard band, and is also shared with the deinterleaver. Once the comparator detects the smallest summation value of signal power among the search range that is detected by the first stage, the corresponding index will be the estimated integral CFO value. The synthesis result of the proposed integral CFO estimator in a 0.18µm cell library with clock rate equals to 44MHz is shown in Table 4-2.
2
mux reg comparator smaller index transform
^
ε
I
-Fig. 4.5 Architecture of the second stage of the proposed integral CFO estimator
Table 4-2 Synthesis result of the integral CFO estimator
Gate Count
Combinational 8955 Non-Combinational 2208
Total 11163
4.3.3 Residual Carrier Frequency Offset Tracking
The tracking stage of the proposed CFO synchronization scheme can be divided into two main blocks, the joint residual CFO/SCO estimator and the PI loop filter. The hardware architecture of the joint residual CFO/SCO estimator is shown in Fig. 4.6. As we can see the continual pilots of the previous symbol is stored in a memory element which is shared with the channel estimator. For the phase calculation, the joint CFO/SCO estimator also exploits the logarithm-based TLU arc-tangent method to achieve low power and high speed consideration. The architecture of the PI loop filter is already discussed in chapter 2 and as shown in Fig. 2.13. The synthesis result of the overall residual CFO tracking scheme in a 0.18µm cell library with clock rate equals to 44MHz is shown in Table 4-3.
ram
-Fig. 4.6 Architecture of the joint residual CFO/SCO estimator
Table 4-3 Synthesis result of the residual CFO tracking scheme
Gate Count
Combinational 11067 Non-Combinational 1269
Total 12336
4.4 DVB-T/H Baseband Receiver Chip Summary
Based on the proposed low complexity CFO synchronization scheme and other low power designs such as high speed FEC decoder and dynamic scheduling FFT processor [24], a DVB-T/H baseband receiver is implemented and tapped out using 0.18um standard CMOS process in Jun. 2005. The layout view is shown in Fig. 4.7 with features listed in Table 4-4.
The proposed baseband receiver contains 371.4K logic gates and 154.2Kbytes memory.
Table 4-4 Chip Feature
Technique 0.18um CMOS, 1P6M
Gate Count (Excluding SRAM) 371,353 Embedded Memory Size 154.2Kbytes
Package 208-pin CQFP
Core Size 6.9 X 5.8 mm2
Clock Speed 109.7 MHz
Supply Voltage 1.8V Core, 3.3V I/O
Core Utilization 59.33%
Power Consumption at 31.67 Mbps 250 mW
FFT RAM
FFT
CE RAM
Viterbi Decoder
RS Decoder
Viterbi RAM
CE EQ (I)
Inner Deinterleaver
EQ (II) DeQAM CFO
(I)
CFO (II)
CFO (III) Time (I) Time
(II)
Ot h ers
Fig. 4.7 Layout view of the DVB-T/H baseband receiver
Chapter 5 .
Conclusion and Future Work
After the algorithm illustration and performance analysis, the proposed low complexity CFO synchronization scheme is robust to solve CFO even in critical channel environment. In the proposed fractional CFO acquisition, the proposed algorithm can overcome the distortion within guard interval caused by multipath delay spread and achieves 0.25~7.8dB gain in RMSE compared with the conventional approach. In the proposed integral CFO acquisition, a 2-stage scheme is proposed to reduce the search range to about half of the conventional one.
Besides, two low complexity algorithms are also proposed to detect the accurate integral CFO value and save more than 80% of number of multiplication without any performance loss to the overall system compared with the conventional approach. In the residual CFO tracking stage, the proposed three stage tracking loop can reduce the residual CFO error effectively.
Applying the proposed CFO synchronization scheme, the synchronization loss to the overall DVB-T/H baseband receiver system is less than 0.2dB even in severe channel distortion including Rayleigh channel, Doppler spread 70Hz, CFO 92.14ppm (10.33 subcarrier spacing) and SCO 20ppm.
In this thesis, we focus on the synchronization with fixed CFO value in time-varying channel. For the future application with handheld terminals, the reception ability in mobile environment and limited operation power consumption will be the most important tasks.
Therefore, a more robust synchronization scheme to time-varying CFO in severe mobile environment should be constructed. Furthermore, a fast and efficient CFO resynchronization scheme should be built to satisfy the low power issue in the future application.
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