In this section, the detailed architecture of each functional block of the CFO synchronization scheme will be illustrated. The synthesis result will also be listed based on the implemented DVB-T/H receiver chip which is tapped out in Jun. 2005.
4.3.1 Fractional Carrier Frequency Offset Synchronization
The hardware architecture of the proposed fractional CFO estimator is shown in Fig. 4.3.
The correlation between R and l n, Rl n N, − is calculated by a complex multiplier and a size N memory. The accumulation length is controlled by the controller based on the number of discarded samples y and the actual length of the guard interval that detected by the mode/GI detector. In our inner receiver design, the coarse symbol synchronization is accomplished by the normalized maximum correlation (NMC) algorithm and exploits the correlation between
,
R and l n , too [21]. The operations would not overlap because the synchronization of symbol bound and fractional CFO are both in acquisition stage. Hence the complex multiplier and size N memory can be combined with the coarse symbol synchronizer together.
,
Combine with coarse symbol sync.
^
ε
FFig. 4.3 Architecture of fractional CFO estimator
The objective of the arc-tangent component is to calculate the phase of the complex correlation result. In our proposed fine CFO estimator, the arc-tangent component is combined with the constant multiplier that multiplies the calculated phase value by 1/ 2π to
save the additional hardware resource for the constant multiplication. The architecture of the conventional arc-tangent approaches can be divided into a direct-TLU method and a division-based TLU method [25]. The former requires a large look-up table when the input wordlength is longer, and the later consumes a divider that costs large hardware area and long latency, respectively. Hence in our proposed fractional CFO estimator, a logarithm-based TLU arc-tangent method is utilized for the phase calculation to achieve low power and high speed consideration [26]. By adopting this technique, the size of look-up table can be reduced effectively and a division free architecture can be obtained by using only combinational addition and subtraction. The synthesis result of the proposed fine CFO estimator in a 0.18µm cell library with clock rate equals to 11MHz is shown in Table 4-1.
Table 4-1 Synthesis result of the fractional CFO estimator
Gate Count
Combinational 11260 Non-Combinational 692
Total 11952
4.3.2 Integral Carrier Frequency Offset Synchronization
In order to achieve low power consideration, the proposed 2-stage guard band based algorithm is utilized in our DVB-T/H receiver system design. The hardware architecture of the first stage of the proposed integral CFO estimator is shown in Fig. 4.4. As we can see the signal power of the receiving data is calculated by two integral squarers instead of real multipliers to save the hardware implementation cost. The memory element is used to store the signal power of the l-th symbol and can be shared with the deinterleaver. Once the summation of the signal power within the left and right window is calculated, the comparator result can determine the shifted direction caused by integral CFO is positive or negative.
2
Fig. 4.4 Architecture of the first stage of the proposed integral CFO estimator
The hardware architecture of the second stage of the proposed integral CFO estimator is as shown in Fig. 4.5. As previous mentioned, two squarers are also exploited to calculate the signal power and can be shared with the first stage to save implementation cost. The signal power within search range of the l-1-th and the l-2-th symbol is stored in two memory elements that are shared with the deinterleaver. By the aid of a FIFO whose length is equal to the width of the moving window, the summation of signal power of the moving window can be obtained. An additional memory element is utilized for storing the summation of the signal power within the moving window in left-hand side of the guard band, and is also shared with the deinterleaver. Once the comparator detects the smallest summation value of signal power among the search range that is detected by the first stage, the corresponding index will be the estimated integral CFO value. The synthesis result of the proposed integral CFO estimator in a 0.18µm cell library with clock rate equals to 44MHz is shown in Table 4-2.
2
mux reg comparator smaller index transform
^
ε
I
-Fig. 4.5 Architecture of the second stage of the proposed integral CFO estimator
Table 4-2 Synthesis result of the integral CFO estimator
Gate Count
Combinational 8955 Non-Combinational 2208
Total 11163
4.3.3 Residual Carrier Frequency Offset Tracking
The tracking stage of the proposed CFO synchronization scheme can be divided into two main blocks, the joint residual CFO/SCO estimator and the PI loop filter. The hardware architecture of the joint residual CFO/SCO estimator is shown in Fig. 4.6. As we can see the continual pilots of the previous symbol is stored in a memory element which is shared with the channel estimator. For the phase calculation, the joint CFO/SCO estimator also exploits the logarithm-based TLU arc-tangent method to achieve low power and high speed consideration. The architecture of the PI loop filter is already discussed in chapter 2 and as shown in Fig. 2.13. The synthesis result of the overall residual CFO tracking scheme in a 0.18µm cell library with clock rate equals to 44MHz is shown in Table 4-3.
ram
-Fig. 4.6 Architecture of the joint residual CFO/SCO estimator
Table 4-3 Synthesis result of the residual CFO tracking scheme
Gate Count
Combinational 11067 Non-Combinational 1269
Total 12336