CHAPTER 5 Simulation Result and Performance Analysis

5.3 S IMULATION R ESULT OF MB-OFDM S YSTEM

5.3.2 System Performance

In this section, performance of our MB-OFDM system is shown by PER simulation, and performance degradation between perfect synchronization and proposed frame synchronizer will be discussed also. In wireless communication, frame synchronizer usually dominates system performance at low SNR condition when system operates at low data rates. Thus we simulate PER at data rate=110Mb/s for the specified 802.15.3a channel models by using perfect frame synchronizer, conventional 128-tap matched-filter, and proposed 32-tap matched-filter for CM1 to CM4 environments. Finally, the performance of proposed design will be shown for 110Mb/s~480Mb/s data rates with the worst required CM channel environment.

FIG 5.38~5.41 are PER simulation at 110Mb/s data rate for CM1~CM4 channel environments and TABLE 5.5 lists the required SNR for PER=8% at 110Mb/s data rate. In the simplest CM1 channel environment (FIG 5.38), the simulated curve of proposed design is very similar to conventional design and perfect synchronization. In the typical CM2 channel environment (FIG 5.39), the proposed design degrades system performance from perfect synchronization with 0.1dB SNR loss for 8% PER, while conventional design degrades 0.05dB SNR loss. In the worse CM3 channel environment (FIG 5.40), performance degradation of proposed design increases to 0.16dB and conventional design increases to 0.1dB. The degradation of reducing tap number from128 taps to 32 taps is almost the same at CM2 or CM3 channel. In the worst CM4 channel environment (FIG 5.41), proposed design has 0.45dB SNR synchronization loss. It is acceptable for our system and reducing 75% correlation complexity from conventional

89

design. FIG 5.42 shows PER of proposed design at CM4 110 Mb/s, CM4 200Mb/s, and CM2 480 Mb/s data rate. The maximum SNR synchronization loss is 0.45 SNR for 8% PER at 110Mb/s data rate in CM4 channel environment. System required SNR and proposed design performance for 8%

PER are listed at TABLE 5.6. It shows that proposed design can meet system SNR requirement for 110M~480Mb/s data rates. FIG 5.43 is the transmission distance of proposed design and system requirement are listed at TABLE 5.7. The transmission distance of proposed design also meets system requirement.

90

1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 10

-2

10

-1

10

0

SNR [dB]

Perfect synchronzrion (FER=0)

Matched-filter with128 taps (conventional) Matched-filter with 32 taps (proposed) PER = 8%

FIG. 5.38 PER of CM1 channel at data rate=110 Mb/s, CFO=400KHz, SCO=40ppm

1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 10

-2

10

-1

10

0

SNR [dB]

Perfect synchronzrion (FER=0)

Matched-filter with128 taps (conventional) Matched-filter with 32 taps (proposed) PER = 8%

FIG. 5.39 PER of CM2 channel at data rate=110 Mb/s, CFO=400KHz, SCO=40ppm

PER of 90

th

per centile channel r ealization PER of 90

th

per centile channel r ealization

91

2 2.5 3 3.5 4 4.5 5 5.5 6

10

-2

10

-1

10

0

SNR [dB]

Ideal synchronzrion (FER=0)

Matched-filter with128 taps (conventional) Matched-filter with 32 taps (proposed) PER = 8%

FIG. 5.40 PER of CM3 channel at data rate=110 Mb/s, CFO=400KHz, SCO=40ppm

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 10

-2

10

-1

10

0

SNR [dB]

Perfect synchronzrion (FER=0)

Matched-filter with128 taps (conventional) Matched-filter with 32 taps (proposed) PER = 8%

FIG. 5.41 PER of CM4 channel at data rate=110 Mb/s, CFO=400KHz, SCO=40ppm

PER of 90

th

per centile channel r ealization PER of 90

th

per centile channel r ealization

92

TABLE 5.5 Required SNR for PER=8% of CM1~CM4 at 110Mb/s data rate

2 4 6 8 10 12 14 16 18 20

10

-2

10

-1

10

0

SNR [dB]

110M CM4 Perfect Sync 110M CM4 Proposed 200M CM4 Perfect Sync 200M CM4 Proposed 480M CM2 Perfect Sync 480M CM2 Proposed PER=8%

FIG. 5.42 PER at 110~480 Mb/s data rate for required worst CM channel CFO=400KHz, SCO=40ppm

SNR (dB) for PER=8% CM1 CM2 CM3 CM4

Perfect (FER=0) 5.08 5.26 5.64 6.27

Conventional (128 taps) 5.12 5.31 5.74 6.49

Proposed (32 taps) 5.13 5.36 5.80 6.72

SNR Loss (perfect vs 128 taps) 0.04 0.05 0.1 0.22 SNR Loss (perfect vs 32 taps) 0.05 0.1 0.16 0.45 SNR Loss (128 taps vs 32 taps) 0.01 0.05 0.06 0.23

PER of 90

th

per centile channel r ealization

93

Date Rate (Mb/s) CM Channel SNR loss(dB) Required SNR(dB) Proposed SNR(dB)

110 CM4 0.45 7.1 6.72

200 CM4 0.44 15.2 15.13

480 CM2 0.105 21.1 19.16

TABLE 5.6 Performance of proposed design for 8% PER of 90th percentile CM channel realization

FIG. 5.43 PER versus transmission distance at CFO=400KHz, SCO=40ppm

Date Rate (Mb/s) CM Channel Required Distance (m) Proposed Distance (m)

110 CM4 10 10.53

200 CM4 4 4.05

480 CM2 2 2.49

TABLE 5.7 Transmission distance of proposed design

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CHAPTER 6

Hardware Implementation and Measured Result

In this chapter, the architecture of the proposed low complexity frame synchronizer with 528MS/s throughput for 120M/bs~480Mb/s data rates UWB system will be introduced. Some measured result of hardware implementation, including area cost, power consumption, and CHIP micro-photo will be shown also.

6.1 Design Architecture

FIG 6.1 is architecture of the proposed frame synchronizer. It comprises a shared auto-correlator (used for packet detection and preamble timing detection), a tap-reduction matched-filter (used for FFT window detection), address-based register-files and a control unit.

Through 5-bit ADC working at 528MHz clock rate, the received signals will be divided into 4-parallel data paths. Thus each path transfers signals at 132MHz clock rate. Then shared auto-correlator starts to detect valid packet from noise signals. By using tap-reduction scheme with reduction factor ‘ω’=4, only one data path is needed to sent to the shared auto-correlator at 132MHz clock rate. And control unit controls a 4 to1 MUX to change the selected path in order for every quarter symbol time to balance multi-path interference. The pre-defined threshold of packet detection can be modified according to user’s requirement to maintain flexibility. By applying the register-sharing algorithm, address-based register-files were proposed to replace the conventional

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FIFO. It only updates one word data for every one cycle at 132MHz clock rate. After tap-reduction matched-filter finds out FFT window boundary, shared auto-correlator switches on dynamic-threshold calculator to decide first frame sync symbol and cuts the appropriate data for FFT.

RXRF 5-bitADC

6-bit I/Q 528MHzclock AGC

address-basedregister-files

…… sharedauto-correlator

controlunit packetdetectionthreshold dynamicthresholdcalculator

tap-reductionmatched-filter AFC

detectionvalid

FFT-windowboundary AGC valid

FFT-windowgate 4-bit I/Q estimated power

132MHzclock

To FFT parallel 32 words

F ram e Sy nc hro n iz er

FIG. 6.1 Architecture of proposed frame synchronizer

96

-FIG. 6.2 Detail architecture of tap-reduction matched-filter

97

6.1.1 Detail Architecture of Tap-Reduction Matched-Filter

FIG 6.2 shows the detail architecture of tap-reduction matched-filter for proposed frame synchronizer. When FFT window detection begins, register-files send stored data in parallel to compare with the matched-filter taps. To maintain time resolution of FFT window detection, tap-reduction matched-filter requires 528MS/s throughput. We achieve such high throughput by parallel architecture with 4 sub matched-filters and use tap-reduction scheme to eliminate enormous hardware cost resulted from parallel architecture. Thus each sub matched-filter only works at 132MHz clock rate. With a reduction factor ‘ω’=4, tap number will be reduced from 128 to 32. And register-files with 32 words are sufficient for the proposed design. Furthermore, register-files also need to work at 528MHz clock rate by using conventional parallel algorithm. It is impossible for .18um CMOS process and parallel 4 suits register-files with 132MHz clock rate is required, causing much gate-count cost and power consumption of register accessing. This problem also can be resolved by using register-sharing algorithm. By using the register-sharing algorithm, only one suit register-files with 32 words working at 132 MHz is needed, since stored data can be shared for the 4 sub matched-filters in parallel. TABLE 6.1 lists register-files requirement of the conventional parallel design and the proposed design.

Data bit Tap bit Data cost (I/Q) Tap cost Total cost

Conventional

4 1 1024(bit) 32(bit) 1056(bit)

Proposed

4 1 256(bit) 128(bit) 385(bit) TABLE 6.1 Register-files cost of the conventional and the proposed design

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To implement the cross-correlation algorithm used by matched filter, amount of complex multipliers is needed. But in our design, since sync sequences have constant amplitude with opposite polarities (1 or -1). The complex multiplier will be simplified to adder/substractor and we use the corresponding matched-filter taps to control function of adder/substractor. Then the 32 sub cross-correlation value of 32 compared taps will be summed and an squarer computes the cross-correlation power. Finally cross-correlation power of the 4 sub matched-filters sends to the 4-input peak sorter finding out the correct FFT window boundary. The peak sorter implements the TOP ‘5’ pre-cursor searching scheme [3] to resist multi-path interference.

6.1.2 Detail Architecture of Shared Auto-Correlator

FIG 6.3 shows the detail architecture of shared auto-correlator. At first, the complex multiplier computes sub auto-correlation value from incoming data selected by 4 to 1 MUX and previous data stored by register-files. Then the accumulator calculates the summation of each symbol ( A(X) in Eq 4.4 or D(Y) in Eq 4.6 ). When packet detection works, an squarer computes the power of auto-correlation result and AGC sends the estimated power of each symbol( P(X) in Eq 4.4) for normalization. The normalized auto-correlation power will be compare with the pre-defined threshold to detect the valid packet. When preamble timing detection works, a register will delay D(Y) one symbol time to get D(Y -1), and the squarer computes the power of D(Y ) adding D(Y -1). At the same time, dynamic threshold calculator generates the dynamic threshold Γ for comparator. To simplify our architecture, decision function (Eq 6.1) will be modified as Eq 6.2.

99

Since AGC tunes the correct RF gain and holds it after valid packet detection, the estimated

symbol power will be almost constant (PY2PY12PY22). Thus the denominator of Eq 6.1 can be eliminated. Moreover, the constant factor ‘ε’ of Eq 4.10 is set to 1/4 and can be replaced with

a bit shifter to shift right 2 bits. Thus the dynamic threshold calculator can be implemented for one bit shifter and one delay register.

D(Y)

FIG. 6.3 Detail architecture of shared auto-correlator

100

6.1.3 Address-Based Register-Files

(Addr==0)

FIG. 6.4 Architecture of Address-Based Register-Files

In the proposed design, FFT window detection needs register-files to work as FIFO for the vector operations of cross-correlation algorithm. The simplest FIFO constructed by shift registers is low gate-count cost. However, all used registers of FIFO shift their data at every cycle results in much dynamic power dissipation. For low power consideration, we replace FIFO with the address-based register-files as FIG 6.4, where “N” is the word length of register-files. When user asserts “EN” pin, an upper counter counts the “Addr” signals from 0 to N-1 repeatedly until “EN”

disabled. By comparing “Addr” signal, only one of the “N” register-files can access the input data to update its value and other N-1 register-files still hold their stored value. Therefore, it can save 1/N dynamic power dissipation of register-files from the shifter-based FIFO. The address-based

101

register-files are similar to RAM but it can support parallel data operations required by cross-correlation algorithm.

6.2 Hardware Measured Result

TABLE 6.2 shows the hardware synthesis results for proposed frame synchronizer in 0.18um cell library at clock rate=166MHz (clock period=6ns). The most area cost components of proposed design is the 4 sub matched-filters in parallel. Although 75% correlation complexity has been reduced from the conventional design by tap-reduction scheme, Parallel 4 sub matched-filters still involves 46% area of the proposed design. TABLE 6.3 is the area cost comparison between the proposed and the conventional design. It shows that the proposed design can save 65.65% area cost from the conventional design.

TABLE 6.2 Gate-count cost of the proposed frame synchronizer

Function Sub-module Gate Count (K)

Memory Address-based Register-files 7.2K

Auto-Correlator 3K Shared Auto-Correlator

Squarer 2.8K Parallel 4 Sub Matched-Filters 23K

Peak Sorter 4.4K

Tap-Reduction Matched-Filter

Squarer 5.6K

Control Unit & Others 3.6K

Total 49.6K

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Gate-Count Memory Matched-Filer Auto-Correlator & Others Total

The Conventional Design 28.8K 106K 9.6K 144.4K

The Proposed Design 7.2K 33k 9.4K 49.6K

Reduced Percentage 14.96% 50.55% 0.14% 65.65%

TABLE 6.3 Area cost comparison (0.18um cell library)

Power Consumption (mW) Memory Matched-Filer Auto-Correlator & Others Total

The Conventional Design 26.1 15.4 7.5 49.0

The Proposed Design 6.5 6.7 7.3 20.5

Reduced Percentage 40% 17.76% 0.4% 58.16%

TABLE 6.4 Power consummation comparison (post-layout simulation)

TABLE 6.4 is the power consummation table of post-layout simulation in 528MS/s throughput. Combining tap-reduction scheme and register-sharing algorithm, the proposed design saves 58.16% power consumption power consumption from the conventional design.

6.3 OFDM-Based UWB Baseband Transceiver

Our OFDM-based UWB Baseband transceiver was implemented by 0.18um standard CMOS process and tested completely. FIG 6.5 shows the microphoto of all Baseband Processor and the zoom-in microphoto of the proposed frame synchronizer. Core size of the proposed frame synchronizer is 2.35mm2, and it is only 6.53 % of the baseband transceiver core. The CHIP summary and measured result are listed in TABLE 6.5.

103

FIG. 6.5 Microphoto of the UWB transceiver CHIP in 0.18um process and room in Microphoto of the proposed frame synchronizer

Technology 0.18um CMOS, 1P6M

Supply Voltage 1.8V Core, 3.3V I/O

Package 208-pin CQFP

Die Size(including PADs) 6.5 x 6.5 mm2

Core Size 6.05 x 6.05 mm2

Gate-Count 1.064M

Maximum working Freq. 264MHz

Core Power Consumption at 480Mb/s (TX/RX)

523mW/575mW

TABLE 6.5 UWB transceiver CHIP summary

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CHAPTER 7

Conclusion and Future Work

According to the algorithm representation and performance analysis, a low complexity frame synchronizer for OFDM system applications is proposed. It comprises three main features: tap- tap-reduction scheme, register-sharing algorithm and dynamic threshold design. Tap-reduction scheme uses a reduction factor ‘w’ to reduce redundant computation and saves design complexity to 1/ω by reducing the received data in spread. Register-sharing algorithm resolves the growing size of register-files in linear when using parallel approaches. It shares the received data by data-rescheduling the compared taps of matched-filter in parallel. The proposed dynamic threshold improves frame error rate by varying the compared threshold with channel condition properly. To evaluate performance of proposed design, we simulate system packet error rate in multi-path channel for different platforms. In LDPC-COFDM system, synchronization loss for 8% PER in Intel channel model with RMS delay spread=5ns is 0.25~0.38 dB SNR at 120~480Mb/s data rates.

In MB-OFDM system, synchronization loss for 8% PER of the 90th percentile channel realization in IEEE 802.15.3a CM channel is 0.105~0.45 dB SNR at 110~480Mb/s data rates. The transmission distance of proposed design is 2.49~10.53 meters at 110~480Mb/s data rates, meeting system requirement of MB-OFDM-based UWB systems.

Among the proposed design, matched-filters save 50% gate-count and 18% power consumption by applying tap-reduction scheme to reduce the number of parallel complex multipliers to one quarter of conventional design. And register- files save 15% gate-count and 40%

105

power consumption by applying register-sharing algorithm to reduce required size of register-files to one quarter of conventional design. Overall, proposed design can save 65.65% gate-count and 58.16% power consumption from conventional parallel approaches with 128-tap matched-filter.

Although 58%~65% hardware cost is saved from conventional parallel approaches by tap-reduction scheme and register-sharing algorithm, matched-filter still dominates 66% gate count and 33% power consumption of proposed design If we can do FFT window detection by replacing matched-filter, a novel frame synchronizer with lower hardware cost can be implemented. At present, coarse band detection without matched-filters can complete frame synchronization successfully in AWGN channel. But for multi-path environment, serious boundary violation reduces the effective CP length and degrades the ability to resist ISI effect. Therefore, we will focus on improving the searching accuracy of FFT-window boundary to propose another matched-filter free frame synchronizer in the future.

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自傳

敝人在民國 70 年出生於台北市,出生後即居住於台北縣中和市。畢業於台 北縣永和市立網溪國小,台北縣永和市立永和國中,台北市立建國中學後,就 讀於國立交通大學電機與控制工程學系。92 年經由推薦甄試進入交通大學電子 研究所系統組,指導教授為李鎮宜博士。小學時期即對中國古典音樂養成濃厚 興趣,曾進入網溪國小國樂班就讀,並於高中時期加入建中國樂社。大學時期

敝人在民國 70 年出生於台北市,出生後即居住於台北縣中和市。畢業於台 北縣永和市立網溪國小,台北縣永和市立永和國中,台北市立建國中學後,就 讀於國立交通大學電機與控制工程學系。92 年經由推薦甄試進入交通大學電子 研究所系統組,指導教授為李鎮宜博士。小學時期即對中國古典音樂養成濃厚 興趣,曾進入網溪國小國樂班就讀,並於高中時期加入建中國樂社。大學時期

在文檔中 應用於正交分頻多工技術為基礎之低複雜度接收端基頻框架同步器 (頁 103-0)