CHAPTER 6 Hardware Implementation and Measured Result
6.2 H ARDWARE M EASURED R ESULT
TABLE 6.2 shows the hardware synthesis results for proposed frame synchronizer in 0.18um cell library at clock rate=166MHz (clock period=6ns). The most area cost components of proposed design is the 4 sub matched-filters in parallel. Although 75% correlation complexity has been reduced from the conventional design by tap-reduction scheme, Parallel 4 sub matched-filters still involves 46% area of the proposed design. TABLE 6.3 is the area cost comparison between the proposed and the conventional design. It shows that the proposed design can save 65.65% area cost from the conventional design.
TABLE 6.2 Gate-count cost of the proposed frame synchronizer
Function Sub-module Gate Count (K)
Memory Address-based Register-files 7.2K
Auto-Correlator 3K Shared Auto-Correlator
Squarer 2.8K Parallel 4 Sub Matched-Filters 23K
Peak Sorter 4.4K
Tap-Reduction Matched-Filter
Squarer 5.6K
Control Unit & Others 3.6K
Total 49.6K
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Gate-Count Memory Matched-Filer Auto-Correlator & Others Total
The Conventional Design 28.8K 106K 9.6K 144.4K
The Proposed Design 7.2K 33k 9.4K 49.6K
Reduced Percentage 14.96% 50.55% 0.14% 65.65%
TABLE 6.3 Area cost comparison (0.18um cell library)
Power Consumption (mW) Memory Matched-Filer Auto-Correlator & Others Total
The Conventional Design 26.1 15.4 7.5 49.0
The Proposed Design 6.5 6.7 7.3 20.5
Reduced Percentage 40% 17.76% 0.4% 58.16%
TABLE 6.4 Power consummation comparison (post-layout simulation)
TABLE 6.4 is the power consummation table of post-layout simulation in 528MS/s throughput. Combining tap-reduction scheme and register-sharing algorithm, the proposed design saves 58.16% power consumption power consumption from the conventional design.
6.3 OFDM-Based UWB Baseband Transceiver
Our OFDM-based UWB Baseband transceiver was implemented by 0.18um standard CMOS process and tested completely. FIG 6.5 shows the microphoto of all Baseband Processor and the zoom-in microphoto of the proposed frame synchronizer. Core size of the proposed frame synchronizer is 2.35mm2, and it is only 6.53 % of the baseband transceiver core. The CHIP summary and measured result are listed in TABLE 6.5.
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FIG. 6.5 Microphoto of the UWB transceiver CHIP in 0.18um process and room in Microphoto of the proposed frame synchronizer
Technology 0.18um CMOS, 1P6M
Supply Voltage 1.8V Core, 3.3V I/O
Package 208-pin CQFP
Die Size(including PADs) 6.5 x 6.5 mm2
Core Size 6.05 x 6.05 mm2
Gate-Count 1.064M
Maximum working Freq. 264MHz
Core Power Consumption at 480Mb/s (TX/RX)
523mW/575mW
TABLE 6.5 UWB transceiver CHIP summary
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CHAPTER 7
Conclusion and Future Work
According to the algorithm representation and performance analysis, a low complexity frame synchronizer for OFDM system applications is proposed. It comprises three main features: tap- tap-reduction scheme, register-sharing algorithm and dynamic threshold design. Tap-reduction scheme uses a reduction factor ‘w’ to reduce redundant computation and saves design complexity to 1/ω by reducing the received data in spread. Register-sharing algorithm resolves the growing size of register-files in linear when using parallel approaches. It shares the received data by data-rescheduling the compared taps of matched-filter in parallel. The proposed dynamic threshold improves frame error rate by varying the compared threshold with channel condition properly. To evaluate performance of proposed design, we simulate system packet error rate in multi-path channel for different platforms. In LDPC-COFDM system, synchronization loss for 8% PER in Intel channel model with RMS delay spread=5ns is 0.25~0.38 dB SNR at 120~480Mb/s data rates.
In MB-OFDM system, synchronization loss for 8% PER of the 90th percentile channel realization in IEEE 802.15.3a CM channel is 0.105~0.45 dB SNR at 110~480Mb/s data rates. The transmission distance of proposed design is 2.49~10.53 meters at 110~480Mb/s data rates, meeting system requirement of MB-OFDM-based UWB systems.
Among the proposed design, matched-filters save 50% gate-count and 18% power consumption by applying tap-reduction scheme to reduce the number of parallel complex multipliers to one quarter of conventional design. And register- files save 15% gate-count and 40%
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power consumption by applying register-sharing algorithm to reduce required size of register-files to one quarter of conventional design. Overall, proposed design can save 65.65% gate-count and 58.16% power consumption from conventional parallel approaches with 128-tap matched-filter.
Although 58%~65% hardware cost is saved from conventional parallel approaches by tap-reduction scheme and register-sharing algorithm, matched-filter still dominates 66% gate count and 33% power consumption of proposed design If we can do FFT window detection by replacing matched-filter, a novel frame synchronizer with lower hardware cost can be implemented. At present, coarse band detection without matched-filters can complete frame synchronization successfully in AWGN channel. But for multi-path environment, serious boundary violation reduces the effective CP length and degrades the ability to resist ISI effect. Therefore, we will focus on improving the searching accuracy of FFT-window boundary to propose another matched-filter free frame synchronizer in the future.
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自傳
敝人在民國 70 年出生於台北市，出生後即居住於台北縣中和市。畢業於台 北縣永和市立網溪國小，台北縣永和市立永和國中，台北市立建國中學後，就 讀於國立交通大學電機與控制工程學系。92 年經由推薦甄試進入交通大學電子 研究所系統組，指導教授為李鎮宜博士。小學時期即對中國古典音樂養成濃厚 興趣，曾進入網溪國小國樂班就讀，並於高中時期加入建中國樂社。大學時期 就讀於交通大學電機與控制工程學系時，曾獲得大一上至大三下各學期之書卷 獎，畢業成績為系上第一名，獲得中華民國斐陶斐榮譽學會榮譽會員。社團活 動以交通大學國樂社為主，參加過兩屆交通大學寒假國樂研習營與三屆北區大 專組國樂合奏比賽，並與團友多次參加學術晚宴伴奏。從大二修課後發現自己 對數位積體電路設計極感興趣，故大學畢業後推徵進入交通大學電子工程研究 所系統組，也獲得碩一下學期系統組書卷獎。研究領域為無線通訊接收端之基 頻框架同步器，其中以 IEEE 802.11a 規格與基於 OFDM 技術之 UWB 系統尤有心 得。碩士論文為應用於正交分頻多工技術為基礎之低複雜度接收端基頻框架同 步器( Study on Low Complexity Baseband Frame Synchronization for OFDM Applications)。