Timing Impacts

In a SSCG system, the frequency varies with time. So does the data if the transmitter uses the clock from the SSCG system. Despite of the modulation profiles, the clock waveform will look like that shown in Fig. 3.6(b).

(a) (b)

Fig. 3.6 Time domain behaviors (a) without modulating (b) with modulating

A. Cycle-to-Cycle Jitter

The cycle-to cycle jitter is not steady because it depends on the previous cycle time. From Fig. 3.7 we can see the relationship between cycle time and jitter.

Chapter 3 Basic of Spread Spectrum Clock Generator

Fig. 3.7 Diagram of cycle to cycle jitter

Here we will derive some formulas about cycle to cycle jitters. The period difference between normal frequency and maximum modulation frequency is:

( )

The number of cycles (N) that exist in the time interval that the modulated clock moves from f to_n

(

^{1− δ}

)

^f_n ^is

a v g

m

N f

= 2 f _(3.10)

,where f is the average frequency of the spread spectrum clock, and _avg f is the _m modulation frequency. From triangular modulation profile, we can derive the average frequency is

( )

a v g n

f = 1 − 0 . 5δ f (3.11)

Therefore, the cycle-to-cycle jitter due to spread spectrum clock can be expressed as

Chapter 3 Basic of Spread Spectrum Clock Generator

KHz modulation frequency, the cycle-to-cycle jitter is

( ) ( )

Fig. 3.8 Diagram of peak to peak jitter

Long-term jitter measures the maximum change in a clock’s output transition form its ideal position. Therefore, Eqn.(3.9) can be viewed as the long-term jitter of a down-spreading clock signal. Similarly, for a 1.2GHz spread spectrum clock with 0.5% triangular modulation and 31 KHz modulation frequency, the long-term jitter is

1 2

Thus, the cycle-to-cycle jitter of the spread spectrum clock is in a considerably small compared with non-spread clock signal. However, the long-term jitter of spread spectrum signal is significant.

Chapter 3 Principles of Fractional-N PLL

Chapter 4

Principles of Spread Spectrum Clock Generator

4.1 Concept of SSCG Using Switching Phase

In general, SSCGs include four types. The first type is digital processing circuit technique [13][14]. This method has speed limit of action. The second type is to modulate the divider [15][16][17][18][19][20][21] (Fig. 4.1) and the major problem is to design proper bandwidth. The third type is to modulate the control voltage of the VCO [22][23][24][25] (Fig. 4.2). It has the drawback about accurate in controlling spreading. Finally, the fourth type is to modulate the multiphase in the output of VCO [26][27][28][29](Fig. 4.3) and this is also the basic theorem about our proposed SSCG because that it owns lowest jitter in all the types [26]. For example, if the divider is divided by N, the minimum variation in type II is 1

N^, but the minimum variation in type IV is only 1

N P× ^. However, one drawback is its control jumping logic will cause jumping spur. This is due to regular sequence of jumping modulus, it would cause spurs in the spectrum. The modern solution is to use the ΣΔ modulator to solve it. It can cause randomization and noise shaping. In the following, we will introduce the switch phase mechanism and the principle of ΣΔ

Chapter 3 Principles of Fractional-N PLL

modulator.

Fig. 4.1 Type II of SSCG

PFD

up

dn Icp Vctr

Vref

CP LF

VCO

1/N

+ SSC

Modulator

Spread-Spectrum Clock

Fig. 4.2 Type III of SSCG

Fig. 4.3 Type IV of SSCG

4.2 The Switch Phase Mechanism

Fig. 4.4 is the timing diagram of 5 (P) phases from VCO. The time difference between any two phases is the same. We can see if the period of each phase isT_VCO, the time between previous phase and current phase is T_D =T_VCO/ 5 T= _VCO/ P,

Chapter 3 Principles of Fractional-N PLL

where P is the number of phase.

Fig. 4.4 Timing diagram of 5 phases from VCO

The output of VCO is feed into a divider which is divided by N. The period of divider output without switching phase is N T× _VCO =T_ref. If we jump one phase in

Fig. 4.5 Timing diagram of switching phase

So the period of the output from divider is longer theT , the charge pump will _ref charge the loop filter so that the V is higher and the period of the output from _C

Chapter 3 Principles of Fractional-N PLL

the output of the divider will be the same with T_REF. Thus, the new T_VCO^'must be less than the original T_VCO so that the new T will be the same as the original_ref T . _ref This method can be used to vary the oscillation frequency of the VCO.

Fig. 4.6 Simple jumping phase PLL

Fig. 4.7 Switching phase PLL using Boolean logic

Fig. 4.6 shows the basic architecture of switching phase PLL. In the locked state, f_REFis equal to divider output. Sof would finally equals _vco f_vco f (N_ref )

P

= + α

vco _ original

f (1 )

N P

= + α

× , whereαis the number of jumping phase. We incorporate the MUX into the feedback path and further replace the jumping control with Boolean logic as shown in Fig. 4.7. For M sequence of fref, if MUX jump one phase for A sequence and no jump for the following M-A sequence, then the output frequency can be derived as follows:

Chapter 3 Principles of Fractional-N PLL

The equivalent jumping ratio isA M. This value can vary between 0 and 1 in fine steps by proper choice of A and M.

vco ref

f f (N 1)

= × + P

vco ref

f =f ×N

Fig. 4.8 Periodic accumulation error phenomenon

There is a problem we will meet when we use the jumping logic. When we use counters to control the modulus of the MUX, there is a periodic accumulation error, as given by Fig. 4.8. In the first M-A output pulses of the divider, the MUX jump 0 phase and the phase error accumulates. Then the phase error is gradually compensated after MUX jump 1 phase for A cycles. Since the phase error grows to significant values, the amplitude of the LPF output waveform is quite large, yielding

Chapter 3 Principles of Fractional-N PLL

decrease the quality of communication, we should reduce it as much as possible. The most popular method is using ΣΔ modulator. We will explain it in detail in the next section.

4.3 Principles of ΣΔ Modulator

Because the reference spurs originate from the regular sequence of the MUX, we can eliminate spurs by randomize it. By randomization the choice of the jumping phase such that the average f_VCO is still given by f_REF (N )

P

× +α , which means

individual multiplier factors occur for only short periods of time, the systematic fractional sideband would be converted to random noise. Besides, we can shape the resulting noise spectrum such that most of its energy appears at large frequency offsets. Therefore, the noise in the vicinity of thef_REF is sufficiently small and the noise at high offsets is suppressed by the LPF of the PLL, as shown in Fig. 4.9. With the ΣΔ modulator [30], the MUX modulus is near pseudo-random sequence and the quantization noise is differentiated in the signal band. The quantization noise comes from the reason that the MUX only can jump X or X+1, not X.Y, where the dot denotes a decimal point and X and Y represent the integer and fractional parts.

Therefore, we can consider that the ideal MUX modulus X.Y is quantized to X or X+1 ( X+d(t) ). Fig. 4.10 is the Noise shaping by means of a ΣΔ modulator. Fig. 4.11 shows the sequence of the^{d t}

( )

, Y is always quantized to 0 or 1.

Chapter 3 Principles of Fractional-N PLL

Fig. 4.9 Randomization and Noise shaping to eliminate unwanted spurs

Fig. 4.10 Noise shaping by means of a ΣΔ modulator

Y d(t)

d(t) Y q(t)= + q(t) q(t) t

−

Fig. 4.11 Output waveform of decimal(t)

quantization +

Z^-1

+

Z^-1

input output

integrator differentiator

q_a

-A B

X Y

Fig. 4.12 Original ΣΔ modulator block diagram

The idea of ΣΔ modulator is to use an integrator and a differentiator, as shown in Fig. 4.12. The equation describe that the signal is through to the output, while the

Chapter 3 Principles of Fractional-N PLL

The original ΣΔ modulator encounters overflow problem. In order to solve this problem, we can put subtraction of differentiator to the input as a negative feedback system and the transfer function does not change. However, the quantization just passes the differentiator and its power is lowered at signal band. Besides, the feed-back circuit is more stable than the feed-forward circuit. Fig. 4.13 shows the improved ΣΔ modulator and the continuous is the transfer function.

Fig. 4.13 Improved ΣΔ modulator block diagram

1

B 1 A

1 z ⁻

= − ^{, (4.8)}

Chapter 3 Principles of Fractional-N PLL

We can get the final transfer function in z domain as follows:

(

¹

)

^a

o u t p u t = i n p u t + 1 + Z ⁻ q , (4.10)

whereq _a is the quantization. The implementation of ΣΔ modulator can be achieved by the accumulator. Fig. 4.14(a) shows the architecture of the accumulator and Fig.

4.14(b) shows its block diagram. In the same way, we can derive its transfer function in Eqn.(4.4), which is the same as Eqn.(4.3). input of the accumulator, B is the bit number of the accumulator and M is the maximum magnitude of the accumulator.

+ +

Fig. 4.14(a) ΣΔ modulator using accumulator (b) Block diagram of ΣΔ modulator Fig. 4.15(a) is the output waveform of the accumulator. Fig. 4.15(b) is the output waveform of the quantization error .We can see the overflow is either 0 or 1.

The qe[z] will compensate the difference value. As shown in Fig. 4.16, we can

Chapter 3 Principles of Fractional-N PLL

incorporate the ΣΔ modulator in the PLL to control the MUX modulus.

qe[z] t

(a) (b)

Fig. 4.15 Output waveform of (a) the accumulator (b) the quantization error

Fig. 4.16 Realization of ΣΔ modulator

It can be seen that, for a N-bit accumulator, the accumulator will produce an overflow on average A/2^B every cycle of the Fdiv clock. Thus the average jumping phase is

To get more insight into ΣΔ modulator, we should analyze it in analytic function. The optimal output signal of divider is in equation:

Chapter 3 Principles of Fractional-N PLL

And the actual frequency of divider is

( )

The normalized frequency error is

( )

^{d i v e}

The quantization phase noise is

( ) ( )

^{r e f}

( )

The noise transfer function in the discrete time domain can be converted into the continuous time domain by the following method.

Chapter 3 Principles of Fractional-N PLL

From Eqn.(3.11), we can get the final power spectral density of quantization noise is

In order to obtain effectively the noise shaping toward the higher frequency, the higher order ΣΔ modulator is required. Fig. 4.17 and Fig. 4.18 show the Implementation and block diagram of 2^nd order ΣΔ modulator. Thus we can get its transfer function as below:

[ ] [ ] (

¹

)

^{a 1}

Fig. 4.17 Implementation of 2^nd order ΣΔ modulator

Chapter 3 Principles of Fractional-N PLL

Fig. 4.18 Block diagram of 2^nd order ΣΔ modulator

Fig. 4.19 shows the common 3^rd order ΣΔ modulator: Multi-Stage Noise Shaping 1-1-1 (MASH 1-1-1)[32][33]. The block diagram is shown in Fig. 4.20.

Thus we can get its transfer function.

[ ] [ ] (

¹

)

^{a 1}

and get the final power spectral density of output noise.

( ) ( )

The output PSD is now proportional tof , revealing that the quantization noise ⁴ is suppressed in the signal band. As in general formula, if we use the i^th order ΣΔ

Chapter 3 Principles of Fractional-N PLL

modulator, the PSD of the phase noise is [34]

( ) ( )

Fig. 4.19 Implementation of 3^rd order ΣΔ modulator

Fig. 4.20 Block diagram of 3^rd order ΣΔ modulator

Chapter 3 Principles of Fractional-N PLL

overflow

(a)

Time(t) (b)

(c)

Fig. 4.21 d(t) of (a) 1^st order ΣΔ modulator (b) 2^nd order ΣΔ modulator (c) 3^rd order ΣΔ modulator

Fig. 4.21 shows the output of ΣΔ modulators. We can observe the output is more highly changeable of the higher order ΣΔ modulator. Thus, the higher order ΣΔ modulator can move the quantization noise to higher frequency and the low pass

Chapter 3 Principles of Fractional-N PLL

characteristic of PLL can filter out the noise.

Chapter 5 SSCG based on the switching phase

Chapter 5

Spread Spectrum Clock Generator

5.1 Introduction

In general, PLL can generate a stable clock to control operations, but have problems about timing jitter. PLLs with a low jitter output clock is an important issue in all communication systems. In this chapter, a low jitter phase-lock-loop (PLL) and a programmable spread-spectrum clock generator (SSCG) for Serial ATA using switching phase is presented. Low jitter PLL is achieved through VCO with low KVCO by using medium-threshold-voltage PMOS and passive resistance. The spectrum in the clock generator can be spread by 10 phases or 20 phases. Our SSCG for Serial ATA Specification is down spread 5000 ppm with a triangular waveform of modulation frequency 30~33KHz. The proposed circuit is fabricated in a 0.18-um CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 20ps and the maximum EMI reduction is -17.8dB in 20 phase spread spectrum mode which the power dissipation is only 28mw.

5.2 System architecture

Chapter 5 SSCG based on the switching phase

switching phase based on modify ΣΔ modulator is shown in Fig. 5.1. As implied by the name in this design, we can choose the SSCG spreading in 10 or 20 phases depending on the system specification. The advantage of spreading spectrum in 10 phases is power saving. The advantage of spreading spectrum in 20 phases is lower timing jitter.

Fig. 5.1 The architecture of SSCG based on switching phase

The programmable SSCG is consists of PFD, CP, LF, VCO, MUX, divider, modulation profile generator, modified delta-sigma modulator and MUX control circuit.

Programmable modulation profile generator generate a proper periodic triangular profile into the modified ΣΔ modulator to generate number of phase jumping fed to the MUX control circuit to select MUX output. The advantage of using ΔΣ modulator is that it can shape the noise to a higher frequency and smooth effect of the PLL loop and results in continuous frequency modulation from a discrete staircase input.

Proper controlling of programmable modulation profile generator can control

Chapter 5 SSCG based on the switching phase

modulation frequency and modulation deviation. The method we use to spread spectrum to fit with the specifications of serial-ATA 6Gbps version which is describe in the following sections.

If the output of modified ΣΔ modulator is 0, the MUX control circuit choose the original phase as the MUX output signal, then f_spread = ×N f_ref

wheref_spread =f_nonspread(1.2GHz),f_ref =100MHz. When the output of modified ΣΔ modulator is 1, the MUX chooses an early phase (because of down-spread) as output signal and _{spread ref} 1

f f (N )

= −P , where P is the number of phase. For the same reason, if the output is 2: _{spread ref} 2

f f (N )

= − P . As we know, the relationship between input and output of ΣΔ modulator is A / M, where A is the input number of the modulator, M is the maximum magnitude of the accumulator in the modulator. Thus, we have:

s p r e a d r e f change between two different specified frequencies (Fig. 5.2).

Fig. 5.2 The variation of frequency in spread spectrum

Chapter 5 SSCG based on the switching phase

In order to conform with Serial-ATA specification (Table 5.1), we choose 5-bits accumulator to construct the modified ΣΔ modulator ( M 2= ^B =2⁵ ). In every modulation period (30 ~ 33us), we set A to be 19 to achieve -5000 ppm spread spectrum frequency range (in the situation of P=10, N=12, M=32, modulation deviation= A / M 19 / 32

4947.9ppm

N P 12 10

− = − = −

× × ). Moreover, if we want to decrease the

jitter, we can use interpolators to produce 20 phases from 10 phases in 5 stage delay cells. Then, we can also spread spectrum in 20 phases by setting A=38 to fit with modulation deviation -5000ppm (modulation deviation = A / M

−N P = -4947.9ppm). Other frequency between 0 to -5000ppm will also be generated by alternating the amount of input number to generate different frequency.

Table 5.1 SSCG in Serial-ATA specifications

SSCG Parameter Limit Range

Min 30KHz Spread Spectrum

Modulation Frequency Max 33KHz

Min -5000ppm Spread Spectrum

Modulation Deviation Max 0ppm

5.3 Behavior Simulation

Because of the great amount of gates counts in the phase-locked loop, the closed-loop simulation with HSPICE will take a lot of time. In order to rapidly and approximately know the behavior of PLL, we use SIMULINK to test and verify system parameters and transient response. Furthermore, we can observe the way the frequency of VCO is locked and the spectrum of the output of VCO is spread. Finally, we can design our chip according to the parameters in SIMULINK. Fig. 5.3 shows the SSCG behavioral model built in SIMULINK.

Chapter 5 SSCG based on the switching phase

(a)

(b)

(c)

Fig. 5.3 SIMULINK model of the SSCG (a) SSCG based on the PLL

Chapter 5 SSCG based on the switching phase

Fig. 5.4 shows the average output of 1^st order ΣΔ modulator and the PSD of 1^st order ΣΔ modulator

(a) (b)

Fig. 5.4 (a) Average output (b) PSD of 1^st orderΣΔ modulator

Fig. 5.5 is the open loop Bode plot and close loop Bode plot respectively. We can observe that the phase margin is 60.6° and f-3db=14.8M rad/s /2π =2.35MHz.

(a) (b)

Fig. 5.5 Frequency response of (a) Open Loop Bode Plot (b) Close Loop Bode Plot Fig. 5.6 shows the transient response of the PLL without and with spread spectrum respectively. We can see the frequency in Fig. 5.6(a) is locked and stable. In Fig. 5.6(b), we use the built in blocks in the Matlab to construct the triangular

Chapter 5 SSCG based on the switching phase

waveform to control the input of ΣΔ modulator. We can observe that the PLL also exhibit its frequency like a triangular waveform.

(a) (b)

Fig. 5.6 (a) Frequency of VCO without SSCG (b) Frequency of VCO with SSCG

Fig. 5.7 (a) and (b) is the spectrum of VCO in the PLL without and with SSCG.

We can see the power spectrum at 1.2GHz is -3.5dB before spreading spectrum. After spreading spectrum, the power rapidly decrease to -22dB.

Power(dB)

Power(dB)

(a) (b)

Fig. 5.7 (a) Spectrum of VCO without SSCG (b) Spectrumof VCO with SSCG

Chapter 5 SSCG based on the switching phase

5.4 Circuit Implementation

5.4.1 Phase / Frequency Detector

Fig. 5.8(a) show the most popular circuit of PFD, because it have advantage of low power, high speed, good dead zone effect, and good lock in phase and frequency.

Because the behind charge pump need two different signals to drive, so the single to different circuit (Fig. 5.8(b)) is preserved. But there is different delay between these two paths (UP and UP_b), it will produce large sharp spikes on charge pump current [35]. So that we plus 1 transmission gate on the way of UP_b. Fig. 5.9 is the dynamic DFF we adopt. It has the advantages of avoiding charge sharing effect, reducing data dependence jitter, reducing spike, reducing pre-discharge and noise’s influence effect, and optimizing critical path delay.

D Q

Fig. 5.8 Schematic of (a) PFD (b) Single to Different circuit

Fig. 5.10 is the timing diagram of PFD working operation. If the CLKOUT leads the REF, the UP signal will be high until the REF arrives. At the meantime, the RESET will produce a pulse signal to DFF to suspend charging or discharge. The charging time or discharge time is proportion to the phase difference between REF and CLKOUT. If the time difference between them is too small, owing to the finite rising time and falling time resulting from the capacitance, the pulse may not have

Chapter 5 SSCG based on the switching phase

enough time to reach a logical high level, failing to turn on the charge pump switches.

This is called dead zone. The dead zone would accumulate jitter. So we add the delay on the path of reset to have enough time to turn on MOS even the time difference is very small. Thus, zero dead zone is achieved (Fig. 5.11).

Fig. 5.9 Circuit of dynamic DFF

Fig. 5.10 Timing diagram of PFD

Chapter 5 SSCG based on the switching phase

zero dead-zone

Phase error

Charge Current

Zero dead-zone

(a) (b) Fig. 5.11 Timing diagram of Zero dead zone

5.4.2 Charge Pump

The charge pump (CP) is composed of current source and switches (Fig. 5.12). It converts digital signal from PFD into analog signal to control the amount of charging or discharging voltage which controlling the oscillator’s frequency. Traditional charge pump (Fig. 5.12(a)) are popular before because they don’t need an additional loop filter and offer low-power consumption with tri-state operation. However, it has many problems. For example, when the switches are OFF, the voltage at the output capacitor C is floating, while the voltages at the sources of PMOS and NMOS are _L rapidly pulled to VDD and GND respectively. Due to the non-ideal characteristics of the MOS switch, such as charge injection and clock feed-through, this rapid change in the source voltages creates glitches in the capacitor current, which results in a jump in

The charge pump (CP) is composed of current source and switches (Fig. 5.12). It converts digital signal from PFD into analog signal to control the amount of charging or discharging voltage which controlling the oscillator’s frequency. Traditional charge pump (Fig. 5.12(a)) are popular before because they don’t need an additional loop filter and offer low-power consumption with tri-state operation. However, it has many problems. For example, when the switches are OFF, the voltage at the output capacitor C is floating, while the voltages at the sources of PMOS and NMOS are _L rapidly pulled to VDD and GND respectively. Due to the non-ideal characteristics of the MOS switch, such as charge injection and clock feed-through, this rapid change in the source voltages creates glitches in the capacitor current, which results in a jump in

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