Programmable Voltage-Controlled Oscillator

Voltage-Controlled Oscillators (VCO) is one of the most important elements in the PLL and critically determines the performance of a frequency synthesizer, such as loop gain, linearity, tuning range, central frequency and etc.

Fig. 5.17 Scheme of voltage control oscillator

In order to design a PLL used in Serial-ATA 6Gbps, we adopt a 5 stage ring oscillators which has 10 phases and oscillate in 1.2GHz. Fig. 5.17 is the schematic of the VCO structure.

Because the operation speed is very faster, we hope the jitter is less. There is an effective way to reduce jitter if we can decrease the KVCO. There will be obvious spur in frequency domain even if a little jiggles in VC if the KVCO is large. The design below is to achieve this goal.

The basic bias replica circuit is presented in [39]. We use the medium-threshold PMOS and resistance instead of nominal-threshold PMOS in symmetric load (Fig.

5.18). The bias replica circuit translates VC to vco_bp and vco_bn to bias the PMOS and NMOS in delay cells and copy the VC to vco_bp. Because it isolates VC from VCO, the noise in VCO will not affect VC directly. The bias-replica circuit will have good behavior in anti-noise, anti-temperature variation, and anti-process variation.

Chapter 5 SSCG based on the switching phase

Fig. 5.18 Bias replica circuit

The basic delay call is presented in [40]. The delay cell is composed of a symmetric load and a voltage controlled current source. Similarly, we add the medium-threshold PMOS (M5~M8) and resistance (R1, R2) to replace nominal-threshold PMOS in symmetric load (Fig. 5.19(a)). The resistance variation ratio of the symmetric load is related with oscillating frequency variation ( Kvco ) seriously.

(a) (b)

Chapter 5 SSCG based on the switching phase

If theKvco is high, there will be large jitter in the output of the VCO from the litter jiggle of theV . Thus, we want to have a low_C Kvco in our PLL. So we use the medium threshold PMOS transistors and passive resistance in the load of delay cells, interpolators and the bias replica circuit to achieve this goal. Table 5.2 is the comparison in PMOS and NMOS at variousV . There are four mainly advantages in _t this design:

1. The working range in V will be larger: The medium threshold voltage _C (0.24v) PMOS in bias replica circuit (M1~M4 in Fig. 5.18) will work correctly even if the V higher. As a result, the Kvco will decrease because of large _C control voltage range ofV . _C

2. Decreasing the process variation: We can decrease the process variation by increasing the gate length. But the oscillation frequency will not reach the frequency we need if we use normal threshold (0.51v) PMOS. So we can use medium threshold PMOS instead of normal threshold PMOS to raise the oscillator frequency and can also decrease the process variation (Fig. 5.19(a)).

3. Its operation will be in the deep saturation region: in this design, the medium threshold PMOS will work in more deep saturation region than in the normal threshold PMOS at the same frequency. In actual, the slope will be less and the Kvco will be smaller.

4. The passive resistance will decrease the velocity variation in the symmetry load: We add a proper passive resistance in the symmetric load.

Although the speed will increase, the resistance variation will decrease.

Consequently, the Kvco will be decreased again.

Chapter 5 SSCG based on the switching phase

Table 5.2 PMOS and NMOS in 0.18um CMOS NORMAL Vt

Fig. 5.20 shows the characteristics of symmetric load and resistor to VCO. The current after adding resistor increases, in other words, the resistor decreases. Thus, the velocity variation decreases.

Fig. 5.20 characteristics of symmetric load and resistor to VCO

Chapter 5 SSCG based on the switching phase

KVCO= 1310MHz/V

Vcontrol(V) (a)

Frequency(Hz)

(b)

Frequency(Hz)

(c)

Fig. 5.21 Characteristics of VCO (a) with normal threshold PMOS (b) with medium threshold PMOS(c) with medium threshold PMOS and passive resistance in the symmetric load.

Chapter 5 SSCG based on the switching phase

Fig. 5.21 is the frequency versus V curves. In the original circuit, the K_C VCO is 1310MHz/V. Replaceing with medium threshold PMOS transistors, the KVCO

becomes 1080MHz/V. Finally, after we add passive resistors, the KVCO decrease to 577MHz/V. The area and power is quite the same as the original design.

Frequency(Hz)

Fig. 5.22 Simulation results of the voltage-controlled oscillator

Fig. 5.22 shows the simulation of our final Kvco curve for different corner case. My central frequency is 1.2GHz at 0.74v in TT case. We can observe the frequency range covers 1.2GHz and Kvco is roughly 600MHz/V in each corner case.

Furthermore, in order for the Kvco curve to cover 1.2GHz under the process variation or parasitic capacitance, we design the upper limit (1.6GHz) is double lower limit (1.0GHz).

In the SSCG aspect, we use interpolators (Fig. 5.19(b)) [41] to generate 20 phases so as to spread the spectrum in a more precise way. The current ratioαdetermines the interpolating phase to be near the leading phase or the lagging phase. When α is smaller than 0.5, the lagging phase controls large portion of current and dominates the interpolated phase. The size of interpolators should be the same as the delay cells. Fig. 5.23 is the diagram in the outputs of ring oscillators and interpolators. In our design, we use two bias circuits: one for ring oscillators, and another for interpolators. Thus, when we want to spread spectrum in 10 phases, we

FF

TT

SS

Chapter 5 SSCG based on the switching phase

can turn off the bias to shut down the interpolators to saving power. But this will cause more jitter in time domain. For example, there will be 8333ppm if jumping 1 phase in 10 phases SSCG ( 1 1

N P 12 10=

× × ). On the contrary, it only changes 4166ppm in 20 phases SSCG ( 1 1

N P 12 20=

× × ). Consequently, we can choose spread spectrum in 10 or 20 phases depending on our need, such as power saving or low jitter in time domain.

Fig. 5.23 Diagram of ring oscillators and interpolators

Chapter 5 SSCG based on the switching phase

Fig. 5.24 VCO output buffer

The swing of the output in the delay cells will different for differentV . In order _C that the divider behind the VCO will work correctly, the input wave should be full swing. We add the output buffer to the delay cells so that it will full swing and increase their driving ability (Fig. 5.24). The size of OP should be as small as possible to reduce the loading of delay cells. Fig. 5.25 is the diagram before and after buffer.

after buffer

after buffer

after buffer

Fig. 5.25 Diagram of delay cell output and buffer output

Chapter 5 SSCG based on the switching phase

5.4.5 Divider

Fig. 5.26 Schematic of divider

Asynchronous divider has less power consumption but induces larger jitter due to jitter accumulation. On the contrary, synchronous divider has no accumulation but has larger capacitance loading. Because that REF is 100MHz and the output frequency is 1.2GHz, we need a circuit which can divide 12. Here we adopt a synchronous divider which divided by 3 and an asynchronous divider which divided by 2 (Fig. 5.26). Because asynchronous divider can spread the input jitter equally, we put the divider which is divided by 2 at the first stage. Then we can have duty cycle of 50% in the output wave, we put the same divider at the last stage. Hence, we put the divider which is divided by 3 at the middle stage. Finally, in order to reduce jitter accumulated by asynchronous circuit, we put a D flipflop after the divider. Fig. 5.27 is the timing diagram of the divider.

Fig. 5.27 Time diagram of divider

Chapter 5 SSCG based on the switching phase