SSCG System

Here we show some important simulation results about our low jitter PLL and programmable SSCG. The post-simulation of VC acquisition of PLL is shown inFig.

5.32. Fig. 5.33 is the diagram of phase1~phase5 in VCO (see Fig. 5.17). Fig. 5.34 is the diagram of these 5 phases delay time. We summarize the difference in 5 phases delay time in 100 stable cycle time and shown in Fig. 5.35. Each of these is comparing with 166.6666ps and listed in percentage. The delay time is depending on parasitic capacitance and the error (1ps) with standard delay (166.6666ps) is within

Chapter 5 SSCG based on the switching phase

our accept range.

Fig. 5.32 Post-simulation of VC acquisition of PLL

Fig. 5.33 Post-simulation of 5 phases in VCO

Fig. 5.34 Diagram of 5 phases delay time

Chapter 5 SSCG based on the switching phase

Fig. 5.35 Difference in 5 phases delay time (Post-Simulation)

Fig. 5.36 shows the rising peak-to-peak jitter of 2.46ps and falling peak-to-peak jitter of 3.1ps in post-simulation. Carrier Spectra without spread spectrum is 0dB at 1.2GHz after PLL locked is shown in Fig. 5.37.

P-P jitter=2.46ps P-P jitter=3.1ps (600 cycles) (600 cycles)

Fig. 5.36 Peak to Peak jitter of PLL

Chapter 5 SSCG based on the switching phase

Power(dB)

Fig. 5.37 Carrier Spectra without spread spectrum (0dBV @ 1.2GHz)

Fig. 5.38 shows the VCO control voltage in the 10 and 20 phases SSCG. We can obviously find that the control voltage is similar to triangular wave (modulation profile). Fig. 5.39 is the carrier spectra in 10 and 20 phases SSCG respectively. The spectrum is spread over a wider bandwidth, and therefore reduces the peak amplitude.

Here the reduction of carrier amplitude is about 17.6dB and 17.8dB. If we want to compare the advantage in time domain about 10 phases and 20 phases SSCG, we can observe their Peak to Peak jitter (Fig. 5.40) or their Cycle to Cycle jitter (Fig. 5.41).

We can see the jitter in 10 phases SSCG is larger than 20 phases SSCG from Fig. 5.40.

In other words, the variation in timing and data is more violent. This is not good for clock/data recovery (CDR) and will increase its difficulty for recovering data. From Fig. 5.41, we also can conclude that the cycle time variation in 10 phases SSCG is more enormous than 20 phases SSCG. But an obvious drawback in 20 phases is consuming more power than 10 phases SSCG.

Chapter 5 SSCG based on the switching phase

31KHz

Voltage(V)

31 KHz

Voltage(V)

(a) (b)

Fig. 5.38 VCO control voltage in (a) 10 and (b) 20 phases SSCG

-17.6dB

-4502ppm

Frequency(Hz)

-17.8dB

-4571ppm

Frequency(Hz)

Power(dB)

(a) (b)

Fig. 5.39 Carrier Spectra with spread spectrum in (a) 10 and (b) 20 phases SSCG

86ps 91ps

Time(t)

78ps 83ps

Voltage(V)

(a) (b) Fig. 5.40 P-P jitter in (a) 10 and (b) 20 phases SSCG

Chapter 5 SSCG based on the switching phase

Fig. 5.41 Cycle to Cycle jitter in 10 and 20 phases SSCG

The simulated performance of the proposed low jitter PLL is summarized in Table 5.5. PLL performance in corner cases is listed in Table 5.6.

Table 5.5 PLL performance summary

Items Performance

Technology TSMC 0.18um 1P6M CMOS

Power Supply 1.8V

Crystal Frequency 100MHz

VCO Center Frequency@Vctr=0.74v 1.2GHz

VCO Tuning Range 1.0~1.6GHz

KVCO 600MHz/V

Settling Time <5μs

Cycle to Cycle Jitter 1ps

Peak to Peak Jitter 20ps

RMS Jitter 3ps

Core Area PLL:355um x 240um

SSCG Control Circuit:95um x 210um Loop Filter

C1=50.0pf C2=3.6pf R=6.8kΩ

VCO Power Consumption 11mW

Total Power Consumption 13.6mW

Chapter 5 SSCG based on the switching phase

Table 5.6 PLL performance in corner cases

TT post simulation FF post simulation SS post simulation

Power Supply 1.8 V 1.8 V 1.8 V

Crystal Frequency 100MHz 100MHz 100MHz

VCO Center

Consumption 11.0mW 12.5mW 9.8mW

CP Power

Consumption 1mW 1.2mW 0.8mW

Total Power

Consumption 13.6mW 15.5mW 12.5mW

Table 5.7 Programmable SSCG performance comparison

Table 5.7 shows the comparison between 10 and 20 phases SSCG. The interpolator power consumes 9.5mW in 20 phases SSCG and don’t need in 10 phases SSCG. So the total power in 20 phases is more than in 10 phases SSCG. However, the jitter in 10 phases SSCG is larger than in 20 phases SSCG. In the case of EMI

10 phase SSCG 20 phase SSCG

Interpolator Power --- 9.5mw

SSCG Control

Circuit Power 4mw 4mw

Total Power 17.8mW 27.8mW

EMI Reduction -17.6dB -17.8dB

Modulation Deviation 0ppm ~ -4502ppm 0ppm ~ -4571ppm

Cycle to Cycle jitter 9ps 6ps

Chapter 5 SSCG based on the switching phase

reduction, there is no obvious difference in 10 phases and 20 phases SSCG. The main reason is that although the charge or discharge time is different in 10 and 20 phases SSCG, the passing frequency is the same. So you can choose spreading spectrum in 10 phases or 20 phases depends on your concern in power or timing issue.

Table 5.8 Comparison of SSCG performance Our Work ISSCC2005

Technology 0.18um 0.18um 0.18um 0.15um 0.35um

Modulation

Frequency 1.2GHz 1.5GHz 1.5GHz 1.5GHz 266MHz

Modulation

Table 5.8 shows the comparison of SSCG performance. We can see the power consumption in my design is very low comparing with other chips. The peak to peak jitter is also very small in our design comparing with other paper. Besides, the maximum power reduction is also pretty good in my SSCG performance. One of the reason about the maximum power reduction in [43][44] are larger than mine is its

Chapter 5 SSCG based on the switching phase

frequency span is 7.5MHz (my frequency span is 6MHz). The more frequency span, the more EMI reduction can be achieved.