Power Amplifier

The output stage of the low-power 1.4-GHz transmitter is a class-A power amplifier (PA) with resistor feedback network. The PA is composed of MPA, LD, CD, R_f, and C_f, as shown in Fig. 4.1. The on chip inductance L_D is used as a RF choke, CD completes output power matching of the PA, and Rf and Cf form a feedback network for stability consideration. The peak transmit power of the transmitter is 4 dBm, so a high linear PA is needed here. In this transmitter design, a class-A amplifier is employed in the PA stage due to the advantage of high linearity [7], which is critical for this work. The power consumption and the efficiency are other two specifications the transmitter must meet. The maximal total power consumption of the transmitter is 25 mW, and the efficiencyη which is defined in eq. (4.1) of the transmitter must be higher than 10%.

η

(4.1) The class-A amplifier is biased in the condition of that the transistor is always

-20 -16 -12 -8 -4 0 4

-12 -10 -8 -6 -4 -2

M ix e r c o n v e rs io n g a in ( d B )

Input IF power (dBm)

Mixer size = 16 μm / 90 nm Mixer size = 24 μm / 90 nm Mixer size = 32 μm / 90 nm

Fig. 4.3 Conversion gain of the passive CMOS SSB mixer

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ON and it always conducts the quiescent current. The signal conduction angle of class-A amplifier is 360^o, as shown in Fig. 4.4.

There are two types of RF transistors in UMC CMOS 90-nm technology, which are 1-V RF MOS and 2.5-V RF MOS. Under the same current bias condition, 1-V RF MOS has higher transconductance than 2.5-V RF MOS has, but 2.5-V RF MOS has higher linearity than 1-V RF MOS has. For the linearity consideration, the 2.5-V RF nMOS is employed to realize the PA stage. Fig. 4.5 (A) and (B) show the I-V curve of the 2.5-V RF nMOS .

Fig. 4.5 (a) shows I_D-V_GS curve of the 2.5-V RF nMOS. In the real design environment, there is no specific corner point of the threshold voltage Vt in the I_D-V_GS curves. Here we define that the corner point is located at the cross point of the extended tangent lines of the pinch-off region and the saturation region. Vt can

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Fig. 4.4 Signal conduction angle of class-A amplifier

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be figured out by the above definition, and its value is 0.7 V. Therefore, the gate voltage bias VBias of the class-A PA must be higher than 0.7 V for the 360^o signal conduction angle. Fig. 4.5 (b) shows the I_D-V_DS curve of the 2.5-V RF nMOS, and the load line analysis. A linear amplifier always operates in the saturation region which is between the triode region and the breakdown region. In the load line analysis, Vmin, which is defined as Vmin = VGS - Vt, is the lowest output voltage. The corresponding current of V_min is the maximum output current I_max. The breakdown voltage of the 2.5-V RF MOS is very high when VGS is low. ID increases very slowly as V_GS = 0.7 V, as shown in Fig. 4.5 (b), so the transistor breakdown is not the limitation of linearity. Here we define that Vmax is the VDS with 1 dB increasing of ID

in the saturation region as V_GS = V_t = 0.7 V, its value is equal to 2.8 V. The corresponding current of Vmax is the minimum output current Imin. From the above definition, the maximum output power of the trasistor can be expressed as

(4.2) By eq. (4.2), the maximum output power in different cases can be obtain. For example, the output voltage is from 0.9 V to 2.8 V as input voltage V_in is from 1.6 V to 0.7 V, as shown in Fig. 4.5 (b). The corresponding Imax and Imin are 57.9 mA and 3.1 mA, respectively. Therefore, the maximum output power is . The corresponding gate

voltage bias VBias is , and VDS is . Under this bias condition, the DC current ID can found out in Fig. 4.5 (a), and ID in this case is 26.67 mA. The RF choke used in the PA is a 9.5-nH inductance, and its parasitic resistor is 6 Ω. Therefore, the appropriate VDD is . The DC power consumption is

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Fig. 4.6 (a) and (b) show that the maximum output power is higher with higher DC power consumption. However, the maximum output power is not proportional to the DC power consumption. With VBias increasing, the growth rate of power consumption increases, but the growth rate of the maximum output power decreases.

Therefore, there is a VBias of the highest efficiency can be obtained, as shown in Fig.

4.6 (b). The V_Bias of the highest efficiency is 0.95 V and the efficiency changes slowly as VBias is from 0.9 V to 1.0 V. The corresponding VDD of the VBias in this range is from 1.67 V to 1.8 V, and the same bias condition of high efficiency would be obtained in the different transistor sizes. In this work, the VBias is chosen to be 0.92 V, the corresponding V_DD is 1.7, and the transistor size is 288μm/0.36μm. This PA can achieve the simulated performance of OP1dB = 6 dBm and 19.2% efficiency with 20.7 mW power consumption.

Fig. 4.7 shows the output power matching by Smith chart in the simulation. S11

0.7 0.8 0.9 1.0 1.1 1.2

Fig. 4.6 (a) Maximum output power and power consumption versus VBias (b) Gain and efficiency versus V_Bias

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is the output impedance, and maker M1 marks the impedance at 1.4 GHz, which is . S22 is the impedance looking into the matching network, and maker M2 marks the impedance at 1.4 GHz, which is . The value of CD is chosen to be 1.8 pF to achieve the output impedance matching.

R_f and C_f form a feedback network for stability consideration. Fig. 4.9 (a), (b), (c), and (d) are the stability simulation results of PA by the simulation setup in Fig.

4.8 (a) and (b). Fig. 4.9 (a) shows the source stability circle and input return loss S11 of PA without feedback network. Fig. 4.9 (c) shows the load stability circle and output return loss S22 of PA without feedback network. In Fig. 4.9, the areas inside the blue circles and outside the red circles are the areas of stable input and output impedance at each frequency. The input and output impedance of the PA should be designed in the stable impedance area. In Fig. 4.9 (a), the input impedance points are near the unstable area. In Fig. 4.9 (c), some output impedance points are in the unstable area. Rf = 2.5 kΩ and Cf = 2.7 pF are used to complete the feedback network to solve the stability issue, as shown in Fig. 4.8 (b). Fig. 4.9 (b) and (d) show the simulation results of stability of the PA with the feedback network. In Fig.

4.9 (b), the input impedance points shift a little bit away from the unstable area. In Fig. 4.9 (d), all output impedance points are in the stable impedance area.

MPA

Fig. 4.7 Output power matching of the PA

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Fig. 4.9 Stability simulation results of PA

(a) Source stability circle and input impedance S11 of PA without feedback network (b) Load stability circle and output impedance S22 of PA without feedback network (c) Source stability circle and input impedance S11 of PA with feedback network (d) Load stability circle and output impedance S22 of PA with feedback network

M

Fig. 4.8 (a) Stability simulation setup of the PA without feedback network (b) Stability simulation setup of the PA with feedback network

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