3 Testing of a Low-V MIN Data-Aware Dynamic-Supply 8T SRAM
4.2 Previous Circuit-Level GOS Models
In this section, we will introduce three circuit-level GOS models: the Bi-dimensional model [4-11] and two nonlinear non-split models ([4-21] and [4-22]). The Bi-dimensional model is the first GOS model and the two nonlinear non-split models [4-21] [4-22] were proposed for representing minimum-size devices. For both the nonlinear non-split models [4-21] [4-22], we will validate their accuracy by comparing to the TCAD-simulation results and analyze the corresponding limitations.
4.2.1 Bi-dimensional model
Figure 4-5 shows the schematic of a 5x5 Bi-dimensional GOS model, which contains an MOSFET array with all the gates connected together. The sources of the left-most five MOSFETs are connected together as the source terminal of the GOS-impacted MOSFET, while the drains of the right-most five MOSFETs are connected together as the drain terminal. The shorting effect caused by the GOS is represented by the resistor, denoted as RGOS, which connects the gate
terminal to the center of the connected MOSFET array. Since this model is composed of multiple minimum-size MOSFETs, their combined effect cannot represent a single minimum-size MOSFET with a GOS, which limits the application of this GOS model on relatively old technologies.
Fig. 4-5. An exemplary Bi-dimensional model with 5x5 internal points [4-11].
4.2.2 Nonlinear non-split model 1 - JET_03
Figure 4-6 shows the nonlinear non-split model JET_03 proposed in [4-21], which utilizes three MOSFETs (named Tm, Ta, and Tb in Figure 4-6) and a resistor (named RGOS in Figure 4-6) to describe a GOS-impacted MOSFET.
According to the fitting guide provided in [4-21], the size of Tm is tuned to fit the reduced saturation drain current (ID(SAT)). The Ta and Tb are tuned to fit the negative drain current and the gate current, respectively. The resistor RGOS is used to refine the fitting.
Fig. 4-6. The nonlinear non-split GOS model, JET_03, proposed in [4-21].
Figure 4-7(a) shows the IDVD fitting results by using JET_03 model to represent a nMOS with a 2.5nm-radius GOS. As the result shows, the maximum ID(SAT) and the negative ID(off) can be described quite well by JET_03 model in Figure 4-7(a), but the other IDVD curves with different VG cannot. Next, Figure 4-7(b) shows the HSPICE transient simulation of an inverter whose nMOS contains the same size GOS modeled by JET_03 model as that in Figure 4-7(a).
As the result shows, the inverter’s response modeled by JET_03 model cannot match the TCAD simulation result especially when the inverter’s response starts to fall. This is caused by the large parasitic capacitance at drain terminal contributed by Tm and Ta. In addition, the parasitic capacitance seen from the gate terminal of the GOS-impacted MOSFET in JET_03 model combines the gate capacitance of three MOSFETs and hence is also larger than a real GOS-impacted MOSFET.
Fig. 4-7. The GOS fitting results by using JET_03 model.
JET_03 model was claimed to be able to describe a minimum-size MOSFET in [4-21] since its source and drain is connected by only one MOSFET, Tm. However, when fitting the reduced ID(SAT), we have to increase the length of Tm, which turns Tm no longer a minimum-size MOSFET. Similar situation occurs when tuning the size of Tm, Ta, and Tb for fitting other DC curves. As a result, the size of all three MOSFETs is larger than the minimum size, which results in a further larger gate capacitance of the GOS-impacted MOSFET.
4.2.3 Nonlinear non-split model 2 - IDT_09
Figure 4-8 shows the nonlinear non-split GOS model IDT_09 proposed in [4-22], which uses only one MOSFET along with extra three current sources and is more suitable for representing a minimum-size GOS-impacted MOSFET.
Different from JET_03 model, the reduced saturation drain current caused by the GOS is modeled by the ”(1 − a)ID” current source. The negative drain current and the gate current caused by the GOS are modeled by the other two current sources iGD and iGS, respectively, where iGD and iGS are represented by a 3rd-order polynomial of VGD and VGS as shown in Equation 4-1 and Equation 4-2, respectively.
Fig. 4-8. The nonlinear non-split GOS model, IDT_09, proposed in [4-22].
iGD = a1·V3GD + b1·V2GD + c1·VGD + d1 (4-1) iGS = a2·V3GS + b2·V2GS + c2·VGS + d2 (4-2) Figure 4-9 shows the results of applying IDT_09 GOS model to the same experiment as in Figure 4-7. As Figure 4-9(a) shows, most of the IDVD curves
match the TCAD result quite well. However, when VG is low, the corresponding IDVD curve may deviate from the TCAD result at large VD, which will lead to a high drain current in SPICE simulation when the GOS-impact MOSFET is supposed to be turned off. Based on further analysis, this fitting error results from the limitation of using a polynomial to represent the current source iGD, even though the order of the polynomial is increased to more than 3.
Fig. 4-9. The GOS fitting results by using IDT_09 model.
As the transient-simulation result shown in Figure 4-9(b), using IDT_09 model can fit the TCAD result better than using JET_03 model. However, the response of the GOS-impacted inverter based on IDT_09 model is still significantly lower than the TCAD result when the input is low. Also, the falling slope of the inverter’s response based on IDT_09 model is slower than the TCAD result. This error results from the capacitance change induced by the GOS that has not been considered in the modeling. Note that this error in the transient simulation will be more significant if the GOS defect is on a pMOS or the size of the GOS is larger. The corresponding experimental results will also be shown in Section 4.3.3.