Type-C Subthreshold SRAM

The analysis of ADFs in Type-C subthreshold SRAM design [2-15] is more complicated than that in Type-A or Type-B designs since the Type-C design uses the combination of the values at WL1 and WL2 to determine the operation mode of a cell. Table 2-XIII shows the value of WL1 and WL2 at its hold, read, and write mode, respectively.

TABLE 2-XIII

Setting of WL1 and WL2 for Type-C design Operation WL1 WL2

Hold 1 0 Read 0 1 Write 1 1

A full analysis of ADFs in the Type-C design should include the impact of each ADF on each word-line (total 4 ADFs for 2 word-lines). For each ADF on each word-line, we need to enumerate the value at each word-line caused by the ADF based on different operation modes of the two faulty cells, which includes four effective combinations: C_m/C_n= (1) Read/Hold, (2) Write/Hold, (3) Hold/Read, and (4) Hold/Write. Note that we eliminate the cases of simultaneous Read and/or Write (i.e. Read/Read, Read/Write, Write/Read, and Write/Write) since the subthreshold SRAM is a single-port SRAM.

Table 2-XIV lists the complete analysis results of WL1 and WL2 values of the Type-C design [2-15] under the four C_m/C_n operations when each of the ADFs in Figure 2-9(b) occurs on WL1 and WL2 separately. According to the setting in Table 2-XIII, the values of WL1 and WL2 will lead to the corresponding behavior listed in the ”Behavior” columns of Table 2-XIV. If the corresponding behavior is different from the supposed one, we highlight the faulty behavior with a gray background in Table 2-XIV. Note that we view the combination WL1=WL2=0 as a Hold operation since this configuration also enables the Type-C design [2-15] to hold the data but just without the extra assistance of M_C3 and M_C9.

The faulty behaviors in Table 2-XIV are categorized into four groups (FB1-USR, FB2-UA, FB3-AR, and FB4-AW). In the paragraphs below, we will detail how each faulty behavior performs and give a short summary for testing ADFs in the Type-C design at the end.

1) FB1-USR (UnSafe Read) : The faulty behavior FB1-USR means that a cell is supposed to be read out, but its value may be attacked during the read operation. As shown in Table 2-XIII, only WL2 should be turned on during a read operation such that the turned off WL1 can protect the cross-coupled inverters from BL/BLB’s direct accessing (as illustrated in Figure 2-8). The cell with the faulty behavior FB1-USR would have both its word-lines turned on during a read operation, and thus the stored data (Q and QB) would be affected by the pre-charged BL/BLB just as the typical 6T SRAM would. In other words, the designed extra-read path in the Typc-C subthreshold SRAM is disabled and

TABLE 2-XIV

Faulty behavior of address decoder faults on Type-C designs (Fig. 2-8).

can no longer help the cell to avoid the potential read disturb. To detect the faulty behavior FB1-USR, we need to apply consecutive read operations to the same cells in the test sequence.

2) FB2-UA (UnAccessible) : The faulty behavior FB2-UA means that a cell is unaccessible by either a read or a write operation. This fault can already be detected by the conventional march sequence shown in Figure 2-9(a), and thus needs no further discussion.

3) FB3-AR (Attacked Read) : As shown as Table 2-XIV, the faulty behavior FB3-AR occurs when ADF II, III or IV occurs on WL2, where Cm and Cn should originally be hold and read, respectively. However, both word-lines of Cm in this case are turned on instead. If Cm and Cn locate at different columns, Cm will be attacked by the un-selected, pre-charged bit-lines just like the cell suffering FB1-USR, which can be detected by the consecutive read operations as discussed in “Section 1) FB1-USR”. On the other hand, if Cm and Cn locate at the same column, the read operation on Cn will be affected by the value stored in Cm as well since both word-lines of Cm are turned on. To trigger this fault, we need Cm and Cn to store the inverse data when Cn is read. The march sequence shown in Figure 2-9(a) satisfies this criterion. However, based on our simulation result, we found that the sensed output of this read fail with both BL and BLB pulled-down (one by Cm, and the other by Cn) is actually determined by the favored value of the sense amplifier in use. Thus, in order to cover different favored values of the sense amplifier, we should apply the march sequence shown in Figure 2-9(a) twice, one with x = 1 and the other with x = 0. In other words, the march elements ↓ r1, … , w0 , ↑ r0, … , w1 , ↓ r0, … , w1 , and

↑ r1, … , w0 should be included in the march algorithm.

4) FB4-AW (Attacked Write) : The faulty behavior FB4-AW is similar to FB3-AR, where Cm should originally be hold with WL1/WL2 = 1/0 but both its word-lines are unexpectedly turned on instead. The only difference is that a write operation (instead of a read operation) is applied to Cn for FB4-AW when both word-lines of Cm are unexpectedly turned on. If Cm and Cn are at the same column, our simulation result shows that the value stored in Cm will not be over-written by the value writing into Cn since the VirGND of Cm still remain low (unlike a normal write operation keeping VirGND high). Also, the value of Cm will not prevent the original write operation to Cn from successfully performed even when their values are different. Thus, FB4-AW is more difficult to detect than FB3-AR. Fortunately, as shown in Table 2-XIV, an ADF causing FB4-AW must cause FB3-AR as well, meaning that FB4-AW can also be detected as long as FB3-AR can be detected through the methods described in

“Section 3) FB3-AR”. Therefore, we only need to focus on detecting FB3-AR when designing the test algorithm.

5) Short Summary : To detect the ADFs occurring on WL1, we need to use consecutive read operations to cover FB1-USR as shown in “Section 1) FB1-USR”. As to the ADFs on WL2, Fault-I, Fault-II, and Fault-III all cause FB2-UA, such that conventional march sequence shown in Figure 2-9(a) can already detect them. In the case that Fault-IV occurs on WL2, we can apply consecutive read operations and the march sequence {↓ r1, … , w0 , ↑

r0, … , w1 , ↓ r0, … , w1 , ↑ r1, … , w0 } to detect FB3-AR.