Chapter 3 Experimental Process
3.2 Epitaxial film characterization tools
3.2.4 Scanning Electron Microscopy
Scanning Electron Microscopy (SEM) is a very convenient characterization technique.
When a fine electron beam with energy in the range of 10 – 30 keV is focused on a sample surface, low-energy secondary electrons are ejected from the sample by scattering between the incident electrons and the material. The secondary electrons are captured by a detector and processed to make an image of the sample. SEM has several benefits over both conventional optical microscopy and TEM. It is much better in resolution and magnification than those of the optical microscopy and much easier in sample preparation than TEM.
In this study, the SEM is mainly used to observe the cross-sectional view of the epitaxially grown layers. The cross-sectional SEM image gives fairly accurate thickness information for each layer and it can be used for growth rate calibration to make precisely controlled device Structures.
Chapter 4
Results and Discussion
4.1 GaAs/Si thin film characterization:
Heteroepitaxial growth of GaAs on Si has attracted much attention due to its potential application for devices of monolithic opto-electronic integrated circuit. However, the inherent difficulties such as 4.1% lattice mismatch, 60% thermal coefficient difference and antiphase domain formation will easily create a large number of threading dislocations that cause the quality of devices critically decrease. Therefore, an appropriate growth condition at very early stage are required for the epitaxy growth because the coalescence of GaAs nuclei on Si substrate is the source of threading dislocations at the early stage.
Si (001) substrate with a 6˚ offcut toward [110] was chosen to be sufficiently high angle so as to ensure diatomic steps. A homogeneous coverage is enhanced at the early stage of nucleation of crystalline GaAs because adatoms diffusing on surface preferentially adsorb
at the step edge sites and step-flow growth is promoted [52],[53]. Because the substrates are not “epi-ready” and long-time exposure to air, a chemical cleaning process in buffered oxide
etch solution (BOE) was used to eliminate the thick silicon oxide on the Si substrate. Just before the growth the oxide layer on the Si surface was stripped by a BOE solution for 30
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seconds, finally dried with dry nitrogen to obtain a hydrogen-terminated surface. The Si surface after cleaning was considered oxide-free, hydrophobic and terminated by H atoms.
This H-terminated Si surface is supposed stable during the transfer to reactor.
4.1.1 Effect of annealing ambient on GaAs film formation:
The wafer after dipping in a dilute HF solution to clean out the surface oxide was put into the reaction chamber and followed by an annealing process. Due to the possibility of oxidation and contamination during the transfer, an annealing step at high temperature is necessary not only for oxide removal, but also for the surface reconstruction [20]. The annealing procedure was carried out in two different sequences all at 6500C in 5 min, then subsequencely reduced to GaAs thin film growth temperature at 4000C with V/III ratio of 23.
The sequence A was done in H2 gas ambient only and the sequence B was in the flow of H2
including AsH3 flux. The AsH3 flux during the annealing period was chosen as 0 sccm, 10 sccm and 40 sccm. The influence of annealing time and temperature were not studied in detail, however, as keeping the wafer annealed longer time damage the substrate surface, that lead to an increasing roughness.
21Fig. 4-1 The two sequences for investigating the effect of substrate annealing ambient.
When the annealing treatment was done in a flow of H2 like in the sequence A, there were only large GaAs islands formed on the surface. The surface morphology on the wafer area between islands is similar to the surface of Si substrate after BOE cleaning, the same roughness mean square (RMS) value of 0.47 nm. The distance between islands were very large and there is no evidence for GaAs coverage of the substrate between these islands. This indicates that epitaxy has progressed mainly by growth of islands rather than nucleation of new islands. On the other hand, when the thermal treatment was done with introducing an AsH3 flow of 10 sccm, the GaAs still nucleated in form of small islands but reduced in size and higher density. When the As flux increased to 40 sccm, a GaAs continuous film has been achieved.
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22Fig. 4-2 SEM image on GaAs/Si top-view surface annealing in H2 ambient only.
The growth of epitaxial film involves the increased adatom migration. If the adatom migration is increased, then the adatoms can migrate over longer distances thereby enhancing the step growth mode. There was evidence that the Ga and As are mobile on the H-terminated Si surface [54]. Whereas, atomics H limit the surface diffusion length of adatoms by essentially increasing their incorporation rate into the growing layer [55].
Therefore, if a 3D growth started at the early stage, the presence of H atoms would further enhance the islands to grow bigger. For continuous film growth, an As-fully-passivated surface should be produced, rather than a partial H-terminated one. All of Si-H bonds should be replaced by Si-As bonds in the GaAs epitaxy growth on Si substrate.
23Fig. 4-3 AFM results of three GaAs/Si samples: a) annealed in H2, b) in H2/10 sccm AsH3 and c) in H2/40sccm AsH3 show the RMS value of 0.47 nm, 2.24 nm and 0.93 nm,
respectively.
It is obviously observed that an initially H-terminated surface effects the island formation in the early stage of GaAs epitaxy on Si. An As-terminated surface is much more desirable to form GaAs film. The interaction of arsenic with the hydrogen terminated surface should be considered. In the Si:H case, there are covalent bonds between the H atom and the dangling bond orbital on each surface Si atom. In the Si:As case, on the other hand, the As atom resides in the outer half of the double layer and the extra valence electronic compared to a silicon atom causes the dangling bond to be replaced with a fully occupied lone pair state [56]. Some papers have demonstrated that As must compete with H to bond to Si surface. As temperature increases, the onset of hydrogen desorption which frees up space for incoming AsH3 allowing the As coverage to increase further and a fully covered by As atoms surface. A fully-As-terminated surface could be obtained as annealing the Si H-terminated substrate under the flow of AsH3 at high temperature of 6500C [57], [58].
24Fig. 4-4 Angle-integrated photoemission spectra taken for a) a clean Si surface and for the same surface b) after hydrogen exposure plus 3000C annealing. This hydrogen covered surface was exposed to arsenic flux and annealed at c) 3500C, d) 5000C and e) 6500C. The
arrows corresponding to the As lone pair state [56].
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According to the fact that As does not stick well to Si surface at low temperature and it must compete with H atoms on the surface, an exposure to high temperature is necessary.
The substrate was annealed at 6500C for 5 min in a constant 28000 sccm flow of hydrogen, simultaneously exposed to 10 sccm AsH3 flow seem not equivalent for fully As-terminated.
The subsequent growth of GaAs forms various small islands instead of a continuous film. In our experiment, to obtain a As-terminated surface required an arsenic flow at higher than 40 sccm in this annealing condition.
25 Fig. 4-5 TEM image of GaAs/Si interface with thermal treatment in a) 10 sccm AsH3 and b)
40 sccm AsH3 respectively.
The As-fully-coverage Si surface is surely desirable as a requirement for GaAs thin film formation. Annealing in H2 and AsH3 ambient at high temperature can also protect the surface from contamination that were desorbed from the inner wall and susceptor of reactors.
M.Deura showed that annealing under group V gases can protect the surface against some contamination elements such as carbon and oxygen [59]. A brief summary could be drawn
out that for fully terminating the Si (001) surface by As atoms, we need to expose the H-terminated surface to AsH3 flow at 40 sccm and during the high temperature annealing process at 6500C. After finding the surface treatment conditions for GaAs thin film formation, we investigate the other parameters during the materials growth to improve the epilayer quality.
4.1.2 Effect of growth temperature:
To investigate the effect of growth temperature, the V/III ratios were kept the same at 23 and the temperature was varied from 3800C to 4600C. At 3800C, the roughness was 1.15 nm and it received the lowest value of 0.93 nm at 4000C. As the growth temperature continuously increased, the roughness was increased to 3.09 nm at 4200C and 5.38 nm at 4600C.
26Fig. 4-6 AFM images of GaAs/Si with different growth temperature a) 380, b) 400, c) 420 and d) 4600C.
At low temperature, the rougher surface may account for the incorporation of carbon. It has been known that hole concentration increases as the growth temperature of GaAs decreases [60]. The carbon incorporation may distort the GaAs lattice and therefore,
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degrading the surface morphology. At high growth temperature, a rough surface is expected since Ga atoms have higher diffusion coefficient lead to too much mobility prior to As trapping, and tending form clusters [54].
27Fig. 4-7 Hole concentration changes with temperature in GaAs growth [60].
A more analysis by TEM may help to explain the trend of surface mophorlogy changing with growth temperature. The cross-section TEM observation of the interface between GaAs and Si have been carried out, in order to see the growth process at early stage.
The GaAs/Si grown at high temperature showed that there were a large density of stacking faults and APDs in the GaAs layer and domain boundaries were also observed. The growth mode here could be assumed for the coalescence of GaAs islands formed at high temperature in the initial stage of growth. As GaAs grows, the small islands grow and connect with each other, eventually forming continuous GaAs film. When such islands coalesce, immobile
defects formed in large numbers, which are difficult to remove by subsequent annealing treatment or growth of higher thickness layer. The formation of big islands at the initial state is not preferable due to a very high density of dislocations causing by islands aggregation.
28Fig. 4-8 TEM images of GaAs/Si (001) interface grown at 4600C under V/III 23.
29Fig. 4-9 Coalescence of large islands formed in the initial growth at high temperature.
When the growth temperature is lower, the vertical growth rate decreases and the lateral growth rate increases. As the TEM image in figure 4-10 shows, the growth mode of
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GaAs at 3800C is also the combination of islands but the islands with longer width and lower height. Under low temperature deposition, the lateral migration of the deposited atoms along the surface is enhanced. The low temperature grown GaAs layer contains lots of dislocations, especially at the interface between two islands. This high dislocation density contributed to a high roughness value. In the case of GaAs/Si sample grown at 4000C under V/III ratio of 23, a very long GaAs film is observed. The lateral growth rate is further increased for continuous film formation. Due to the lateral dimension is much longer compared to the vertical one, the growth mode could be assumed a quasi-2D growth. In which, the lattice-mismatch induced stress is partially relaxed in form of APDs, stacking faults and microtwins starting from the GaAs/Si interface up to the surface.
30Fig. 4-10 TEM images of GaAs/Si (001) interface grown at 3800C.
31Fig. 4-11 TEM images of GaAs/Si (001) interface grown at 4000C.
4.1.3 Effect of V/III ratio:
To investigate the effect of V/III ratio, GaAs was grown at 4000C and tuning the V/III ratio through changing the AsH3 flow. The samples grown at lower or higher V/III of 18.4 inherit higher roughness morphology. At low V/III ratios of 11.5 and 16, the rms value are 1.67 nm and 0.75 nm, respectively. At high V/III ratios of 23 and 34, the rms value are 0.93 nm and 1.74 nm. The best sample with V/III ratio of 18.4 receives rms value of 0.66 nm.
32Fig. 4-12 Surface morphology of GaAs/Si sample grown at 4000C with low V/III ratio a)11.5, b) 16 and c) 18.4.
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33Fig. 4-13 Hole concentration at 300K as a function of [AsH3] with [TMGa] as parameter [61].
At low V/III of 11.5 (low As flux), the possibility of Ga atoms being incorporated into GaAs epitaxy exceeds that of As atoms, leading to poor surface morphology and APD formation [61]. The hole concentration was almost inversely proportional to [AsH3] and increased drastically when [V/III] was decreased. Moreover, the lattice contraction is attributed to the incorporation of substitutional carbon during the growth of III-V materials, as speculated by the authors with the change of GaAs Bragg angle [62]. The incorporation of carbon as contamination deteriorates the surface morphology.
34Fig. 4-14 Surface morphology of GaAs/Si sample grown at 4000C with high V/III ratio c) 18.4, b) 23 and c) 34.
For V/III ratio higher than 18.4, the surface morphology becomes rougher because of different growth rate at difference growth orientation. The lateral growth rate of GaAs in [110] direction is faster than in the [-110] direction for higher V/III ratios [63]. The lateral growth rate of the steps is seen to be related to the number of bonds binding a Ga atom to the growing step. At high As partial pressures and relatively low temperatures, the growing surface, including the steps, is thought to be saturated with As species. As seen in Figure 4-16, the [-110] step has a dangling As atom, making only a single bond to an adjacent Ga atom. As a result, a Ga adatom on the [110] step is able to make three bonds, while on the [110] step only two bonds are formed, the same as for a Ga adatom on an (001) terrace. Thus, the growth rate under As-rich conditions at low temperatures will be higher for the [110].
The different growth rate in different direction contributed to worsen the surface morphology of epilayer.
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35Fig. 4-15 Surface morphology of GaAs/Si grown at 4000C with V/III 23.
36Fig. 4-16 Schematic cross-sections of (a) [-110] and (b) [110] steps [63].
37Fig. 4-17 Lateral growth rate of GaAs by MOCVD as a function of AsH3 pressure during growth [63].
Figures 4-18, 4-19 and 4-20 are the high resolution TEM images of GaAs/Si interface grown at different V/III ratios of 11.5, 18.4 and 23, respectively. The formation of GaAs islands at low V/III ratio of 11.5 could be explained by high mobility of Ga atoms under low As flux and Ga atoms tend to form clusters prior to As trapping. When As flux increases, additional As terminates the mobility of the Ga atoms. The formation of dominant 900 misfit dislocations, fewer APDs and stacking faults in the optimized growth conditions at 4000C and V/III of 18.4 contributed to a better surface roughness. It is obviously clear that V/III ratio plays a role in the mismatch relaxation process.
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38Fig. 4-18 TEM image of GaAs/Si interface grown at V/III=11.5.
39Fig. 4-19 TEM image of GaAs/Si interface grown at V/III=18.4.
40Fig. 4-20 TEM image of GaAs/Si interface grown at V/III=23.
41Fig. 4-21 900 misfit dislocations at the GaAs/Si interface for optimum growth condition (V/III=18.4 and growth temperature 4000C).
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4.2 Integration of Ge on GaAs/Si artificial substrate by
UHVCVD:
Ge has the highest bulk hole mobility amongst all conventional semiconductors, and is a relatively mature in terms of integration with silicon technology. Therefore, silicon p-channel transistors can be replaced by germanium to complement strained n-channel Si transistors for enhanced hole transport [64]. Ge has the close lattice constant to GaAs, thus the Ge/GaAs/Si integration is expected to be grown at low threading dislocation. The narrower band gap of Ge (Eg=0.66 eV) lies within a wider band gap of GaAs (1.42 eV), resulting in a good confinement of carriers in the Ge layer [65].
The best GaAs/Si sample with RMS value of 0.66 nm was used for Ge integration. The UHVCVD system grows the Ge layer on artificial substrate at 4000C in 45 min. The Ge layer can achieve a thickness of 80 nm, growth rate is 1.8 nm per min. Fig. 4-22 shows the TEM image of the Ge/GaAs/Si interface. There are high density of microtwins and stacking fault presented in the Ge layer, starts from the Ge/GaAs interface and are located on {111} plane.
The RMS roughness of the Ge substrate is 5.7 nm in AFM analysis. From the XRD result we just can find only Ge peak, the GaAs layer is too thin and may be diffused out during Ge deposition.
42Fig. 4-22 TEM image of Ge layer grown on GaAs/Si artificial substrate by UHVCVD.
43Fig. 4-23 XRD result of Ge layer grown on GaAs/Si substrate.
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Chapter 5
Conclusion and Future Work
5.1 Conclusion:
A GaAs thin film so-called a nucleation layer has been successfully integrated on Si (001) substrate. By tuning the growth conditions, a 11-nm GaAs nucleation layer has been grown on Si (001) with a growth rate of 1.8 nm per minute and has smooth surface roughness of 0.66 nm. The combination of careful surface treatment with BOE cleaning, annealing in AsH3 flow of 40 sccm, appropriate V/III ratio of 18.4 and growth temperature of 4000C could produce a thin GaAs film with dominant 900 misfit dislocation. The formation of mostly 900 misfit and less 600 one indicates that the GaAs layer inherits low threading dislocations. The preferable strain relaxation offered by 900 misfit formation contributed to the low dislocation density inside the GaAs epilayer, therefore a smooth surface can be achieved. This GaAs/Si heterostructure with a very smooth surface morphology is a potential substrate for many other III-V materials like InAs, InGaAs, InSb or Ge to integrate on. The GaAs/Si combination can help to form a bridge for epitaxy engineering in large lattice mismatch system.
5.2 Future work:
The effect of nucleation layer thickness for Ge integration has not been investigated yet. The Ge integration conditions also need to be optimized, especially surface morphology for further devices processing. In the future, due to the Ge surface roughness is still a problem, we think that integrate Ge Fin on GaAs/Si substrate using the non-coalesced aspect-ratio-trapping hetero epitaxy involves the heterogeneous epitaxial growth inside trenches trapping the threading dislocations that originate at the heterostructure interface and propagate into the epitaxy region along the <111> directions [66]. The GaAs/Si smooth surface could be an perfect substrate for this application, the threading dislocation is expected to be lower than direct Ge on Si account for the close lattice constant of Ge and GaAs. Furthermore, the thin GaAs layer which has higher band gap also can serve as a good barrier layer to confine carrier in the Ge active layer, then the device performance should be better.
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