Circuit Design of Proposed Methods

In this part, the circuit designs of the algorithms presented in previous section are proposed. Our purpose is to show that the UW-based synchronization and channel estimation algorithms are not only able to provide better performance but also have low complexity and are suitable for hardware designing. Besides, The design principles still follow the rules mentioned in section 4.3.1.

(1) UW-based Synchronizer

The design of the UW-based synchronizer is quite simple. As shown in Figure 5.5, the synchronizer block called UW_sync is roughly divided into three parts. The first part is a shift register, 80_DFF, is used to store the latest 80 symbols input and its components can be implied by the name – 80 DFFs.

The newest 16 symbols and the oldest 16 symbols, which are stored in DFF 65 through 80 and DFF 1 through 16 as indicated in Figure 5.5, perform the conjugate multiplications and summation. Once the result of the summation is large than certain threshold value, that is, two consecutive UWs are matched, it can be inferred that these two UWs are currently stored in DFF 1through 16 and DFF 65 through 80. Thus, one frame of symbols - symbols in DFF 1 through DFF 64 then pass the FFT_switch and be sent to next stage.

Figure 5.5: Circuit design of the UW-based synchronizer

(2) UW-based Channel Estimator

From Eq.(5.12) through (5.14) we can see that the proposed algorithm gives a conspicuous structure of parallelism, since Eq.(5.13) and (5.14) are in identical operation format. Besides, coupled with the preamble structure inside one packet, the initial channel estimate l(0)H is automatically available, and the initial values of r(0) and P(0) in Eq.(5.15) and (5.16) can be derived. Therefore, we can see our design in Figure 5.6 that two sets identical entities are implemented, except that the upper one is for calculating P(i) and the lower one is for r(i). Since K=64 in our system, two buffers reg_p and reg_r with depth 64 are used to store the value of P(i) and r(i), and every time the received Y(i) is inputted to this block, values of P(i) and r(i) will be updated according to Eq.(5.13) and (5.14), and then written back to corresponding buffers.

pin

Figure 5.6: Circuit design of the UW-based channel estimator

5.5 Summary

In this section, we presented two applications of UW other than phase tracking mentioned in Chapter 2 and 4. We show that the structure of UW is not only useful in stationary system, but also useful in the tasks such as synchronization and channel estimation in a mobile environment. The synchronization algorithm employs UW as a selected training sequence while the channel estimation algorithm utilizes the constant nature of the UW extension in UW-based SC systems to obtain a moving average of the received signal over a finite period of time, which achieve a better performance than traditional preamble-only channel estimation. We also show that the two algorithms are not only theoretically uncomplicated, but also practically simple and therefore appropriate for hardware implementation.

Chapter 6

Conclusion

In future wireless communication systems, the demand of higher throughput and higher link quality is urgently called for, since various multimedia or home applications will be provided and thus reliable and affordable technologies are required to realize those contents. SC modulation, coupled with linear frequency domain equalization at the receiver, has less sensitivity to transmitter nonlinearities and phase noise than OFDM, and its complexity and performance are similar to those of OFDM in wireless communication. Single carrier with frequency domain equalization has been adopted by IEEE 802.16 standard to be one of the three modes as an alternative technique of OFDM in physical layer, and it is also currently a working assumption for uplink multiple access scheme in 3GPP Long Term Evolution, or Evolved UTRA. This reveals the potential of the SC-FDE technique and therefore encourages us to build up a hardware system based on SC-FDE system instead of the theoretical analysis only.

This thesis had described the signal processing concepts and algorithms of a SC-FDE system based on the UW structure in physical layer, and a self-designed platform equipped with four FPGA modules, USB interface, and RF modules is adopted to implement our system. A real wireless communication environment containing RF mismatch, multipath effects and so on are thus generated through real indoor experimental environment and RF modules on the self-designed platform. In our thesis we especially focus on the structure of the Unique-Word, and show that it is applicable to SC-FDE system in tasks such as phase tracking, synchronization and

channel estimation. What is more, corresponding circuit designs and analyses of the proposed UW-algorithms are presented; we show that those proposed UW-based algorithms are not only theoretically suitable for the SC-FDE system but also practically applicable in hardware implementation.

To summarize, hardware implementation is highly complicated. Therefore, the avalailability of MATLAB simulation, proper quantization algorithms, useful HDL simulation software, and powerful debugging tools becomes especially significant.

Nevertheless, some future works still remain. For example, higher modulation order such as 16QAM, 64 QAM and so on can be realized; in addition, the UW-based synchronizer and channel estimator circuit structures provided in Chapter 5 can be implemented and coupled with our system to further raise the performance. Finally, although there is a lot of room for improvement, we believe that the SC-FDE system implemented on the FPGA-based platform we proposed is still highly advanced nowadays.

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