Chapter 2 SC-FDE Baseband Transceiver Architecture
2.4 Summary
In this chapter, we introduce the SC-FDE system, and propose our system architecture including the transmitter and receiver. At the transmitter, convolutional encoder, mapper, UW generator, preamble channel generator, the polyphase filter design of upsampler and root-raised cosine filter are gone through. At the receiver, timing synchronization is first mentioned, which consists of packet detection, match filtering and symbol timing recovery. Frequency synchronization and channel estimation then follow, and phase estimation is proposed. Finally, de-mapper, and Viterbi decoder are described in the rest part of the receiver. In this chapter we highlight the two algorithms proposed: the modified delay-locked-loop algorithm for timing recovery and the UW-based phase tracking algorithm implemented on the system as an independent section to give a detailed introduction. More experimental results and performance analysis will be given in Chapter 4.
Chapter 3
SC-FDE System Platforms
In Chapter 3, we will introduce our self-designed platform as the development environment. The platform is used to perform the verification of whole SC-FDE system including baseband and RF parts, where transmitter and receiver are implemented on two separated boards with their own RF modules each. The self-designed platform is closer to a real wireless communication system and therefore can take all phenomena and effects of the wireless system into account. In the following sections, hardware modules, hardware description language, software design flows, and the corresponding debugging tools of our platforms are detailed explained.
3.1 Self-designed Platform
In order to approach a real wireless communication system, the multi- synchronous and high-speed bus FPGA design, combined with our module-based RF, AD/DA, and MAC/BB hardware system, becomes the best solution. Our laboratory has finished and successfully tested RF, AD/DA and MAC/BB boards. The development environment is shown in Figure 3.1, and the close-up shot of main board is shown in Figure 3.2, where four Xilinx Virtex II 6000 FPGAs are mounted in MAC/BB board, and each MAC/BB board is able to connect with at most two AD/DA and two RF modules.
In order to avoid the interference between high speed digital bus, those layouts and interconnections of different modules shall be handled very carefully. Our measurements show that directly connected modules did achieve feasible solution which reduces the risk of facing interconnection problems. Further analysis and evaluation during development are given in the following sections.
Figure 3.1: Development environment of self-designed platform
Figure 3.2: Main board of self-designed platform
3.1.1 RF Module
The RF module, as shown in Figure 3.3 consists of MAX2828, which is specifically designed for single-band IEEE 802.11a applications covering world-band frequencies of 4.9 GHz to 5.875 GHz. MAX2828 includes all circuitry required to implement the RF transceiver function, providing a fully integrated receive path, transmit path, voltage-controlled oscillator (VCO), frequency synthesizer, and baseband control interface. Only the RF switches, RF bandpass filters (BPF), RF baluns, and a small number of passive components are required to form the complete RF front-end solution. Because the balance of I/Q signals will impact on the waveform of RF output, the RLC components had been fine tuned. Besides, we also tested the frequency accuracy and power level of transmitted carriers in our interested band from 5.15 GHz to 5.875 GHz. One of those measurements is shown in Figure 3.4; the power level shall be further improved with fine tuning of matching circuits.
We used 3-wires (Clock, Data and Latch) to control the RF module from PC currently, and then the control mechanism will be integrated into MAC/BB after verification. In sum, MAX2828 completely eliminates the need for external SAW filters by implementing on-chip monolithic filters for both the receiver and transmitter. The baseband filtering and the Rx/Tx signal paths are optimized to meet the IEEE 802.11a and 802.11g standards. It is also suitable for the full range of the corresponding 802.11a/g OFDM data rates (6Mbps, 9Mbps, 12Mbps, 18Mbps, 24Mbps, 36Mbps, 48Mbps, and 54Mbps) and 802.11g QPSK data rates (1Mbps, 2Mbps, 5.5Mbps, and 11Mbps), at the required sensitivity levels.
Figure 3.3: RF module on self-designed platform
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Figure 3.4: Measured carrier spectrum form RF module
3.1.2 AD and DA Modules
The AD/DA module, as shown in Figure 3.5, consists of ADS2807 and DAC2900. The ADS2807 is a dual, high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital Converter (ADC). This converter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The measured timing diagram is shown in Figure 3.6, which indicates the valid data during the high clock period. In addition, it is recommended that data hold time is 3.5 ns for saving data from bus to Static random access memory (SRAM), which had been verified on our AD/DA boards too. The differential nature of this track-and-hold and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity. The track-and-hold can also be operated single-ended. Besides, it provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled allowing low-drive, external references to be used for improved tracking in multichannel systems.
The DAC2900 is a monolithic, 10-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW on a +5V single supply. Operating with high update rates of up to 125MSPS, the DAC2900 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for
"Direct IF" applications. The DAC2900 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight gain and offset matching. Each DAC has a high impedance differential current output, suitable for single-ended or differential analog output configurations. In addition, the DAC2900 combines high dynamic performance with a high throughput rate to create a cost effective solution for a wide variety of waveform synthesis applications.
Figure 3.5: AD/DA module on self-designed platform
Clock
Valid Data Clock
Valid Data
Figure 3.6: Measured data waveform from AD/DA module
3.1.3 MAC/BB Platform
The MAC/BB is an FPGA-based module which is composed of four Xilinx Virtex-II 6000 modules, as shown in Figure 3.7. Recently, the demand for more complex programmable hardware is constantly growing to meet the formidable
industry requirement. The major categories of programmable hardware are programmable logic device (PLD) and FPGA. A PLD consists of micro-cells and a central inter-connection logic. Typical PLD applications are “glue logic” for connecting other ASICs. On the other hand, FPGAs consist of even more complex logic block on one chip. Typical applications are central control units (CPU) and DSPs up to very complex SoC design. Therefore, we adopt some FPGA modules to realize our communication system. Generally, FPGA can be categorized into three types by its structure:
1. Look-up-table (LUT): Xilinx, Altera, AT&T 2. Multiplexer: Actel, Quicklogic
3. Transistor array: Cross point
If we focus on its programming architecture, there are two major types:
1. SRAM: Xilinx, Altera, AT&T, Atmel 2. Anti-fuse: Actel, Cypress, Quicklogic
SRAM type has a merit of being able to program repeatedly while Anti-fuse type has the feature of one time programmable (OTP). Anti-fuse type can offer security for design but cannot be modified further.
Compared to ASIC, FPGA has lower performance apparently, especially on power consumption and maximum supportable speed. However, as the technique of semiconductor industry grows, FPGA becomes more and more competitive to ASIC.
Actually, FPGA has more integration ability and flexibility than ASIC, and undoubtedly, is the best candidate component for a fast-prototyping system. On the other hand, more and more DSP systems are implemented using FPGA rather than DSP processors, since when sample rates grow above a few Mhz, a DSP has to work very hard to transfer the data without any loss. An FPGA on the other hand dedicates logic for receiving the data, so can maintain high rates of I/O, Therefore, a high speed environment especially combined with rigid, repetitive tasks suits the FPGA. It outperforms conventional DSP processors on a board-for-board comparison, resulting in significant improvements in processing speed, size, weight, power, and costs.
On our MAC/BB platform, an FPGA-based module which is composed of four Xilinx Virtex-II 6000 modules, where each of them combines a wide variety of flexible features and a large range of densities up to 6 million system gates, enhancing programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. With its advantages of very fast data rate, it can achieve full duplex and real time operating for wireless communication. The VHDL codes had been used to drive LEDs by differential clock rate from oscillator to verify its functionality.
Figure 3.7: MAC/BB platform
3.1.4 USB Interface
In order to have a convenient input for the audio/video signal in the future, USB interface was designed into the platform, which is shown in Figure 3.8. It will comply with the USB specification revision 1.1, and be upgraded to USB 2.0 if necessary. The compatibility test is conducted with compliance software run at PC equipped with PCI to UTMI compliant interface card during test stage. This will make sure we can easily connect our platform with any signal source with USB port. The built-in USB interface codes for FPGA was defined and implemented.
Figure 3.8: USB module on self-designed platform
3.2 Benefits of using VHDL
In our thesis we use VHDL (Very High Speed Integrated Circuit Hardware Description Language) as our hardware description language, since it has the following advantages:
(1) Executable specification
It is often reported that a large number of DSP designs meet their specifications first time, but fail to work when plugged into a system.
VHDL allows this issue to be addressed in two ways: A VHDL specification can be executed in order to achieve a high level of confidence in its correctness before commencing design, and may simulate one to two orders of magnitude faster than a gate level description.
A VHDL specification for a part can form the basis for a simulation model to verify the operation of the part in the wider system context (e.g.
printed circuit board simulation). This depends on how accurately the specification handles aspects such as timing and initialization. Behavioral simulation can reduce design time by allowing design problems to be
it also permits design optimization by exploring alternative architectures, resulting in better designs.
(2) Portability between tools
VHDL descriptions of hardware design and test benches are portable between design tools, and portable between design centers and project partners. One can safely invest in VHDL modeling effort and training, knowing that he will not be tied in to a single tool vendor, but will be free to preserve the investment across tools and platforms. Also, the design automation tool vendors are themselves making a large investment in VHDL, ensuring a continuing supply of state-of-the-art VHDL tools.
(3) Technology independent design
VHDL permits technology independent design through support for top down design and logic synthesis. To move a design to a new technology one need not start from scratch or reverse-engineer a specification - instead one can go back up the design tree to a behavioral VHDL description, then implement that in the new technology knowing that the correct functionality will be preserved.
3.3 FPGA Design Flow
In our design, we choose Xilinx ISE 6.3 and Synplify Pro 8.2 as the development tool for the first half of the design flow. Figure 3.9 is the main system design flow with FPGA and later we will give more information about the flow.
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Figure 3.9: FPGA design flow
(1) Design Entry
In general, EDA tools are required to develop register transfer level (RTL) codes by appropriate methodologies. In Xilinx ISE 6.3, it supports three methods: HDL (hardware description language) Editor, Schematic Flow, and FSM (finite state machine) Editor. HDL Editor allows us to edit source files directly like VHDL [28]-[30] and Verilog [31]-[32], which are the most common HDLs in use today. Schematic Flow is another choice to create our source files by drawing the scheme with underlying HDL macros. FSM Editor allows us to edit by timing state diagram, which is suitable for realization controller, such as memory access controller.
(2) Synthesis
After completing editing RTL source files, we need to translate them into gate level called netlist files, which only contains information of logic gates and inter-connections. We choose to use Synplify Pro 8.2 for synthesis.
(3) Simulation
Design verification is an important aspect of each project design. Before implementing our circuit in the target device, it is a good idea to simulate and
verify the circuit. The most common verifications are functional simulation and timing simulation.
A. Functional Simulation
Functional simulation can be done after the schematic has been entered or a HDL file has been created and synthesized. Functional simulation gives information about the logic operation of the circuit, but it does not provide any information about timing delays.
B. Timing Simulation
The timing simulation will give us detailed information about the time it takes for a signal to pass from one gate to the other (gate delay) and gives information on the circuit’s worst-case conditions. The total delay of a complete circuit will depend on the number of gates the signal sees and on the way the gates have been placed in the FPGA. One of the most popular simulation tools is ModelSim, which is completely integrated into Xilinx ISE 6.3, and can perform functional simulation and timing simulation very well.
Thus, we choose ModelSim SE 6.1e as the simulation tool in our design flow.
(4) Implementation
The implementation is typically done after the design has been verified by functional simulation. The implementation tools will translate the netlist (schematic, HDL), place and route the design in the target device and generate a bitstream that can be downloaded into the device.
(5) Download to FPGA
After the process of implementation, we can download our design into hardware platform. To verify that signals are really working properly in circuit, we can use the logic analyzer (LA) to debug. Once the result does not match what we expect, we need to come back to modify our design and go through the whole design flow again. That is to say, iterative tests are required until we obtain the results we want.
3.4 Debugging Tools
As an old saying goes, “What is a workman without his tools.” In our self-designed platform, we do have some useful tools for debugging as follows.
1. Logic Analyzer:
We use Agilent 16702B LA to perform the major task of debugging.
There are two modules installed on it. One is 16522A Pattern Generator Module, and the other is 16711A Measurement Module. The former is mainly used for generating desired signals, such as the reset signal or some selection signals for model selection; the latter is used for probing signals in FPGA on the self-designed platform.
2. Oscilloscope:
It is usually used when transmitted signals are prepared by FPGA and sent to the DA module by specific cables. Therefore, we can verify the waveform shown in the oscilloscope. For our system we may expect to see the waveform containing preambles in the form of square wave in the head part and data symbols appended with UW follow behind those preambles.
3. Spectrum Analyzer:
Agilent PSA Series Spectrum Analyzer E4443A is chosen. It offers high-performance spectrum analysis up to 6.7 GHz and beyond with swept-tuned measurements with digital Resolution-BandWidths (RBW) filters. In our debugging flow, E4443A capture the transmitted 5.2GHz signals, down convert them to 70MHz intermediate frequency (IF), and then fed out to vector signal analyzer to perform advanced analysis. Its block diagram is shown in Figure 3.10.
4. Vector Signal Analyzer:
Instead of swept-tuned measurements, vector signal analyzer 89600S performs FFT measurements with digital FFT filters, which can measure all
signal characteristics (i.e. phase) and avoid very long sweeps times required for narrow RBW. Figure 3.11 shows the block diagram of vector signal analyzer, notice that it is PC-based and therefore machines only capture the RF signal accurately and feeds to PC, where final analysis are performed on PC.
Figure 3.10: Spectrum analyzer block diagram
Figure 3.11: Vector signal analyzer block diagram
3.5 Summary
In this chapter, we introduce our self-designed platform used to perform the final verification of whole SC-FDE system. The platform equipped with FPGA, USB, and AD/DA modules as well as the RF modules by which realistic wireless channel characteristics can be generated. In addition, hardware description language and software design flows as well as corresponding debugging tools are mentioned; in particular the logic analyzer and oscilloscope are used to measure baseband signals, and spectrum analyzer and vector signal analyzer are used to capture and analyze RF signals.
Chapter 4
SC-FDE System Realization
The SC-FDE system is implemented on the FPGA-based hardware introduced in Chapter 3. This chapter is the major part of this thesis, which is organized as follows.
In the first subsection, a complete design flow is proposed. Then the MATLAB verification is given, and algorithms proposed in Chapter 2 are demonstrated and the system performance of SC-FDE system is shown and compared with the OFDM system. In addition, the circuit design of the system on FPGA is detailed, and finally, the ModelSim simulation and experimental results will be presented, where the principles and concepts of circuit design on FPGA will specially be emphasized.
4.1 Design Flow
Digital Signal Processing (DSP) design has traditionally been divided into two types of activities — systems/algorithm development and hardware/software implementation. The majority of DSP system designers and algorithm developers use the MATLAB language for prototyping their DSP algorithm. Hardware designers take the specifications created by the DSP engineers and create a physical implementation of the DSP design by creating a register transfer level (RTL) model in a hardware description language (HDL) such as VHDL and Verilog. Our SC-FDE system can be regarded as a DSP system, and Figure 4.1 shows the design flow we adopt.
First, we have to program a floating-point MATLAB code in order to verify the algorithms mentioned in Chapter 2 as well as evaluate the system performance. Then, the floating-point MATLAB code is required to be manually converted into the
First, we have to program a floating-point MATLAB code in order to verify the algorithms mentioned in Chapter 2 as well as evaluate the system performance. Then, the floating-point MATLAB code is required to be manually converted into the