基於獨特碼架構之頻域等化單載波系統之FPGA實現

國

立 交 通 大 學

電信工程學系碩士班

碩士論文

基於獨特碼架構之頻域等化單載波系統

之

FPGA 實現

FPGA Realization of a Unique Word Based

Single Carrier System

with Frequency Domain Equalization

研 究 生：陳欣瑤 Student:

Hsin-Yao

Chen

指導教授：李大嵩 博士 Advisor:

Dr.

Ta-Sung

Lee

基於獨特碼架構之頻域等化單載波系統之

FPGA 實現

FPGA Realization of a Unique Word Based

Single Carrier System

with Frequency Domain Equalization

研 究 生：陳欣瑤 Student: Hsin-Yao Chen

指導教授：李大嵩 博士 Advisor:

Dr. Ta-Sung Lee

國立交通大學

電信工程學系碩士班

碩士論文

A Thesis

Submitted to Institute of Communication Engineering

College of Electrical Engineering and Computer Science

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of

Master of Science

in

Communication Engineering

June 2007

Hsinchu, Taiwan, Republic of China

基於獨特碼架構之頻域等化單載波系統

之 FPGA 實現

學生：陳欣瑤

指導教授：李大嵩 博士

國立交通大學電信工程學系碩士班

摘要

所面對之高峰值對均值功率比(PAPR)問題，因此在 IEEE 802.16 標準中， SC-FDE

成為了於OFDM 以外另一實體層技術的選擇。在本論文中，吾人將使用自行研發

之平台，實現一基於獨特碼(UW)架構之單載波系統，其中基頻演算法部分將實現

於平台之Xilinx Virtex-II FPGA 模組。在此系統中之演算法除包括通道估計器、

頻率修正器、迴旋碼解碼器等之外，吾人也實現了基於獨特碼架構下之相位追蹤 器，使得此一單載波系統之功能性更加完整。此外，吾人更進一步提出此一獨特

碼架構於相位追蹤以外之應用，包括於時脈偏移下用以修正FFT 窗之偏移，以及

於移動之環境下用以更新通道之估計等。最後，本篇論文中將說明獨特碼的架構 不但在理論上十分簡單，實際上也十分適合用於硬體平台的實現。

FPGA Realization of a Unique Word Based

Single Carrier System with

Frequency Domain Equalization

Student:

Hsin-Yao

Chen

Advisor:

Dr.

Ta-Sung

Lee

Department of Communication Engineering

National Chiao Tung University

Abstract

In recent years, Single Carrier System with Frequency Domain Equalization (SC-FDE) becomes a key technology in the development of new wireless communication systems. It has similar performance, efficiency as well as low signal processing complexity advantages as orthogonal frequency division multiplexing (OFDM), but does not suffer from the high peak to average power ratio (PAPR) problem as in OFDM system. Therefore, SC-FDE has been adopted by IEEE 802.16 standard as an alternative technique to OFDM in the physical layer. In this thesis, we propose a solution for building up a Unique-Word (UW) based SC-FDE system on a self-designed platform with Xilinx Virtex-II FPGA module mounted. In addition to channel estimator, frequency offset compensator and convolutional encoder, a UW-based phase offset tracker is realized to make the functionalities of the system more complete. Moreover, other applications of UW structure are presented, including FFT window synchronization and update of channel estimation in mobile environment, etc. Finally, we will show that the UW structure is not only theoretically simple, but also practically suitable for hardware implementation.

Acknowledgement

First, I am very grateful to my advisor, Dr. Ta-Sung Lee, for his enthusiastic guidance especially the training of oral presentation and being earnest in our works. I would also thanks to Jeff Tsai who gives me a lot of technical support on the circuit design of self-designed platform, and Yen-Yu Chen who is always patient with my consultation. Special thanks to Lih-Gong Wu, whose priceless comments and invaluable suggestions are indispensable to the completion of this thesis. Heartfelt thanks are also offered to all members in the Communication Signal Processing and System Design (CSPSD) Lab for their constant encouragement and help.

At last but not least, I would like to express my deepest gratitude to my family for their endless love and the support all the way from the very beginning of my postgraduate study, especially my mom for her tender encouragement, and my dad as a constant reminder of health.

Contents

Chinese Abstract

...

I

English Abstract

...

II

Acknowledgement

...

III

Contents

...

IV

List of Figures

...

VII

List of Tables

...

X

Acronym Glossary

...

XI

Abbreviation Glossary

...

XIV

Chapter 1 Introduction... 1

Chapter 2 SC-FDE Baseband Transceiver Architecture... 4

2.1 Overview of SC-FDE System... 4

2.2 Transmitter Architecture ... 6

2.2.1 Convolutional Encoder ...7

2.2.2 Mapper / De-mapper ...8

2.2.3 Unique Word Structure ...8

2.2.4 Preamble Channel and Frame Structure ...10

2.2.5 Upsampler and Root Raised Cosine Filter...11

2.3 Receiver Architecture... 14

2.3.3 Channel Estimator...22

2.3.4 Phase Estimator...23

2.3.5 Viterbi Decoder...25

2.4 Summary ... 27

Chapter 3 SC-FDE System Platforms ... 28

3.1 Self-designed Platform... 28 3.1.1 RF Module ...30 3.1.2 AD and DA Modules...32 3.1.3 MAC/BB Platform...33 3.1.4 USB Interface...35 3.2 Benefits of using VHDL ... 36

3.3 FPGA Design Flow ... 37

3.4 Debugging Tools ... 40

3.5 Summary ... 42

Chapter 4 SC-FDE System Realization... 43

4.1 Design Flow ... 43 4.2 MATLAB Verification ... 44 4.3 FPGA Realization ... 50 4.3.1 Design Principles ...51 4.3.2 Circuit Design ...53 4.4 ModelSim Simulation ... 69 4.5 Experimental Results ... 71 4.6 Summary ... 73

Chapter 5 Other Applications on Unique Word Structure in

SC-FDE System... 74

5.1.1 Comparison of CP and UW in Terms of Bandwidth Efficiency and BER

Behaviour...76

5.2 Application of the Unique Word Structure... 77

5.2.1 Synchronization ...77

5.2.2 Channel Estimation...79

5.3 Simulation Results ... 83

5.4 Circuit Design of Proposed Methods... 85

5.5 Summary ... 87

Chapter 6 Conclusion ... 88

List of Figures

Figure 2.1: Transmitter architecture of SC-FDE system...7

Figure 2.2: Convolutional encoder with code rate 1/3 and constraint length 5 ...7

Figure 2.3: QPSK, 16-QAM, and 64-QAM constellations...8

Figure 2.4: Transmitted block using the concept of UW ...9

Figure 2.5: Training sequence and frame structure of IEEE 802.11a standard ... 11

Figure 2.6: Diagram of upsampler and pulse shaping filter...12

Figure 2.7: Evolution of the polyphse filter ...13

Figure 2.8: Noble identity ...13

Figure 2.9: Receiver architecture of SC-FDE system...14

Figure 2.10: Double sliding window packet detection ...15

Figure 2.11: Block diagram of delay-locked loop...16

Figure 2.12: Detection set of delay-locked-loop...17

Figure 2.13: Oversampled waveform with the correct sample points ...19

Figure 2.14: Original and new detection set in proposed DLL algorithm ...19

Figure 2.15: Proposed DLL algorithm Flow...20

Figure 2.16: Constellation diagram of one equalized frame ...23

Figure 2.17: Trellis diagram part 1...26

Figure 2.18: Trellis diagram part 2...27

Figure 3.1: Development environment of self-designed platform ...29

Figure 3.2: Main board of self-designed platform ...29

Figure 3.3: RF module on self-designed platform ...31

Figure 3.4: Measured carrier spectrum form RF module...31

Figure 3.5: AD/DA module on self-designed platform...33

Figure 3.6: Measured data waveform from AD/DA module ...33

Figure 3.7: MAC/BB platform...35

Figure 3.8: USB module on self-designed platform ...36

Figure 3.9: FPGA design flow ...38

Figure 3.10: Spectrum analyzer block diagram ...41

Figure 3.11: Vector signal analyzer block diagram ...41

Figure 4.1: FPGA design flow ...44

Figure 4.2: Impulse and frequency response of RRC filter with β=0.25...45

Figure 4.3: (a) Original waveform (b) RRC shaped waveform on transmitter (c) RRC shaped waveform on receiver...46

Figure 4.4: Eye diagram of RRC shaped waveform ...46

Figure 4.5: (a) Received oversampling waveform (b) DLL selected samples on receiver (c) Original samples on transmitter...47

Figure 4.6: Real and estimated channel frequency response ...48

Figure 4.7: (a) One equalized block in the presence of residual CFO (b) One equalized block after the proposed phase tracking algorithm (c) One equalized block after the lower-complexity phase tracking algorithm...49

Figure 4.8: System performance of SC-FDE and OFDM...50

Figure 4.9: Circuit design of transmitter ...53

Figure 4.10: Circuit design of convolutional encoder...54

Figure 4.11: Circuit design of mapper ...55

Figure 4.12: Circuit design of de-mapper ...55

Figure 4.13: Circuit design of preamble generator ...56

Figure 4.14: Circuit design of Unique Word generator...57

Figure 4.15: Circuit design of multiplexer...58

Figure 4.16: Circuit design of polyphase filter ...59

Figure 4.17: Circuit design of receiver side ...59

Figure 4.18: Circuit design of double sliding window packet detection method...60

Figure 4.19: Circuit design of the delay-locked loop...61

Figure 4.20: Circuit design of the frequency offset compensation block ...62

Figure 4.21: Circuit design of fast Fourier transform ...63

Figure 4.22: Conventional channel estimation and equalization strategy...64

Figure 4.23: Modified channel estimation and equalization strategy ...64

Figure 4.24 Circuit design of channel equalizer ...65

Figure 4.25 Circuit design of phase offset compensator...66

Figure 4.26: Circuit design of Viterbi decoder...67

Figure 4.27: Circuit design of branch metric generator ...67

Figure 4.28: Circuit design of add, compare, and select block ...68

Figure 4.29: SC-FDE transmitter ModelSim simulation result ...69

Figure 4.30: SC-FDE receiver ModelSim simulation result...70

Figure 4.31: Transmitted waveform of SC-FDE system...70

Figure 4.32: Self-designed platform development environment...71

Figure 4.33: Self-designed platform experimental result: source data and detected data waveform on LA ...72

Figure 5.1: Single Carrier with (a) Cyclic Prefix and (b) Unique Word ...76

Figure 5.2: Synchronization and tracking of the FFT-window ...78

Figure 5.4: Comparison of the proposed preamble based channel estimation and

UW-update channel estimation ...84

Figure 5.5: Circuit design of the UW-based synchronizer...85 Figure 5.6: Circuit design of the UW-based channel estimator ...86

List of Tables

Table 2-1: Main PHY Parameters of the Investigated SC-FDE System ...6 Table 2-2: Proposed phase tracking algorithm ...24 Table 2-3: State transition table...26 Table 4-1: Relative Resource consumption of the SC-FDE system at the transmitter72 Table 4-2: Relative Resource consumption of the SC-FDE system at the receiver ....73 Table 4-3: Time consumption of Synthesis and P&R in SC-FDE system ...73 Table 5-1: Summary of simulated SC-FDE systems...84

Acronym Glossary

1G first generation

ADC analog to digital converter

AMPS advanced mobile phone services

ASIC application specific integrated circuit

AWGN additive white Gaussian noise

BER bit error rate

BMG branch metric generator

BPSK binary phase shift keying

BRAN broadband radio access network

CDMA code division multiple access

CIR channel impulse response

CP cyclic prefix

CPLD complex programmable logic device

CPU central processing unit

CSI channel side information

DAC digital to analog converter

D-AMPS digital AMPS

DFF delay flip-flop

DFT discrete Fourier transform

DLL delay-locked loop

DSP digital signal processor

EDA electronic desing automation

ETSI European Telecommunications Standards Institute

FDE frequency domain equalization

FEC forward error correction

FFT fast Fourier transform

FIR finite impulse response

FPGA field programmable gate array

FSM finite state machine

GSM global system for mobile communications

HDL hardware description language

HiperMAN high-performance MAN

I/O input/output

IBI inter-block interference

ICI inter-carrier interference

IEEE institute of electrical and electronics engineers

IF intermediate frequency

ISI inter-symbol interference

JTAG joint test action group

LA logic analyzer

LED light emitting diode

LSB least significant bit

LTE long term evolution

LUT look up table

MAC media access control

MAN metropolitan area network

MLSE maximum likelihood sequence estimation

NLOS non-line-of-sight

OBW occupied bandwidth

OFDM orthogonal frequency division multiplexing

OSC oscillator

OTP one time programmable

PAPR peak-to-average power ratio

PCI process control interface

PHY physical layer

PLL phase-locked loop

QAM quadrature amplitude modulation

QPSK quaternary phase shift keying

RAM random access memory

RF radio frequency

ROM read-only memory

RRC root raised cosine

RTL register transfer level

SC single carrier

SNR signal to noise ratio

SoC system on a chip

SOHO small office/home office

SRAM static random access memory

USB universal serial bus

UTMI USB 2.0 transceiver macrocell interface

UTRA universal telecommunication radio access

UW unique word

VCO voltage-controlled oscillator

VHDL very high speed integrated circuit hardware description language

VSA vector signal analyzer

WCDMA wideband CDMA

Abbreviation Glossary

BPF bandpass filter

Chapter 1

Introduction

Wireless communications is one of the most active areas of technology development of our time. Similar to the developments in wired line capacity in the 1990s, the demand for new wireless capacity is growing at a very rapid pace. From the first-generation (1G) radio systems developed in the 1970s and 1980s, transmitting voice over radio by analog communication techniques such as Advanced Mobile Phone Services (AMPS), to the 2G systems built in the 1980s and 1990s, featuring the adoption of digital technology such as Global System for Mobile Communications (GSM), Digital-AMPS (D-AMPS) and code division multiple access (CDMA), and further to today’s 3G wideband CDMA (WCDMA) technologies, whose transmission data rate can be up to 2 Mbps in good conditions. Driven by the transformation of a medium supporting voice telephony into a medium that is demanded to support other services such as the transmission of video, images, text, and data, future wireless system must provide high data rate services to satisfy the increasing needs of the next-generation wireless networks. Recent air interface standards for such wideband wireless metropolitan area network (MAN) systems are being developed by the IEEE 802.16 working group and also by the European Telecommunications Standards Institute (ETSI) Broadband Radio Access Network (BRAN) High-Performance MAN (HiperMAN) group. Such systems are installed to operate over non-line-of-sight (NLOS) links, serving residential and small office/home office (SOHO) subscribers with high data rate transmission.

However, as the bit rate increases, the problem of inter-symbol interference (ISI) becomes more serious. The above wireless access systems in residential neighborhoods must cope with the dominant propagation impairment of multipath which causes multiple echoes of the transmitted signal to be received with delay spreads of up to tens of microseconds. For bit rates in the range of tens of megabits per second, this translates to inter-symbol interference that can span up to 100 or more data symbols. For example, at a 5 MHz symbol rate, a 20 μs multipath delay profile spans 100 data symbols. This raises the question of what types of anti-multipath measures are necessary, and consistent with low-cost solutions.

Several variations of orthogonal frequency-division multiplexing (OFDM) have been proposed as effective anti-multipath techniques [1]-[4], primarily because of the favorable trade-off they offer between performance in severe multipath and signal processing complexity. However, it is shown that when combined with frequency domain equalization (FDE), the single-carrier (SC) approach delivers performance similar to OFDM, with essentially the same overall complexity [5]-[7]. In addition, SC modulation uses a single carrier, instead of the many typically used in OFDM, so the peak-to-average transmitted power ratio for SC-modulated signals is smaller [8]-[10]. This in turn means that the power amplifier of an SC transmitter requires a smaller linear range to support a given average power (in other words, requires less peak power backoff). As such, this enables the use of a cheaper power amplifier than a comparable OFDM system; and this is a benefit of some importance, since the power amplifier can be one of the more costly components in a consumer broadband wireless transceiver. Therefore, single carrier with frequency domain equalization (SC-FDE) has been adopted by IEEE 802.16 standard to be one of the three modes as an alternative technique of OFDM in physical layer, and it is also currently a working assumption for uplink multiple access scheme in 3GPP Long Term Evolution (LTE), or Evolved UTRA. These show its potential of being an important candidate for future mobile wireless systems.

Moreover, a novel approach considering phase tracking algorithms for SC-FDE systems, which make use of the concept of Unique Word (UW) blockwise extension instead of the classical concept of cyclic prefix (CP) like it is used in OFDM is

provided [11]-[13]. The UW is a very simple known sequence that are distributed along the frame, which in this paper is focused on its performance on phase tracking algorithms as a counterpart of the use of pilot tones for IEEE 802.11a like OFDM systems [14]. Besides, with the UW-based structure, the algorithm developer has a lot of freedom for the tasks of synchronization [15]-[17], channel estimation [18]-[19] or noise prediction [20], which we will discuss in Chapter 5.

The goal of this thesis is to realize a Single-Carrier system with Frequency-Domain Equalizer on field programmable gate array (FPGA)-based platforms, where we intend to verify the above-mentioned algorithms on a self-designed platform. The complete functional blocks in both the transmitter and receiver are provided, and the associated algorithms applied in each functional block are also presented. After giving an overview of system architecture, we propose a total solution to build up FPGA-based platforms for realizing the SC-FDE system, including MATLAB verification and FPGA realization. The developed system contains a baseband transmitter, a digital-analog converter, an analog-digital converter, and a baseband receiver.

The organization of this thesis is as follows. Chapter 2 describes the proposed SC-FDE transceiver architecture and its corresponding schemes. In Chapter 3, the development environments of the proposed self-designed platform are introduced. In Chapter 4, the overall system realization is presented, and the performance evaluation is also included. Later, a further discussion of the UW-based SC-FDE system will be provided in Chapter 5. Finally, we make our concluding remarks in Chapter 6.

Chapter 2

SC-FDE Baseband Transceiver

Architecture

This chapter focuses on the SC-FDE baseband transceiver architecture. An overview of the SC-FDE system will first be given. Then we divide the developed architecture into transmitter and receiver, and provide functional descriptions and associated algorithms for each block. In addition, the modified delay-locked-loop algorithm for timing recovery and the Unique Word based phase tracking algorithm adopted on the system will be described.

2.1

Overview of SC-FDE System

Recently, SC-FDE system has received a lot of attention as an attractive alternative solution for the problem of ISI in the wideband wireless system. Compared to the time-domain equalization that requires one or more transversal filters with the tap number covering the maximum channel impulse response length, FDE outperforms the conventional time-domain equalization and requires less complexity by using fast Fourier transform (FFT) and is more suitable for long channels. With such a comparably lower complexity similar to OFDM, SC-FDE does not suffer high peak-to-average power ratio (PAPR) as well as sensitivity to frequency and phase offsets as they are in the OFDM systems. Previous work [5][7] has also shown that FDE has better performance than OFDM systems in uncoded and high coding rate systems.

In our system we investigate a SC-FDE system, where the parameters are adapted to the IEEE 802.11a OFDM based wireless LAN (WLAN) standard. The transmission format at the physical layer (PHY) is frames consisting of a preamble part and the data payload. The preamble comprises ten short preambles and two long preambles, which are used for different synchronization tasks at the receiver. The data payload consists of six SC-FDE frames, each appended with a known sequence, called Unique Word, and six frames together are attached after the preamble. Moreover, the UW is cyclically extended in the guard time, resulting in the cyclic-prefix-like structure and equalization criterion can be easily achieved in the frequency domain. The detailed structure of preamble will be discussed in Section 2.2.4.

Parameters to be synchronized are the temporal position of the transmission frame, the carrier frequency, the clock frequency, and the temporal position of the FFT-window. Additionally, an estimate of the channel transfer function is needed. The effect of carrier phase offsets and clock phase offsets on the system performance is compensated for by channel equalization. After the preamble based carrier frequency synchronization there will always be some remaining carrier frequency offset, which causes phase errors in the received and equalized data symbols. In IEEE 802.11a systems, pilot subcarriers are used to estimate and track these phase errors. In this project we show, that simple UW-based phase tracking algorithms provide almost optimum performance in SC-FDE systems, and the main parameters of the investigated SC-FDE system are shown in Table 2.1.

We summarize the advantages of SC-FDE as follows:

¾ SC modulation has reduced peak-to-average ratio requirements from OFDM, thereby allowing the use of less costly power amplifiers

¾ Performance of SC-FDE system is similar to that of OFDM system, even for very long channel delay spread

¾ Frequency domain receiver processing has a similar complexity reduction advantage to that of OFDM: complexity is proportional to log of multipath spread

¾ Coding, while desirable, is not necessary for combating frequency selectivity, as it is in non-adaptive OFDM

¾ SC modulation is a well-proven technology in many existing wireless and wired-line applications, and its radio-frequency (RF) system linearity requirements are well known

Table 2-1: Main PHY Parameters of the Investigated SC-FDE System

RRC(α=0.25) Pulse Shaping 1/3 Coding Rates QPSK Modulation Schemes 16 Short Preamble Size (symbols)

64+16(CP) Long Preamble Size (symbols)

64 FFT Size

16 Number of Unique Word symbols/frame

48 Number of data symbols/frame

64 Number of total symbols/frame

6 Number of frames/packet RRC(α=0.25) Pulse Shaping 1/3 Coding Rates QPSK Modulation Schemes 16 Short Preamble Size (symbols)

64+16(CP) Long Preamble Size (symbols)

64 FFT Size

16 Number of Unique Word symbols/frame

48 Number of data symbols/frame

64 Number of total symbols/frame

6 Number of frames/packet

2.2 Transmitter Architecture

The baseband SC-FDE transmitter architecture is shown in Figure 2.1. The source data is first fed into the channel encoder, e.g., using the convolution code for error correction at the receiver. After coding, the binary values are converted into Quadrature Phase Shift Keying (QPSK) values with a mapper, and a guard period is added between successive frames. The insertion of a guard period anticipates the blockwise processing needed in the receiver when using FFT operations. The guard period will then be filled up with a known, simple UW sequence with the UW generator, and every six UW-appended frames will be preceded by the preamble with the preamble generator. The UW and preamble are used for certain synchronization purposes and the detail functionalities will be discussed in Section 2.2.3. After pulse shaping (Root Raised Cosine Pulses) and digital-to-analog conversion the resulting I/Q signals are up-converted onto the desired frequency band.

Encoder Mapper UW Generator Preamble Generator MUX Upsample & RRC DAC Data Channel

Figure 2.1: Transmitter architecture of SC-FDE system

2.2.1Convolutional Encoder

A convolutional encoder typically will generate two or three output bits for each input bit. The output bits are dependent on the current input bit, as well as the state of the encoder. The state of the encoder is represented by several bits which precede the current bit. Figure 2.2 shows a convolutional encoder adopted in our system with code rate equal to 1/3 and constraint length equal to 5. Convolutional coding adds redundant bits in such a way that the decoder can, within limits, detect errors and correct them.

+

+

+

+

+

+

2.2.2 Mapper / De-mapper

Quadrature amplitude modulation (QAM) is the most popular type of modulation scheme since the rectangular constellations are easy to implement as they can be split into independent in-phase and quadrature parts. A mapper is used to map a small group of bits into a symbol according to the rectangular constellation adopted. Figure 2.3 shows the rectangular constellations of QPSK, 16-QAM, and 64 QAM. The higher modulation order the mapper adopts, the more information a symbol can carry, yet higher modulation order always suffers from interference more severely. In our system, we adopt QPSK as our modulation scheme.

QPSK 16-QAM 64-QAM I Q 2 4 6 -6 -4 -2 2 4 6 -6 -4 -2 QPSK 16-QAM 64-QAM I Q 2 4 6 -6 -4 -2 2 4 6 -6 -4 -2

Figure 2.3: QPSK, 16-QAM, and 64-QAM constellations

2.2.3 Unique Word Structure

Frequency domain equalization for single carrier system is based on the equivalence between the convolution of two sequences in the time domain and the

received signals have to be processed blockwise. Therefore, performing a blockwise transmission and inserting a Cyclic Prefix (CP) between successive blocks is necessary, since the cyclic extension enables the circular convolution of the transmitted frame and the channel impulse response. The conventional CP structure, however, is less useful for other purpose like synchronization as long as the content of the CP is not known and varies with every single frame. The overhead induced by the CP could be used in a more efficient way if its content would be known before and could be chosen in a proper way. Therefore, instead of the cyclic prefix, a known sequence called Unique Word (UW) is part of every processed frame [11]-[13].

First of all, Figure 2.4 depicts the structure of one transmitted frame, which consists of the original data sequence of NS symbols and the guard interval with NG

symbols. The overall duration of one frame with N = NS+NG symbols is

( )

FFT S G

T = NT = N +N T (2.1)

where T is the symbol duration and let T_G =N T_G be the guard interval.

N_sT N_GT T_FFT N_sT N_GT T_FFT UW UW UWUW

Figure 2.4: Transmitted block using the concept of UW

A mathematical description of the investigated SC-FDE system using the UW instead of the traditional CP is now given. Let us denote s_{Data i,}( )t to be the

continuous-time representation of the data symbols part of the i-th transmitted frame with s_{Data i,}( ) 0t = for t∉

[

]

Define si(t) as the whole i-th frame. Therefore,

[

]

[

]

Including the UW from the previous frame, an extended frames t( )can be defined as

[

]

[

]

With this cyclically extended frame the linear convolution (∗) of the i-th frame with the channel impulse response becomes a circular convolution (⊗) and the received block r ti( ) fulfils the condition

_{( )} l_{( ) ( ) ( )}

i i i

r t =s t ∗h t =s t ⊗ (2.4) h

within the interval

[

]

response. When restricting the received frame to FFT window

[

]

For f₀=1T_FFT and n Z∈ . The capitalization represents the Fourier Transform of the corresponding lowercase parameters in Eq.(2.4). Therefore, the frequency domain relation in Eq.(2.5) shows that the concept of UW is comparable to the concept of CP.

In this thesis, we focus on the design and performance of Unique Word based phase tracking algorithms [14], and we will show that the algorithm provide almost optimum performance in SC-FDE systems in Section 4.2 .

2.2.4 Preamble Channel and Frame Structure

Referring IEEE 802.11a standard, we attach the training sequence, also called preamble, in front of every packet. At the receiver, preambles can be utilized to do a number of tasks, such as timing synchronization, frequency synchronization, and channel estimation. The format of preamble channel and frame structure is shown in Figure 2.5. Preambles can further be separated into short preamble and long preamble,

shorter length compared with long preamble. Each short preamble contains 16 symbols with time-span 0.8 μs, and ten short preambles have a total time-span of 8 μs. The following parts are two long preamble symbols, and each one is protected by a guard interval filled with its cyclic extension, which have a total time-span of 8 μs. After preamble channel, data symbols with cyclically UW extension follow.

Figure 2.5: Training sequence and frame structure of IEEE 802.11a standard

2.2.5 Upsampler and Root Raised Cosine Filter

Upsampling is an operation that is often done before the pulse shaping filter to make the filter design simpler. If we do not increase the sample rate, we will need to design a very sharp filter which is not only very difficult and expensive to implement, but may sacrifice some of the spectrum in its roll off. Besides, a filter with a smooth roll off will have nicer phase characteristics as well.

Root raised cosines (RRC) filter is a commonly used pulse shaping filter in digital communication systems to limit ISI. The frequency response of an ideal root raised cosine filter consists of unity gain at low frequencies, the square root of raised cosine function in the middle, and total attenuation at high frequencies. The width of the middle frequencies is defined by the roll off factor constant β (0<β<1). Root raised cosine filter is generally used in series pairs, so that the total filtering effect is that of a raised cosine filter. The advantage is that if the transmit side filter is stimulated by an impulse, then the receive side filter is forced to filter an input pulse shape that is identical to its own impulse response, thereby setting up a matched filter and maximizing signal to noise ratio (SNR) while at the same time minimizing ISI. Mathematically, the frequency response F_rrc( )ω may be written as

1 For (1 ) 0 For (1 ) ( ) ( (1 )) 1 cos 2 For (1 ) (1 ) 2 c c rrc c c c c F ω ω β ω ω β ω π ω ω β βω ω β ω ω β ⎧ ≤ − ⎪⎪ ⎪⎪ _{≥ +} ⎪⎪ ⎪⎪ = ⎨_{⎪ ⎛ − − ⎞} ⎟ ⎜ ⎪ _{+ ⎜ ⎟} ⎪ _⎜⎜ ⎟_⎟ ⎪ _{⎝ ⎠} ⎪ _{− < < +} ⎪⎪ ⎪⎩ (2.6)

where ω is half the data rate. _c

The operation of upsampling and RRC filtering is shown in Figure 2.6, where

H(z) is the frequency response of the pulse shaping filter and L is the upsampling rate.

↑L H(z)

x[n] ↑L H(z) y[m]

x[n] y[m]

Figure 2.6: Diagram of upsampler and pulse shaping filter

Note that this procedure is computationally inefficient because the filter operates on a sequence that is mostly composed of zeros. To avoid operations on zero-valued samples, rearrangement of the preceding block diagram is required. First of all, transform H(z) into its upsampled polyphase components, where h[n] is the time domain counterpart of H(z):

(

)

(

)

(

)

(

)

∑

∑ ∑

∑ ∑

∑

Therefore, Figure 2.6 can be redrawn as Figure 2.7(a). By the Noble identity for interpolation which is shown in Figure 2.8, Figure 2.7(a) can further evolve into Figure 2.7(b) and (c). Filters hp[n] in Figure 2.7(c) is called polyphase filters. Let the

symbol rate before upsampling be 1/T and the length of h[n] be N. Without polyphase

simplification the computational cost is LN T (computations/sec), while that with polyphase structure is N T(computations/sec). Thus we save a factor of L.

x[n]

y[m]

…

x[n]

y[m]

…

x[n]

y[m]

…

…

…

x[n]

y[m]

…

…

…

(a)

(b)

(c)

Figure 2.7: Evolution of the polyphse filter

↑L H(zL₎

x[n]

y[m]

x[n]

y[m]

x[n]

y[m]

x[n]

y[m]

x[n]

x[n]

y[m]

y[m]

2.3

Receiver Architecture

The baseband function diagram of the proposed SC-FDE receiver is shown in Figure 2.9. The received signal is first down-converted to the baseband. After passing through the timing synchronization processing blocks, short preambles are separated as a means for frequency synchronization. The payload part is then processed blockwise. Each frame is transferred to frequency domain by the FFT block and equalized in the frequency domain. To acquire the channel information, long preamble is used to do frequency domain channel estimation. After being transformed back to the time domain, the phase shift of the equalized data is corrected by the known UW structure inserted in data channel to further improve the performance. The detected symbol streams are then recovered by a Viterbi decoder.

Frequency Synchronization Frequency Offset Estimation FFT Channel Estimation IFFT Carrier Phase Offset Compensation Carrier Phase Offset Estimation Timing Synchronization

Frequency Synchronization Channel Equalization

Phase Tracking Preamble Unique Word Sampling Rate Reduction Match Filter Packet Detection Frequency Domain Equalization

Slicer Demapper Viterbi Decoder

Output Data

2.3.1 Timing Synchronization

2.3.1.1 Packet Detection

Packet detection is the task of finding an approximate estimate of the start of the preamble of an incoming packet. It is the first data-processing block of IEEE 802.11a baseband receiver. As such it is the first synchronization algorithm that is performed, so the rest of the synchronization process is dependent on good packet detection performance. On the other hand, power consumption can also be taken into consideration since the packet detection mechanism determines when the block behind should start to function. The double sliding window packet detection method is used in the thesis. It computes the signal energy over two sliding windows, A and B, as shown in Figure 2.10. When the packet starts to enter window A, the energy in A gets higher and higher. The basic principle is to form the decision variable mn a ratio

of total energy contained inside the two windows. The packet detection is declared when the value of mn crosses over the threshold value.

A B m_n Threshold A B m_n Threshold Packet Packet

Figure 2.10: Double sliding window packet detection

The algorithm is described as 2 1 1 * 0 0 2 * 1 1

where is length of window A where is length of window B

− − − − − = = + + + = = = = = = =

∑

∑

∑

∑

In addition to packet detection, finer timing synchronization in a SC-FDE system is required to decide where to place the start of the FFT window within one frame. Although an SC-FDE system exhibits a guard interval, making it somewhat robust against timing offsets, non-optimal symbol timing will cause more inter-symbol interference and inter-carrier interference (ICI) in delay spread environments. This will result in performance degradation. To eliminate timing offset induced by different path delays, fine timing synchronization will be performed after coarse timing synchronization.

2.3.1.2 Match Filter and Symbol Timing Recovery

After packet detection the received signal is fed through a matched filter and re-sampled at the symbol rate. The matched filter is simply an FIR filter with an impulse response matched to the transmitted pulse. It aids in timing recovery and helps suppress the effects of noise. The goal of symbol-timing recovery is to sample message signals at the receiver for best performance. Since upsampling is done at the transmitter, oversampling is performed at the analog-to-digital converter (ADC) as well to make the design of the filters simpler. Therefore, the received symbol rate should be reduced before the signal is sent to the digital processing blocks afterwards. Although the symbol rate is typically known to the receiver, the receiver does not know when to sample the signal for the best noise performance. One simple method for recovering symbol timing is performed using a delay-locked loop (DLL). Figure 2.11 is a block diagram of the necessary components. [22]-[24]

Match Filter Symbol Sampler Offset Decision Late Sample Early Sample On Time Sample DLL Block Diagram decision statistic

The goal of the DLL is to sample the waveform at the peaks in order to obtain the best performance in the presence of noise. If it is not sampling at the peaks, we say it is sampling too early or too late. The DLL finds peaks without assistance from the user. When it begins running, it arbitrarily selects a sample, called the on-time sample, from the matched filter output. The sample from the time-index one greater than that of the on-time sample is the late sample, and the sample from the time-index one less than that of the on-time sample is the early sample. The early, on-time and late samples together form a detection set. Figure 2.12 shows examples of detection sets where the on-time sample comes at a peak, before, and after the peak.

Early Sample On-Time Sample Late Sample Detection Set sa m ple va lu e Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e (a) (b) (c) Early Sample On-Time Sample Late Sample Detection Set sa m ple va lu e Early Sample On-Time Sample Late Sample Detection Set Early Sample On-Time Sample Late Sample Detection Set sa m ple va lu e Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e Early Sample On-Time Sample Late Sample Detection Set Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e Early Sample On-Time Sample Late Sample Detection Set Early Sample On-Time Sample Late Sample Detection Set sa m ple v alu e (a) (b) (c)

Figure 2.12: Detection set of delay-locked-loop

The on-time sample is the output of the DLL and will be used to decide the data bit sent. To achieve the best performance in the presence of noise, the DLL must adjust the timing of on-time samples to coincide with peaks in the waveform. It does this by changing the number of time-indices between on-time samples. Recall that the symbol duration is T and the upsample rate at the transmitter is 4. Accordingly, one transmitted symbol will occupies 4T in time after upsampling. Therefore, three cases

1. In Figure 2.12(a), the on-time sample is already at the peak, and the receiver knows that peaks are spaced by 4T. If it then takes the next on-time sample 4T

samples after this on-time sample, it will be at another peak.

2. In Figure 2.12(b), the on-time sample is too early. Taking an on-time sample 4T samples later will be too early for the next peak. To move closer to the next

peak, the next on-time sample is taken 4T + T = 5T samples after the current

on-time sample.

3. In Figure 2.12(c), the on-time sample is too late. Taking an on-time sample 4T samples later will be too late for the next peak. To move closer to the next peak, the next on-time sample is taken 4T - T =3T samples after the current on-time sample.

The input to the offset decision block in Figure 2.11 is called the decision

statistic. When the decision statistic is positive, the on-time sample is too early; when

it is zero, the on-time sample is at a peak, and when it is negative, the on-time sample is too late. The offset decision block could adjust the time at which the next on-time sample is taken based on the decision statistic. However, in the presence of noise, the decision statistic becomes a less reliable indicator. In this thesis, a modified DLL algorithm is proposed. Figure 2.13 shows a real case of the beginning of a received oversampled waveform, derived at the output of the match filter. From the packet structure discussed in Section 2.2.4, we know that this is the beginning part of short preambles. Since the amplitude of preamble symbol is known at the receiver, through simulation we know that the correct sample points of the oversampled waveform should be the ones circled as shown, with amplitude around 2 in our case.

The amplitude of the ideal sampling point is

approximately 2

The amplitude of the ideal sampling point is

approximately 2

Figure 2.13: Oversampled waveform with the correct sample points

Therefore, if the detection set is chosen such that the on-time sample is “too far away” from the correct sample, the modified DLL algorithm will not let current on-time sample be the output, but shift the detection set by one symbol to make the new on-time sample be “closer to” the nearest correct sample and be the new output, as shown in Figure 2.14. The direction that the detection set is shifted is determined by the decision statistics as mention above. A full algorithm flow chart is shown in Figure 2.15.

Correct samples

Original Detection Set New Detection Set

Correct samples

Original Detection Set New Detection Set

Correct samples

Original Detection Set New Detection Set

Correct samples

Original Detection Set New Detection Set

idle

New determination set?

next_dis = 0 ? Early or Late? sign(d2)=sign(d3-d1)? Late : Need Modification ? abs(d2) > thr. ? Early : Need Modification ? abs(d2) > thr. ? Need Modification : Late or On Time ? abs(d3-d1) > diff. ? No Modification : Late or On Time ? abs(d3-d1) > diff. ? Need Modification : Early or On Time ? abs(d3-d1) > diff. ? No Modification : Early or On Time ? abs(d3-d1) > diff. ? Yes No No No No Yes No Yes Yes No

dout = d2 dout = d3 dout = d2 dout = d1

next_dis = 4 next_dis = 3 next_dis = 5 next_dis = 4 next_dis = 2 next_dis = 3 next_dis = 1 next_dis = 2 Yes No Yes No Yes Yes idle

New determination set?

next_dis = 0 ? Early or Late? sign(d2)=sign(d3-d1)? Late : Need Modification ? abs(d2) > thr. ? Early : Need Modification ? abs(d2) > thr. ? Need Modification : Late or On Time ? abs(d3-d1) > diff. ? No Modification : Late or On Time ? abs(d3-d1) > diff. ? Need Modification : Early or On Time ? abs(d3-d1) > diff. ? No Modification : Early or On Time ? abs(d3-d1) > diff. ? Yes No No No No Yes No Yes Yes No

dout = d2 dout = d3 dout = d2 dout = d1

next_dis = 4 next_dis = 3 next_dis = 5 next_dis = 4 next_dis = 2 next_dis = 3 next_dis = 1 next_dis = 2 Yes No Yes No Yes Yes

2.3.2

Frequency Synchronizer

The purpose of frequency synchronization is to correct the frequency offset, which is caused by the difference of oscillator frequencies at the transmitter and the receiver and may degrade the system performance [25]. Therefore, we try to estimate the frequency offset and compensate the received signals.

Assuming that the absolute value of the frequency offset does not exceed 1 2DT_d ,

where D is the delay between the identical samples of the two symbols; T_d denotes the sampling period. To derive the estimated frequency offset, an intermediate variable z is defined as:

1 * 0 L n n D n z − r r₊ = =

∑

where rn is one of the two identical symbols, and L is the symbol length. After a series

of derivation, the estimated frequency offset fˆ+ can be shown by

l 2 _d z f DT π Δ = − ( (2.9)

where (z can be computed by an arc tangent of the summation of conjugate multiplications between these two identical symbols. To do the above task, the preamble channel becomes the most proper candidate.

The 802.11a standard specifies a maximum oscillator error of 20 ppm; therefore the total maximum error is 40 ppm. Supposing that the carrier frequency is 5.3 GHz, the maximum possible frequency error is about 212 kHz. Owing to the inherent structures of short preamble and long preamble, the maximum unambiguous estimated frequency offset is 625 kHz for short preamble and 156.25 kHz for long preamble. Therefore, both short preamble and long preamble are required to estimate frequency offset so as to cover the probable frequency offset specified by the standard. In our thesis we use short preamble as a means to estimate the frequency offset.

2.3.3

Channel Estimator

Unlike conventional time domain equalization that uses one or more transversal filters taps with the number of data symbols spanned by the multipath, Frequency domain equalization has been shown to be an attractive solution for frequency selective channels in a single carrier system. Compared to the time-domain equalization, FDE outperforms the conventional time-domain equalization when the channel is highly dispersive, and it requires less complexity than maximum likelihood sequence estimation (MLSE) by using fast Fourier transform. The main task of the frequency domain equalizer is to eliminate inter-symbol interference within the individual frames. As long as the guard interval with duration TG is longer than the

channel impulse response (with duration Th), there is no interference between the

information symbols of successive frames.

The channel can be estimated using the known training symbols within the preamble. In our system, owing to the same symbol structure as data symbols, long preamble becomes the best candidate for performing this job. Let R and_{i k,} X denote _k

the frequency response of the i-th received long preamble and the original long preamble, the estimated channel frequency response is then derived by:

l

(

)

(

)

(

)

Let Dk be the frequency response of received data symbol, the ZF channel

equalization can be shown as:

m mk K k D S H = (2.11)

2.3.4 Phase Estimator

The processing of the preamble takes care of the initial synchronization of the SC-FDE receiver. However, there will always be some remaining phase offset after the initial preamble based carrier frequency synchronization, varying during the reception of the packet, making solely initial frequency synchronization insufficient. Furthermore, the system will experience phase noise produced by the combination of the RF oscillator and the phase-locked loop (PLL). In OFDM systems this residual offset causes inter-carrier interferences and a rotation of the constellation. In SC-FDE systems this residual offset also causes a rotation of the whole constellation from one received frame to the another, but instead of inter-carrier interferences, which cause a random spreading of the constellation points, the constellation points of the individual symbols experience a 1-D spreading along a circle (in the case of perfect timing synchronization). Figure 2.16 shows the constellation diagram of one equalized frame (48 data symbols, 16 UW symbols) in the QPSK mode in the presence of residual phase offset. It is, therefore, necessary to estimate and correct the rotation of the received constellation points.

-1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5

Constellation with residual CFO

Real Im a g UW -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5

Constellation with residual CFO

Real Im a g UW UW

The phase rotation from one frame to the next one caused by a residual CFO

f

Δ is 2πΔfT_FFT , and the phase rotation from one individual symbol to the other is 2πΔfT. In the classical cyclic prefix approach (as used in OFDM, and in earlier SC-FDE proposals [10]), the guard interval is formed by data symbols, and the cyclic prefix is not processed any longer at the receiver. One major advantage of the UW approach is the fact, that the guard interval is part of the FFT-window and is therefore equalized together with the information symbols. Therefore the equalized UW-symbols can effectively be used for different synchronization tasks.

The mean rotation phase of the constellation diagram caused by a residual CFO

f

Δ accumulates linearly from one frame to another. If the phase of the first frame is

1

Θ then the phase of the n-th block is given by Θ = Θ +_{n 1} (n− ΔΘ 1) _n withΔΘ =_n 2πΔfT_FFT. The straightforward approach to track the phase is to use an average of 16 Unique Word phase errors, and to de-rotate the constellation by the estimated phase. However, due to the fact that the UW-symbols are positioned at the end of a frame, they experience a larger phase rotation than the data symbols. Fortunately, according to the linearly-accumulated phase error properties mentioned above, it is possible to linearly de-spread the constellation points using an individual de-rotation once we derive the known average Unique Word phase errors [14].

The phase tracking algorithm is summarized in Table 2.2, and the phase compensation result will be given in the MATLAB floating point verification part in Chapter 4.

Table 2-2: Proposed phase tracking algorithm

-1 0 -- 2 / 2 0 1

- Equalize the -th frame by

- Determine the estimate of current frame by averaging over the 16 UW phase errors

- De-rotate each received symbol ( ) by

n n FFT j n j kT T Set for n to N n e r k e Θ Θ − Θ = = Θ + + ( ) -1 - Determine the accumulated phase offset

G T n n n end Θ = Θ + Θ+ -1 0 -- 2 / 2 0 1

- Equalize the -th frame by

- Determine the estimate of current frame by averaging over the 16 UW phase errors

- De-rotate each received symbol ( ) by

n n FFT j n j kT T Set for n to N n e r k e Θ Θ − Θ = = Θ + + ( ) -1 - Determine the accumulated phase offset

G

T

n n n

end

2.3.5 Viterbi Decoder

Decoding of convolutional codes is most often performed by the Viterbi decoder, which is an efficient way to obtain the optimal maximum likelihood estimate of the encoded sequence [26][27]. Viterbi decoder can be further divided into hard-decision and soft-decision decoding, where hard-decision is adopted in out system. According to the design of the convolutional encoder in transmitter, we can derive the state transition table in Table 2.3 and then further illustrate the trellis diagram as shown in Figure 2.17 and Figure 2.18.

The Viterbi algorithm is a recursive sequential minimization algorithm that can be used to find the least expensive way to route symbols from one edge of a state diagram to another. To do this, the algorithm uses a cost analysis mechanism to calculate the distance between the received symbol and the symbol associated to that edge. The distance between the received symbol s and the symbol associated to that edge in the state diagram is often referred to as the branch metric. If BM [i, j](s), is the metric of the branch from state i to state j, the problem is finding the path for which the metric, i.e. the sum of the branch metrics of the path edges, is at a minimum. The Viterbi algorithm solves this problem by applying the following recursive equation for each state transition

(

)

[ ]( ) min [ ]( -1) [ , ]( )

PM j t = PM i t + BM i j s (2.12)

where PM [j](t) is the path metric associated to the (minimum cost path leading to) state j at time t. At the end of the decoding, it is possible to reconstruct the maximum likelihood sequence through a trace back starting from the possible decoder states. Normally for decoders using non-punctured codes, the trace back depth equals five-times constraint length, which is sufficient to decode the correct output in the presence of noise. In our system, constraint length equals 5; therefore an appropriate trace back depth is 25.

Table 2-3: State transition table

din s0 s1 s2 s3 state g2 g1 g0 s0' s1' s2' s3' state' din s0 s1 s2 s3 state g2 g1 g0 s0' s1' s2' s3' state'

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 8 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 8 0 0 0 1 0 2 1 1 0 0 0 0 1 1 1 0 0 1 0 2 0 0 1 1 0 0 1 9 0 0 0 1 1 3 0 0 1 0 0 0 1 1 1 0 0 1 1 3 1 1 0 1 0 0 1 9 0 0 1 0 0 4 1 0 1 0 0 1 0 2 1 0 1 0 0 4 0 1 0 1 0 1 0 10 0 0 1 0 1 5 0 1 0 0 0 1 0 2 1 0 1 0 1 5 1 0 1 1 0 1 0 10 0 0 1 1 0 6 0 1 1 0 0 1 1 3 1 0 1 1 0 6 1 0 0 1 0 1 1 11 0 0 1 1 1 7 1 0 0 0 0 1 1 3 1 0 1 1 1 7 0 1 1 1 0 1 1 11 0 1 0 0 0 8 1 1 0 0 1 0 0 4 1 1 0 0 0 8 0 0 1 1 1 0 0 12 0 1 0 0 1 9 0 0 1 0 1 0 0 4 1 1 0 0 1 9 1 1 0 1 1 0 0 12 0 1 0 1 0 10 0 0 0 0 1 0 1 5 1 1 0 1 0 10 1 1 1 1 1 0 1 13 0 1 0 1 1 11 1 1 1 0 1 0 1 5 1 1 0 1 1 11 0 0 0 1 1 0 1 13 0 1 1 0 0 12 0 1 1 0 1 1 0 6 1 1 1 0 0 12 1 0 0 1 1 1 0 14 0 1 1 0 1 13 1 0 0 0 1 1 0 6 1 1 1 0 1 13 0 1 1 1 1 1 0 14 0 1 1 1 0 14 1 0 1 0 1 1 1 7 1 1 1 1 0 14 0 1 0 1 1 1 1 15 0 1 1 1 1 15 0 1 0 0 1 1 1 7 1 1 1 1 1 15 1 0 1 1 1 1 1 15

din s0 s1 s2 s3 state g2 g1 g0 s0' s1' s2' s3' state' din s0 s1 s2 s3 state g2 g1 g0 s0' s1' s2' s3' state'

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 8 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 8 0 0 0 1 0 2 1 1 0 0 0 0 1 1 1 0 0 1 0 2 0 0 1 1 0 0 1 9 0 0 0 1 1 3 0 0 1 0 0 0 1 1 1 0 0 1 1 3 1 1 0 1 0 0 1 9 0 0 1 0 0 4 1 0 1 0 0 1 0 2 1 0 1 0 0 4 0 1 0 1 0 1 0 10 0 0 1 0 1 5 0 1 0 0 0 1 0 2 1 0 1 0 1 5 1 0 1 1 0 1 0 10 0 0 1 1 0 6 0 1 1 0 0 1 1 3 1 0 1 1 0 6 1 0 0 1 0 1 1 11 0 0 1 1 1 7 1 0 0 0 0 1 1 3 1 0 1 1 1 7 0 1 1 1 0 1 1 11 0 1 0 0 0 8 1 1 0 0 1 0 0 4 1 1 0 0 0 8 0 0 1 1 1 0 0 12 0 1 0 0 1 9 0 0 1 0 1 0 0 4 1 1 0 0 1 9 1 1 0 1 1 0 0 12 0 1 0 1 0 10 0 0 0 0 1 0 1 5 1 1 0 1 0 10 1 1 1 1 1 0 1 13 0 1 0 1 1 11 1 1 1 0 1 0 1 5 1 1 0 1 1 11 0 0 0 1 1 0 1 13 0 1 1 0 0 12 0 1 1 0 1 1 0 6 1 1 1 0 0 12 1 0 0 1 1 1 0 14 0 1 1 0 1 13 1 0 0 0 1 1 0 6 1 1 1 0 1 13 0 1 1 1 1 1 0 14 0 1 1 1 0 14 1 0 1 0 1 1 1 7 1 1 1 1 0 14 0 1 0 1 1 1 1 15 0 1 1 1 1 15 0 1 0 0 1 1 1 7 1 1 1 1 1 15 1 0 1 1 1 1 1 15 S0 S0 S8 S0 S8 S0 S8 S4 S12 S0 S8 S4 S12 S0 S8 S4 S12 S2 S10 S6 S14 S0 S8 S4 S12 S2 S10 S6 S14 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 0/000 1/111 0/000 1/111 0/110 1/001 0/000 1/111 0/000 1/111 0/000 1/111 0/110 1/001 0/101 1/010 0/011 1/100 0/110 1/001 0/101 1/010 0/011 1/100 0/110 1/001 0/000 1/111 0/011 1/100 0/101 1/010 1/001 0/110 1/010 0/101 1/100 0/011 1/001 0/110 1/111 0/000 1/100 0/011 1/010 0/101 1/000 0/111 1/110 0/001 1/101 0/010 1/011 0/100 1/110 0/001 1/000 0/111 1/011 0/100 1/101 0/010

S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 S0 S8 S4 S12 S2 S10 S6 S14 S1 S9 S5 S13 S3 S11 S7 S15 0/000 1/111 1/001 0/110 1/010 0/101 1/100 0/011 1/001 0/110 1/111 0/000 1/100 0/011 1/010 0/101 1/000 0/111 1/110 0/001 1/101 0/010 1/011 0/100 1/110 0/001 1/000 0/111 1/011 0/100 1/101 0/010 S0 S4 S2 S6 S1 S5 S3 S7 S0 S4 S2 S6 S1 S5 S3 S7 S0 S2 S1 S3 S0 S2 S1 S3 S0 S1 S0 S1 S0 0/010 0/100 0/111 0/001 0/100 0/010 0/001 0/111 0/101 0/011 0/000 0/110 0/011 0/101 0/110 0/000 0/000 0/000 0/000 0/100 0/001 0/010 0/111 0/011 0/110 0/101 0/001 0/111 0/110 0/111

Figure 2.18: Trellis diagram part 2

2.4 Summary

In this chapter, we introduce the SC-FDE system, and propose our system architecture including the transmitter and receiver. At the transmitter, convolutional encoder, mapper, UW generator, preamble channel generator, the polyphase filter design of upsampler and root-raised cosine filter are gone through. At the receiver, timing synchronization is first mentioned, which consists of packet detection, match filtering and symbol timing recovery. Frequency synchronization and channel estimation then follow, and phase estimation is proposed. Finally, de-mapper, and Viterbi decoder are described in the rest part of the receiver. In this chapter we highlight the two algorithms proposed: the modified delay-locked-loop algorithm for timing recovery and the UW-based phase tracking algorithm implemented on the system as an independent section to give a detailed introduction. More experimental results and performance analysis will be given in Chapter 4.

Chapter 3

SC-FDE System Platforms

In Chapter 3, we will introduce our self-designed platform as the development environment. The platform is used to perform the verification of whole SC-FDE system including baseband and RF parts, where transmitter and receiver are implemented on two separated boards with their own RF modules each. The self-designed platform is closer to a real wireless communication system and therefore can take all phenomena and effects of the wireless system into account. In the following sections, hardware modules, hardware description language, software design flows, and the corresponding debugging tools of our platforms are detailed explained.

3.1 Self-designed Platform

In order to approach a real wireless communication system, the multi- synchronous and high-speed bus FPGA design, combined with our module-based RF, AD/DA, and MAC/BB hardware system, becomes the best solution. Our laboratory has finished and successfully tested RF, AD/DA and MAC/BB boards. The development environment is shown in Figure 3.1, and the close-up shot of main board is shown in Figure 3.2, where four Xilinx Virtex II 6000 FPGAs are mounted in MAC/BB board, and each MAC/BB board is able to connect with at most two AD/DA and two RF modules.

In order to avoid the interference between high speed digital bus, those layouts and interconnections of different modules shall be handled very carefully. Our measurements show that directly connected modules did achieve feasible solution which reduces the risk of facing interconnection problems. Further analysis and evaluation during development are given in the following sections.

Figure 3.1: Development environment of self-designed platform

3.1.1 RF Module

The RF module, as shown in Figure 3.3 consists of MAX2828, which is specifically designed for single-band IEEE 802.11a applications covering world-band frequencies of 4.9 GHz to 5.875 GHz. MAX2828 includes all circuitry required to implement the RF transceiver function, providing a fully integrated receive path, transmit path, voltage-controlled oscillator (VCO), frequency synthesizer, and baseband control interface. Only the RF switches, RF bandpass filters (BPF), RF baluns, and a small number of passive components are required to form the complete RF front-end solution. Because the balance of I/Q signals will impact on the waveform of RF output, the RLC components had been fine tuned. Besides, we also tested the frequency accuracy and power level of transmitted carriers in our interested band from 5.15 GHz to 5.875 GHz. One of those measurements is shown in Figure 3.4; the power level shall be further improved with fine tuning of matching circuits. We used 3-wires (Clock, Data and Latch) to control the RF module from PC currently, and then the control mechanism will be integrated into MAC/BB after verification. In sum, MAX2828 completely eliminates the need for external SAW filters by implementing on-chip monolithic filters for both the receiver and transmitter. The baseband filtering and the Rx/Tx signal paths are optimized to meet the IEEE 802.11a and 802.11g standards. It is also suitable for the full range of the corresponding 802.11a/g OFDM data rates (6Mbps, 9Mbps, 12Mbps, 18Mbps, 24Mbps, 36Mbps, 48Mbps, and 54Mbps) and 802.11g QPSK data rates (1Mbps, 2Mbps, 5.5Mbps, and 11Mbps), at the required sensitivity levels.

Figure 3.3: RF module on self-designed platform 1 A P C L R W R A R e f 2 0 d B m A t t 5 0 d B C e n t e r 5 . 4 G H z 2 0 0 k H z / S p a n 2 M H z R B W 1 0 0 k H z V B W 3 0 0 k H z S W T 2 . 5 m s 0 6 . N o v 0 5 2 0 : 1 4 P R N - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 D e l t a 2 [ T 1 ] 0 . 0 0 d B 0 . 0 0 0 0 0 0 0 0 0 H z M a r k e r 1 [ T 1 ] - 5 0 . 8 0 d B m 5 . 3 9 9 0 0 0 0 0 0 G H z 2 1 D a t e : 6 . N O V . 2 0 0 5 2 0 : 1 4 : 2 4