CHAPTER 3 Review of Low-Power LNA Design
4.2 The Proposed Low-Power UWB LNA
4.2.6 Simulation and Measurement Result
The simulated results of the LNA with SFBB technique compare with that of the LNA without SFBB technique.
The simulated input impedance matching (S11) with and without SFBB technique are shown in Figure 4.14 and Figure 4.15 respectively:
0 1 2 3 4 5 6 7
Frequency (GHz) S11(dB)
-20 -15 -10 -5
Figure 4.14 Simulated S11 (input impedance matching) with SFBB technique.
Figure 4.15 Simulated S11 (input impedance matching) without SFBB technique under different supply voltages.
Chapter 4 Design of Low-Power SFBB UWB LNA
The simulated reverse isolation (S12) with and without SFBB technique are shown in Figure 4.16 and Figure 4.17 respectively:
Figure 4.16 Simulated S12 (reverse isolation) with SFBB technique.
Figure 4.17 Simulated S12 (reverse isolation) without SFBB technique under different supply voltages.
Chapter 4 Design of Low-Power SFBB UWB LNA
The simulated gain (S21) with and without SFBB technique are shown in Figure 4.18 and Figure 4.19 respectively:
Figure 4.18 Simulated S21 (gain) with SFBB technique.
0 1 2 3 4 5 6 7
Frequency (GHz) S21(dB)
0 5 15 10 20 25 30
-5
Figure 4.19 Simulated S21 (gain) without SFBB technique under different supply voltages.
Chapter 4 Design of Low-Power SFBB UWB LNA
The simulated output impedance matching (S22) with and without SFBB technique are shown in Figure 4.20 and Figure 4.21 respectively:
Figure 4.20 Simulated S21 (output impedance matching) with SFBB technique.
0 1 2 3 4 5 6 7
Frequency (GHz) S22(dB)
-19 -18 -17 -16 -16 -15
without SFBB
Figure 4.21 Simulated S22 (output impedance matching) without SFBB technique under different supply voltages.
Chapter 4 Design of Low-Power SFBB UWB LNA
The simulated noise figure (NF) with and without SFBB technique are shown in Figure 4.22 and Figure 4.23 respectively:
Figure 4.22 Simulated noise figure with SFBB technique.
Figure 4.23 Simulated noise figure without SFBB technique under different supply voltages.
Chapter 4 Design of Low-Power SFBB UWB LNA
The simulated performance summary of with SFBB and without SFBB for different supply voltage is shown in Table 4.1.
Table 4.1 Simulated performance summary of wi/wo SFBB for different supply voltage.
Supply
The measured results of the LNA with SFBB technique compare with the simulated results.
The measured and simulated input impedance matching (S11) of the proposed LNA is shown in Figure 4.24:
Figure 4.24 Measured and simulated S11 (input impedance matching) of the proposed LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured and simulated output impedance matching (S22) of the proposed LNA is shown in Figure 4.25:
Figure 4.25 Measured and simulated S22 (output impedance matching) of the proposed LNA.
The measured and simulated gain (S21) of the proposed LNA is shown in Figure 4.26:
Figure 4.26 Measured and simulated S21 (gain) of the proposed LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured and simulated reverse isolation (S12) of the proposed LNA is shown in Figure 4.27:
0 1 2 3 4 5 6 7
Frequency (GHz) -100
S12(dB)
-30
-50 -40
-70 -60
-80 -90
Figure 4.27 Measured and simulated S12 (reverse isolation) of the proposed LNA.
The measured and simulated noise figure (NF) of the proposed LNA is shown in Figure 4.28:
Figure 4.28 Measured and simulated NF (noise figure) of the proposed LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured 3rd-order input intercept point (IIP3) at 4 GHz of the proposed LNA is shown in Figure 4.29:
Figure 4.29 Measured third-order input intercept point (IIP3) at 4 GHz of the proposed LNA.
The measured 3rd-order input intercept point (IIP3) versus frequency of the proposed LNA is shown in Figure 4.30:
Figure 4.30 Measured third-order input intercept point (IIP3) versus frequency of the proposed LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured 1-dB compression point (P1dB) at 4 GHz of the proposed LNA is shown in Figure 4.31:
Figure 4.31 Measured 1-dB compression point (P1dB) at 4 GHz of the proposed LNA.
The performance summary of the proposed LNA and comparison with several papers that has been proposed and published is shown in Table 4.2.
Table 4.2 The performance summary of the proposed LNA and comparison with several papers.
Ref. Tech. BW
Chapter 4 Design of Low-Power SFBB UWB LNA
The chip layout and microphotograph of the proposed LNA are shown in Figure 4.32(a) and Figure 4.32(b) respectively, and the chip area is 0.96 mm × 0.64 mm (0.61 mm2).
Figure 4.32 (a) Layout, (b) microphotograph of the proposed LNA.
4.3 Noise Improvement for The proposed LNA
In the preceding LNA design, called the LNA 1 after here, more substrate thermal noise will be coupled to MOSFET channel under the self forward bulk-source bias than that under zero bulk-source bias will, since the bulk-source depletion becomes narrow. And the complementary architecture also degrades the noise figure significantly, because there are two channel thermal noise sources and two induced gate noise sources in the first stage. For these issues, we have to find some ways to improve the noise performance.
4.3.1 Noise Improvement
Under the forward bulk-source bias, the depletion between the channel and substrate becomes narrower than zero bulk-source bias does. As shown in Figure 4.32, thermal noise contributed from the substrate will be coupled to channel more easily. Therefore, we utilize a capacitor that provides a path for the substrate thermal noise toward ground as well as does not affect the self voltage-divided loop.
Chapter 4 Design of Low-Power SFBB UWB LNA
Figure 4.33 Reduce the noise contributed from the substrate.
Figure 4.34 The proposed noise-improved LNA.
In order to suppress the noise contribution from the substrate and R1, we employ two capacitances, C1 and C2, to provide the paths for these noise sources toward ground, as shown in Figure 4.33.
Another significant noise degradation results from the complementary architecture since there are two channel thermal noise sources and two induced gate noise sources in the first stage. To improve the noise degradation, we select to suppress the channel thermal noise contributed from M2 by coupling both the inductors, LS2 and LD.
Chapter 4 Design of Low-Power SFBB UWB LNA
Figure 4.35 The proposed noise-improved LNA with equivalent channel thermal noise source .
From Figure 4.34, at the first, we assume that the channel thermal noise voltage at X contributed from M2 is positive while negative at Y relatively. Thus, the noise voltage at Z which is resulted from the noise voltage at Y through the cascode stage path is given by
, ω || ω || ω
,
(4.24) where A and B represent the imaginary and real part respectively.
At this point, in order to suppress the channel thermal noise contributed from M2, we utilize another path, mutual inductor (LS2, LD), toward Z to reduce the noise with opposite polarity to that of (2.4). The channel thermal noise voltage contributed from M2 through the mutual path at Z is negative while positive at X assumed above, which is given by.
/
/ ω ωM (4.25)
where n, M, and K denotes the turn ratio, mutual inductance and coupling coefficient, and C and D represent the imaginary and real part respectively.. Therefore, combining both the contrary noise voltage at point Z can achieve the noise suppression. Furthermore, using the mutual inductor can reduce the chip area effectively.
However, there is an issue while using this mutual inductor mentioned above. From Figure 4.34, the RF signal at point X and point Y are out of phase of that at point Z, and the second cascode stage that provides a negative voltage gain. Then, this loop forms a positive
Chapter 4 Design of Low-Power SFBB UWB LNA
feedback that the LNA may not stable to oscillate. Consequently, there is a tradeoff between the noise suppression and unstable condition. Thus, we separate both the inductor a little to avoid oscillating. The chip layout and microphotograph of the proposed LNA are shown in Figure 4.35(a) and (b) respectively, and the chip area is 0.99 mm × 0.47 mm.
(a) (b)
0.99 mm
0.47 mm
Figure 4.36 (a) Layout, (b) microphotograph of the proposed noise-improved LNA.
4.3.2 Measurement Result
The measured results of the noise-improved LNA, called the LNA 2 with SFBB technique compare with that of the preceding LNA, called the LNA 1.
The measured noise figure (NF) of the proposed noise-improved LNA is shown in Figure 4.37:
Figure 4.37 Measured NF of the proposed noise-improved LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured S11 of the proposed noise-improved LNA is shown in Figure 4.38:
Figure 4.38 Measured S11 of the proposed noise-improved LNA.
The measured S22 of the proposed noise-improved LNA is shown in Figure 4.39:
Figure 4.39 Measured S22 of the proposed noise-improved LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured S21 of the proposed noise-improved LNA is shown in Figure 4.40:
Figure 4.40 Measured S21 of the proposed noise-improved LNA.
The measured S12 of the proposed noise-improved LNA is shown in Figure 4.41:
0 1 2 3 4 5 6 7
Frequency (GHz) S12(dB)
-30
-50 -40
-70 -60
-80 -90 -100
Figure 4.41 Measured S12 of the proposed noise-improved LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured 3rd-order input intercept point (IIP3) at 4 GHz of the proposed noise-improved LNA is shown in Figure 4.42:
Figure 4.42 Measured IIP3 at 4 GHz of the proposed noise-improved LNA.
The measured third-order input intercept point (IIP3) versus frequency of the proposed noise-improved LNA is shown in Figure 4.43:
Figure 4.43 Measured third-order input intercept point (IIP3) versus frequency of the proposed noise-improved LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The measured 1-dB compression point (P1dB) at 4 GHz of the proposed noise-improved LNA is shown in Figure 4.44:
Figure 4.44 Measured third-order input intercept point (IIP3) at 4 GHz of the proposed noise-improved LNA.
Chapter 4 Design of Low-Power SFBB UWB LNA
The performance summary of the noise-improved LNA and comparison with several papers that has been proposed is shown in Table 4.3.
Table 4.3 The performance summary of the noise-improved LNA and comparison with several papers.
Ref. Tech. BW
Chapter 5 Conclusion
Chapter 5 Conclusion
The low-power UWB LNA has been demonstrated in 0.18-µm CMOS 1P6M process.
Low-power consumption is achieved by using a forward bulk-source bias (or called the forward body bias, FBB). And the forward bulk-source voltage in our design is obtained by means of the proposed ultra-low power self-bias that we don’t need an additional bias circuit to supply the bulk terminal of MOSFET. However, the self forward body bias technique will give rise to some noise figure degradation. Therefore, we proposed the second LNA (LNA 2), to improve the noise figure of the preceding LNA (LNA 1). The measurement result shows that the LNA 1 has a gain of 12.5–15.5 dB from 2.6 to 6.6 GHz with a good input/output matching S11<-10 dB and S22<-17 dB and average noise figure of 3.2 dB while consuming power of 6.3 mW from 1.06 V voltage supply. The chip area is 0.96 mm × 0.64 mm. And the proposed noise-improved LNA 2 to improve the noise figure degraded lightly by the self-bias loop. The measurement result of the LNA 2 shows that it has a gain of 13.5–16.2 dB from 2.0 to 6.6 GHz with a good input/output matching S11<-10 dB and S22<-16 dB and average noise figure of 2.6 dB while consuming power of 4.5 mW from 1.06 V voltage supply. The chip area is 0.98 mm × 0.47 mm.
Reference
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