CHAPTER 3 THE DESIGN, CHARACTERISTICS AND ANALYSIS OF
3.4 SIMULATION RESULTS
3.4.1 Pseudo-BJT-Based Silicon Retina
Fig. 3.11 shows the beta value (current gain) of the NPN pseudo-BJT and PNP
pseudo-BJT. The HSPICE simulation bases on the device parameters of 0.35μm two-poly four-metal n-well CMOS technology. The designed current gain is 25 and the geometric ratio (W/L) is 0.4 μm over 0.35 μm for both NPN and PNP Pseduo-BJT. As indicated in section 3.2, in low-induced current level, the current gain is larger than designed value. When the induced current becomes larger, the current gain approaches to desired values as shown in Fig. 3.11.
Fig. 3.12 shows the smoothing function for the proposed Pseudo-BJT-based silicon retina shown in Fig. 3.6. A linear silicon retina array with 8 pixels being considered verifies the function of smoothing. The light is incident on the 3rd to the 6th pixels, while the photocurrent is simulated in two different current levels, that is1nA and 10nA. The simulated voltage of Vsmooth is –0.03 volt.
The edge-extract function for the proposed Pseudo-BJT-based silicon retina is shown in Fig. 3.13. The same condition as what in smoothing functions is considered.
Note that the current peaks appear in the edge of the light image.
Fig. 3.14 shows the simulated output current waveform of a cell in a linear silicon retina array with the moving-object image incident on the array. The speed of the moving object is 1.25x 106 cells/sec and the photocurrent is simulated in 1 nA.
Fig. 3.15 (a) shows 2-dimensional pattern with the photocurrent incident on 16 pixels locating at the center of the chip of 64 pixels (8x8). The light window simulated in 1 nA is located at row 3rd to row 6th and column 3rd to column 6th. Fig.
3.15(b) shows the extracted output current under the situation described in Fig. 3.15 (a). Greater response occurs in four corners because the corners locate at the intersection of the two edges.
Fig. 3.16 shows the edge-extract function for the proposed Pseudo-BJT-based silicon retina. A linear silicon retina array with 32 pixels being considered verifies the function of edge-extraction. The light is incident on the 12th to the 19th pixels, while the photocurrent is simulated in two different current levels, that is 25nA and 125nA.
The corresponding voltage of Vsmooth is 0.9volt and 1volt, respectively.
Fig. 3.17 shows the edge-extract function under different smoothing biases. A linear silicon retina array with 32 pixels is considered. The simulation condition is shows in Table 3.1.
Fig. 3.18 shows the flash reaction of the proposed silicon retina in a linear array with 32 pixels. The simulated condition is shown in Table 3.2. There is overshooting when the light turns on, but this phenomenon becomes unapparent when the input photocurrent decreases to 25nA.
Fig. 3.19 shows the effect of the capacitor produced by pn-diode in the pixel circuit. Fig.3.18 (a) shows the pre-simulation and post-simulation result of the flash reaction of the proposed silicon retina. The simulation condition is the same as Table
3.2.
Fig. 3.20 shows the parasitic N-well capacitor in the pixel circuit. The parasitic N-well capacitor is 345fF. Fig. 3.21 shows the comparison of simulation results with and without parasitic N-well capacitor.
Table 3.3 shows the power supply rejection ratio of the proposed silicon retina.
The power supply rejection ration is defined as the ration of current gain of input and current gain of power supply. Consider Pseudo-BJT, the current gain of input current is 26.7 while the current gain of VDD and VSS power supply current is 0.105 and 0.405. Consider the output node, the current gain of input current is 8.8 while the current gain of VDD and VSS power supply is 0.1 and 0.41. Table 3.4 shows the simulated condition of the power supply rejection ratio in Table 3.3.
Fig. 3.22 shows the model to simulate the pn-diode which operates in solar cell mode. The current control current source F1 is used to generate the diode current. The current source Ip is used to generate photocurrent while the pn-diode is under illumination. The summation of the pn-diode current and photocurrent flows through the output resistor to define the bias condition of the pn-diode by a voltage control voltage source which. The components and their corresponding meaning are shown in Table 3.5.
With the solar cell model shown in Fig. 3.22, the simulated flash light reaction of solar cell is shown in Fig. 3.23. As the light turns on, the voltage of solar cell increases to a stable voltage in a very quick manner. As the light turns off, the voltage of the solar cell decreases slowly. Since the artificial retina need not work while the light is off, the unstable voltage of solar cell would not affect the performance the silicon retina. Thus, the solar cell is suitable power supply for silicon retina.
Fig. 3.1 Visualization of light absorption, electron-hole creation, and the light-induced current in a pn junction diode. Reprinted from “Semiconductor Device Fundamentals,” by Robert F. Pierret, 1996, pp. 349.
Fig. 3.2 Photodiode I-V characteristics. Reprinted from “Semiconductor Device Fundamentals,” by Robert F. Pierret, 1996, pp. 350.
Output Output Output Output
(a)Output Output Output Output
(b)
Output Output Output Output
(c)
Output Output Output Output
(d)
Fig. 3.3 Four different diode array designed as artificial retina.
Fig. 3.4. A p+-n-well diode and a current mirror with current gain of 8 formed by PMOS as the artificial retina.
(a)
(b)
Fig. 3.5. The circuit diagram of (a) npn pseudo-BJT (PBJT) and its device symbol, (b) pnp pseudo-BJT (PBJT) and its device symbol.
Fig. 3.6. The pixel circuit of the proposed low-power implantable PBJT-based retina circuit.
Fig. 3.7 Architecture of 2-D retinal array of 32x4 pixels. The column decoder converts five-bit binary column address to decimal number.
CELL CELL CELL
CELL CELL CELL CELL
Column Decoder Column Address
CELL CELL CELL CELL
CELL CELL
CELL
CELL
CELL CELL CELL CELL CELL
4
……
……
……
……
-2.00E-05 -1.50E-05 -1.00E-05 -5.00E-06 0.00E+00 5.00E-06 1.00E-05
-6.00E-01 -4.00E-01 -2.00E-01 0.00E+00 2.00E-01 4.00E-01 6.00E-01
V(volt) I(A)
Phi=0W Phi=30W Phi=60W Phi=90W Phi=120W
Fig. 3.8 The I-V characteristics of a teskey of pn junction diode.
-6.0 -3.0 0.0 3.0 6.0
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Voltage (V) Current (μA)
Light source = 0W Light source = 30W Light source = 60W Light source = 90W load line
Fig. 3.9. Characteristic I-V curves of the teskey and a load line of the proposed circuits.
Fig, 3.10. One block of solar cell as power supply. Positive and negative power supply formed by 2 series-wound solar cells and 1200 paralleled solar cells respectively exploiting the tissue potential varying from -60mV to -35mV.
Fig. 3.11. The beta value (current gain) of the NPN pseudo-BJT (the upper one) and PNP pseudo-BJT (the lower one).
(a)
(b)
Fig. 3.12. The smoothing function of pseudo-BJT-based silicon retina simulated under the photocurrent of (a) 1nA, (b) 10nA.
(a)
(b)
Fig. 3.13. The edge-extract function of pseudo-BJT-based silicon retina simulated under the photocurrent of (a) 1nA, (b) 10nA.
Fig. 3.14. The simulated output current waveform of a cell in a linear silicon retina array with the moving-object image incident on the array. The generated photocurrent I is 1nA and the speed of the moving object is 1.25x 106 cells/sec.
(a)
(b)
Fig. 3.15. (a) The 2-dimensional pattern with the photocurrent incident on 16 pixels locating at the center of the chip of 64 pixels (8x8). The light window simulated in 1 nA is located at row 3rd to row 6th and column 3rd to column 6th. (b) The corresponding edge-extract output current.
(a)
(b)
Fig. 3.16. (a) The edge-extract function for the proposed Pseudo-BJT-based silicon retina (32 pixels). The light is incident on the 12th to the 19th pixels, while the photocurrent is simulated in two different current levels, that is, 25nA (a) and 125nA (b). The corresponding voltage of Vsmooth is 0.9volt and 1volt, respectively.
Fig. 3.17. (a) The edge-extract function under different smoothing biases. A linear silicon retina array with 32 pixels is considered. The simulation condition is shows in Table 3.1.
Table. 3.1. The simulation condition of Fig. 3.17.
Fig. 3.18.The flash reaction of the proposed silicon retina in a linear array with 32 pixels. There is overshooting when the light turns on, but this phenomenon becomes unapparent when the input photocurrent decreases to 25nA.
Table. 3.2. The simulation condition of Fig. 3.18.
Fig. 3.19. The pre-simulation and post-simulation result of the flash reaction of the proposed silicon retina. The simulation condition is the same as Table 3.2.
Fig. 3.20. The parasitic N-well capacitor in the pixel circuit. The parasitic N-well
(a)
(b)
Fig. 3.21 The comparison of simulation results with (a), and without parasitic N-well capacitor (b).
Table. 3.3 The power supply rejection ratio of the proposed silicon retina.
Table 3.4 The simulated condition of the power supply rejection ratio in Table 3.3.
Fig. 3.22. The model to simulate the pn-diode which operates in solar cell mode.
Table 3.5. The components in Fig.3.19 and the corresponding meaning.
Fig. 3.23. The simulated flash reaction of solar cell.
CHAPTER 4
EXPERIMENTAL RESULTS
4.1 LAYOUT DISCREPTION
Two experimental chips are designed and fabricated in a 0.35um double-poly-four-level-metal N-well CMOS technology for implantation and instrument measurement respectively. The chip for implantation consists of a 8x8 array of the proposed Pseudo-BJT-based silicon retina circuit. The total solar cells of area 1064064um2 divided into four blocks. Each blocks contains 2 series-wound and 1200 parallel-wound solar cells. Each pixel occupies area of 900 um2 while the photodiode in each occupy 300um2. Fig 4.1(a), (b) and (c) shows the photograph of the basic cell in the 2-D array, photodiode in single pixel and solar cells respectively whereas Fig. 4.1(d) shows the photograph of the whole implantation chip. The chip for instrument measurement consists of 4x32 array of the proposed Pseudo-BJT-based silicon retina circuit, a decoder and solar cells of area 1097600um2. Figure 4.2 (a) and (b) shows the photograph of the whole chip and the decoder respectively. The ratio between total pixel area and total solar cell area is 10.5%.
4.2 MEASUREMENT RESULTS
Fig. 4.3 (a) shows the measurement setup chart where as Fig. 4.3 (b) shows the corss-sectional drawing of the setup for the chip. The light source is white light provided by illuminator, DRILE model 66182 and model 68830, while the convex with focus of 28cm focuses the light on the chip. The measurement is done with Hp 4145B semiconductor parameter analyzer which biases the output node at half dc power supply. The opaque material is used to shield the light to form the boundary of the light and dark. Figure. 4.4 (a) and (b) shows power and the luminance of the light on the chip versus different input light power under this setup condition. Table 4.1 shows the corresponding luminance of the input light power.
Fig. 4.5 (a) shows the I-V characteristics of the solar cell in the chip for instrument measurement under different luminance. Fig. 4.6 (a) and (b) shows the open circuit voltage and short circuit current. From Fig. 4.6, one can know that the photocurrent generated by solar cell increase dramatically while the light intensity
increase while the voltage of solar cell increase much slower in the same condition.
The overall power-conversion efficiency of single-crystalline solar cells ranges from 10 to 30 % yielding 10 to 30 mW/cm2 [67]. The measured solar cell efficiency is 14.8%.
Fig .4.7 shows flash light reaction of the solar cell in the chip for instrument measurement. The light source is yellow LED with light intensity of 212lux.
Fig. 4.8 shows the spectrum analysis of photodiode.
Fig. 4.9 shows the photograph of the chip with opaque material as a shield from light. The light and dark boundary occurs in the 5th and 13th pixel. Fig. 4.10 (a) shows the post-simulated waveform and the measured waveform of a 1-D array under the light intensity of 736 lux. The smooth voltage is set to 0.9 volt. Fig. 4.10 (b) shows the measured waveform of a 1-D array under the light intensity of 3460 lux. The smooth voltage is set to 1 volt. Table 4.2 and 4.3 shows the post-simulation condition and the measurement condition of Fig. 4.10 (a) and (b), respectively. The pixel locating at the light and dark boundary has large current response, which can be used to stimulus the retinal cell. The current response increases as the light intensity increases. Fig. 4.11 shows the measured waveform of 2-D array under light intensity of 3460 lux. The smooth voltage is set to 1volt.
Fig. 4.12 shows the response of the chip for instrument measurement under flash light. The light intensity is 3460 lux and the smooth voltage is 1 volt.
Fig. 4.13 shows the measured waveform while using the solar cell as power supply in a linear array. The light illuminates on the 0th to 14th pixels, and the light and dark boundary occurs in the 14th pixel. The light intensity is 3460 lux and the smooth voltage is 1 volt. Table 4.4 shows the post-simulation condition and the measurement condition of Fig. 4.13 The power dissipation under this condition is 14.8uW.
4.3 DISSCUSSIONS
The area of solar cell occupies most area of the implantable silicon retina. If we increase the light intensity but keep the photocurrent generated by photodiode in the pixel circuit, the solar cell will performs with higher efficiency. Thus we can reduce the area of solar cell. Table 4.5 shows the required solar cell area if we fix the photocurrent generated in the photodiode in the pixel circuit but increase the light intensity and reduce the photodiode area. Due to the focusing of the lens in the eye, however, the area of solar cell and photodiode can be both reduced about 1.5 times to generate the same photocurrent. Table 4.6 shows the corresponding area of solar cell and photodiode with the consideration of the focusing of lens in the eye.
The measurement waveform shown in Fig. 4.9, 4.10, 4.11 shows ripples in the dark side. This ripples is due to light diffraction and slit interference of the light. Fig.
4.14 shows the typical diffraction and slit interference pattern. Consider the cross-sectional drawing of the setup for the chip in Fig. 4.3 (b), there is truly diffraction and slit interference in this measurement procedure.
Fig. 4.15 explains why the positive and negative peaks are not the same in this work. Even if we choose the smooth voltage so that the smoothing function is half the original response, the negative peak is still less than the positive one.
A key point in implantable retinal prosthesis is how the remaining cells and the implantable silicon retina interact. To demonstrate the function of the proposed silicon retina, the remaining retinal cells of the test animal with implantable retinal prosthesis should be removed. This is because the remaining retinal cells may transmit signal to neurons at next stage and results in interference. After the above-mentioned experiment has been carried out, we can implant the retinal prosthesis to test animal to observe the influence of the remaining retinal cell on the performance of the retinal prosthesis.
4.4 SUMMARY
Table 4.7 shows the summary of the chip for instrument measurement. There are six MOSFET transistors in single pixel circuit. The power dissipation is 14.8uW under the illumination of 736 lux.
(a)
(b)
(c)
(d)
Fig. 4.1 (a) The photograph of the basic cell in the 2-D array, (b) the photodiode in single pixel, (c) solar cells as power supply in the chip for implantation and (d) the photograph of the whole implantation chip.
(a)
Fig. 4.2 (a)The photograph of the whole implantation chip and (b) the decoder
(a)
(b)
Fig. 4.3 (a) The measurement setup chart. (b)The cross-sectional drawing of the setup for the chip.
(a)
(b)
Fig. 4.4 The power (a) and the luminance (b) of the light on the chip versus different input light power under this setup condition.
0.000
Light source
strength(W) 30 60 90 120
Corresponding
luminance (lux) 95 736 2010 3460
Table 4.1 The luminance of the light on the chip under different light source strength.
Fig. 4.5 The I-V characteristics of the solar cell in the chip for instrument measurement. The solar area is 1120umx490um.
(a)
(b)
Fig. 4.6 The open circuit voltage(a) and the short circuit current (b) of the solar cell in the chip for instrument measurement.
Open Circuit Voltage
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
30 60 90 120
Light source strength
Voltage(V)
Fig. 4.7 The flash light reaction of the solar cell in the chip for instrument measurement. The light source is yellow LED with light intensity of 212lux.
Spectral response
0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0. 35 0. 4 0. 45 0. 5
400 450 500 550 600 650 700
Wavelength (nm)
A/W
Fig. 4.8 The spectrum analysis of photodiode under visible light.
Fig. 4.9 The photograph of the chip for instrument measurement with opaque material shielding from light to form the light and dark boundary.
(a)
(b)
Fig. 4.10 The post-simulated waveform and the measured waveform under light intensity of 736 lux and smooth voltage of 0.9 volt (a), and under light intensity of 3460 lux and smooth voltage of 1 volt.
Table 4.2 The post-simulation condition and measurement condition for Fig. 4.10 (a).
Table 4.3 The post-simulation condition and measurement condition for Fig. 4.10 (b).
Fig. 4.11 The measured waveform of the 2-D array under light intensity of 3460 lux and smooth voltage of 1 volt.
Fig. 4.12 The response of the chip under flashlight. The flashlight intensity is 3460 lux and the smooth voltage is 1 volt.
Fig. 4.13 The measured waveform of the chip for instrument measurement. The light intensity is 3460 lux while the smooth voltage is 1 volt.
Table 4.4 The post-simulation condition and measurement condition for Fig. 4.13.
Table 4.5 The required solar cell area under different illumination but fixed photocurrent of photodiode.
Table 4.6 The required solar cell area consideration the focusing of the lens.
Fig. 4.14 Typical diffraction and slit interference pattern.
Original response Smoothing function
Fig. 4.15 The reason why the positive and negative peaks are not the same.
Table 4.7 The summary of the chip for instrument measurement.
CHAPTER 5
CONCLUSIONS AND FURTHER WORKS
5.1 MAIN RESULTS OF THIS THESIS
In this thesis, two Pseudo-BJT-based silicon retina have been designed and fabricated in a 0.35um double-poly-four-level-metal N-well CMOS technology: one is for implantation; the other is for instrument measurement. The I-V characteristics of solar cell are measured and the results proved the possibility of using solar cell as power supply of implantable artificial retina. The functions of the chip for the instrument measurement are verified by using dc power supply and solar cells. This chip operates the functions of photoreceptors, horizontal cells and bipolar cells. The power dissipation of the chip for instrument measurement is 14.8uW under light intensity of 736 lux. The solar cell area can be reduced to 399920um2 if we increase the light intensity to 5780 lux.
5.1 FURTHER WORKS
In the proposed implantable Pseudo-BJT-based silicon retina, a solution of power supply in artificial retinal prosthesis, using solar cell as power supply, has been proposed. It is compatible with standard CMOS technology. However, the solar cell area occupied large area that reduces the resolution of the artificial retina. Solar cells with higher efficiency are required.
The proposed implantable Pseudo-BJT-based silicon retina replaces the retinal cells, including photoreceptor, horizontal cell, and bipolar cell. It performs image smoothing and edge extraction functions. It breaks the function limitation of current sub-retinal prosthesis. However, there are still some retinal cells not included in this artificial retina. The stimulus signal generated by the proposed artificial retina is monophase while the optic nerve receives the biphasic stimulus. Besides, developing a silicon retina that can process color images is also essential. These will be done in the future. These will be done in the future.
REFERENCES
[1] W. Liu, E. McGucken, K. Vitchiechom and M. Clements, “Dual Unit Visual Intraocular Prosthesis,” Proc. IEEE/EMBS Annual International Conference of the IEEE ,Volume: 5 ,30 Oct.-2 Nov. 1997.
[2] W. Liu, “Retinal Implant: Bridgin Engineering and Medicine,” IEDM Digest, pp.492-495, Dec. 2002
[3] D. Marr, Vision, San Francisco, CA: W. H. Freeman, 1982.
[4] D. Marr and E. Hildreth, “Theory of Edge Detection,” Proc. Royal Soc. London B., 207, pp. 187-217,1980
[5] J. Babaud, A. P.Withkin, M. Baudin, and R. O. Duda, “Uniqueness of the Gaussian Kernel for Scale-Space Filtering,” IEEE Trans. Pattern Anal. And Mach. Intell., Vol. PAMI-8, pp. 26-33, Jan.1986.
[6] P. Perona and J. Malik, “Scale-Space and Edge Detection Using Anisotropic Diffusion,” IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. 12, No. 7, pp.629-639, July, 1990.
[7] A. Rosenfeld and M. Thurston, “ Edge and Curve detection for Visual Scene Analysis,” IEEE Trans. Comput., vol. C-20, pp. 562-569, May, 1971.
[8] A. Yuille and T. Poggio, “Scaling Theorems for Zero Crossings,” IEEE Trans.
[8] A. Yuille and T. Poggio, “Scaling Theorems for Zero Crossings,” IEEE Trans.