2.2 Polarization effect of GaN
2.2.2 Strain-induced piezoelectric and spontaneous polarization
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In case of Ga-face of GaN shown in Fig. 2.5, the spontaneous polarization PSP direction is downward to the substrate. In the other word, the polarization in N-face of GaN in Fig. 2.5 is in opposite direction to Ga-face. In addition, GaN has piezoelectric spontaneous polarization PPE result from the lattice mismatch between AlGaN and GaN. The PPE can be calculated by piezoelectric constants e33 and e31, elastic constants c13 and c 33, and the lattice parameters a0, is given by equation.
(2-1) where a is the lattice constant of GaN along a-axis, and a0 is equilibrium value of lattice constant. (a- a0)/a represents the in-plan strain along a-axis. Since [ ] is less than zero. For AlGaN, over the whole range of compositions, piezoelectric polarization is positive for compressive and negative for tensile barriers. On the other hand, the spontaneous polarization of GaN and AlN is negative. Fig 2.6 shows the directions of the spontaneous and piezoelectric polarization in Ga- and N- face strained and relaxed AlGaN/GaN heterostrucutre.
2.3 AlGaN/GaN HEMTs
2.3.1 Hetero-epitaxial growth of AlGaN/GaN HEMTs
Due to the lack of large-size and low-cost commercial-grade substrate, GaN materials are usually grown on the foreign substrates such as sapphire, Si or SiC.
Table 2.2 shows some of the material properties of these substrates as compared
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to the GaN and AlN layers. Generally, the lattice constants and thermal expansion coefficients of these substrates differ significantly (except SiC) from that of GaN. The first successful epitaxial layer layers of GaN were grown on Sapphire. However, the very large lattice mismatch (14.8%) and the difference in the thermal expansion coefficient between GaN and sapphire substrate cause the huge challenges in the grown of nitrides. As a result of these mismatches, large amount of dislocations are generated in the GaN film. The quality of the GaN film is therefore critically dependent on the ability of the transition layer (buffer layer) used to accommodate the stress generated from these mismatches.
The commonly used buffer layers include low temperature GaN [6-7], AlN [8-10] or their variations [11-13]. Dislocations generated in GaN are mainly screw, edge and mixed TDs. In addition to the buffer layers, other approaches are also used to improve the crystal quality of GaN film such as the insertion of AlN interlayers [14] or Si delta-doping layer [15].
High crystalline quality GaN materials are usually grown by metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) methods. MOCVD is famous for growing the LED-quality GaN and is also used to grow GaN materials for HEMT applications lately. The main advantages of MOCVD, as compared to MBE, are the high growth rate and high crystal quality even for the direct growth of GaN layers on the foreign substrates.
Besides, MBE has also proven to be a promising technique to grow GaN materials for HEMT devices application [16-18]. The benefits of growing GaN by MBE include real-time monitoring of crystal growth with reflection high-energy electron deflection (RHEED), a carbon-free and hydrogen-free growth environment, a smooth surface, sharp interfaces and low point defect density. These attributes are important for achieving high quality materials for
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HEMT devices. Table 2.3 lists some important developments on the electrical properties of AlGaN/GaN structure grown by MOCVD and MBE techniques.
Although these difficulties have been solved, the low thermal conductivity is still an unneglectable problem. Compared with sapphire, SiC has less lattice mismatch (4%) with GaN and very good thermal properties, which is nearly 10 times more than that of sapphire. Therefore, SiC is rather popular substrate. Yet, SiC is too expensive for commercialization. Recently, GaN HEMTs grown on Si substrate was been widely investigated due to lower material cost and compatible with Si technology for circuit integration.
2.3.2 The Basic Structure and Operation of AlGaN/GaN HEMTs
GaN materials for HEMT fabrication consists of a higher bandgap material, such as AlGaN [19] or AlInN [20], grown on the top of the GaN film as the barrier layer. The discontinuity in conduction bands between the two materials forms a 2-dimentional electron gas (2DEG) channel at the hetero-interface.
Basic GaN HEMT structure and band diagrams are shown in Fig. 2.7.
AlGaN/GaN HEMT 2DEG formation is totally different from GaAs HEMT. In AlGaAs/GaAs HEMT, the channel electrons come from the surface states in the AlGaAs. The electrons in the AlGaAs where driven into the GaAs layer, because the hetero-junction created by different band-gap materials. The formation mechanism of GaN HEMT 2DEG is due to the strong polarization effect and large amount of surface states. High electron density (~1.5x1013 cm-2) can be induced at the 2DEG by AlGaN barrier layer with Al~25%, and high electron mobility (~2000 cm2/V*s) can be achieved on an AlGaN/GaN heterostructure. Therefore, AlGaN/GaN HEMT does not require intentional
11
doping in the barrier to provide carrier in the 2DEG channel. The 2DEG enables better electron confinement and less carrier scattering. Due to both high mobility and high carrier density, AlGaN/GaN HEMT device of high current density (>2 A/mm) has been demonstrated [21].
2.3.3 Issues of High Gate Leakage Current AlGaN/GaN HEMTs
Despite the impressive device performance, the potential of AlGaN/GaN HEMTs for commercial application have not been fully realized as yet. The RF power expected from fundamental nitride material properties significantly exceeds the experimental data. One of the key problems limiting the HEMT RF power is the high Schottky-gate leakage current, which results in the degradation of DC/RF parameters. At positive gate bias, high forward gate current can shunt the gate-channel capacitance, thus limiting the maximum drain current. At negative gate bias, high voltage drop between the gate and drain results in premature breakdown and the maximum applied drain voltage is restricted [22].
In addition, gate leakage currents increase the device sub-threshold currents, which decrease the achievable amplitude of the RF output. All these limitations become even more severe at high ambient temperatures. Mechanisms of the high gate leakage current in AlGaN/GaN HEMTs have been investigated and possible solutions to suppress the leakage have been explored in the past few years. Through numerical simulations and DC electrical measurements, Miller et al. reported, found that vertical tunneling through the gate area is the dominant mechanism for gate leakage in AlGaN-barrier HEMTs, while additional leakage current mechanisms such as lateral tunneling and defect-assisted tunneling also contributed to the total gate leakage [23]. To suppress the high gate current,
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Miller et al. proposed an enhanced-barrier HEMT structure, in which a GaN cap layer was grown on the top of the standard AlGaN barrier. Owing to the strong polarization effects in the nitrides, the peak barrier height in the new GaN/AlGaN/GaN HEMT was increased, thus decreasing the tunneling gate leakage current. Mizuno et al. compared the gate leakage current of a GaN-based HEMT with a GaAs-based HEMT [24]. They observed both a two to three orders of magnitude larger gate leakage of the GaN-based HEMTs as compared to that of the GaAs-based HEMTs, and the temperature-independence for the gate leakage current in GaN-based HEMTs. Considering that AlGaN has a larger Schottky barrier height (1.4 eV) than GaAs HEMTs (~1.0 eV), the authors attributed tunneling to be the main leakage mechanism instead of the thermionic emission. They also found that surface treatment with CF4 plasma prior to the gate metal deposition was able to reduce the gate leakage current by two to three orders of magnitude. A possible explanation of such leakage suppression is that the plasma treatment introduces deep acceptors to compensate the high-density positive charge on the AlGaN surface. Thus, the depletion layer thickness under the gate increases, and gate leakage current due to electron tunneling becomes small.
2.4 AlGaN/GaN MOS HEMTs
2.4.1 Introduction
As described above, device performance of conventional Schottky gate AlGaN/GaN HEMT device suffers from high gate leakage current. As a result,
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the drain current collapse when operating at high-frequency and poor long-term reliability of Schottky gate. In order to reduce the gate leakage current, a concept of high-k insulators layers between gate metal and semiconductor were investigated in the past years. A schematic comparison between HEMT and MOS-HEMTs for AlGaN/GaN is illustrated in Fig. 2.8.
2.4.2 The requirements of high-k insulators oxide
(A) Insulator constant
Insulator constant is the most important parameter for oxide material used in the MOS structure. Due to the reduction of chip’s size in the future, the horizontal electrical field is increased and the gate modulation ability is decreased. In order to solve these problems, the capacitance per unit area must be improved to decrease the effect of undesired electrical field.
(2-2) where C is capacitance, Q is charges, and V is turned on voltage.
, ε ן C (2-3) where ε is the insulator constant of oxide, A is cross section area, and d is the distance between the two plates. According to Eq. (2-2), the devices with larger accumulation capacitance can be turn on more easily by a smaller voltage. Using smaller operating voltage will result in higher device efficiency and cost saving.
According to the Eq. (2-3), the MOS device which using oxide material with larger insulator constant as its gate insulator will have larger accumulation capacitance. So, the high-k oxide is desired for III-V MOS devices technology.
The energy band gap versus insulator constants of different oxide materials is
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plotted depicted in Fig. 2.9.
(B) Energy band gap
The energy band gap of oxide materials is an important factor which influences the leakage current of the MOS devices. The oxide with smaller energy band gap causes the carrier tunneling more easily; it will induce undesired leakage current and influence the devices performance. The oxide with larger energy band gap can prevent the carriers tunneling. But, the oxide with higher insulator constant will have the smaller energy bandgap. So, it is important to find the suitable oxide to improve the MOS devices performance.
Several gate oxide candidates are listed in Table 2.4. Besides, the band offset of oxide on semiconductor material is also needed to be considered, the value must exceed 1 eV so that the oxide can serve an effective insulator [18].
ALD Al2O3 is introduced in this study due to its relatively high band gap (about 8.7 eV) and remains amorphous under typical processing conditions. In addition, Al2O3 also possesses high breakdown electric field (5~20 MV/cm), high thermal stability (up to 1000℃) and strong adhesion with dissimilar materials [25]. With well-controlled thickness and uniformity for the Al2O3 layer deposited by ALD technology by the good insularity of Al2O3 layer, ALD Al2O3 is the leading candidate for the gate insulators in MOS-HEMT device.
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Table 2.1 Advantages of GaN material for electronic applications.
Material property Advantages Wide bandgap
3.42 eV
Great endurance for high device operating temperature
Suitable for high power applications.
Working under high temperature environment +High breakdown field
4×106 V/cm
Larger power density
High thermal conductivity
~1.3W/cm* K
Better heat dissipation, enhanced device performance
Easier device packaging High saturate electron velocity
~2.7×107 cm/sec
Suitable for high frequency applications
Table 2.2 Material properties and figure of merit (FOM) of GaN, 4H-SiC, GaAs and Si at 300K for microwave power device applications. All FOMs are normalized with respect to those Si.
Material Bandgap
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Table 2.3 Comparison of 2DEG mobility and sheet carrier concentration of AlGaN/GaN structure grown by MOCVD and MBE on different substrates. The carrier mobility and concentration are measured at 300, 77, 4.2 or 0.3 K unless specify in the bracket; x is the Al content in AlGaN layer.
Growth
Method substrate
Al content
2DEG mobility (cm2/Vs)
(Sheet carrier concentration (ns (cm-2)) Reference x 300K 77K 4.2K 0.3K
Higashiwaki et al., (2008) [24]
Sapphire 0.18 10300 (1.5K)
(6.9×1012)
Selvaraj et al., (2009) [28]
Silicon 1800
(1×1013)
Arulkumaran et al., (2010) [29]
Sapphire 0.19 1500 (9×1012)
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Table 2.4 Comparison of the gate oxide’s properties
Fig. 2.1 Band gap (Eg) versus lattice constant at 300 K for wurtzite (α-phase) and zincoblende (β-phase) GaN, InN, and AlN. The right-hand scale gives the light wavelength, corresponding to the band gap energy.
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Fig. 2.2 Semiconductor materials for RF applications.
Fig. 2.3 Electron drift velocity of GaN, SiC, Si and GaAs at 300 K computed using the Monte Carlo technique.
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Fig. 2.4 Schematic drawing of the crystal and energy band structure of wurtzite GaN and Zinc Blende GaN.
Fig. 2.5 Schematic of the crystal structure of wurtzite Ga-face and-face GaN.
The spontaneous polarization (Psp) direction is also shown.
Psp
Psp
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Fig. 2.6 Polarization induced sheet density and directions for the spontaneous and piezoelectric polarization in Ga- and N-face AlN/GaN heterostructures.
Fig.2.7 Basic structure and its band diagram AlGaN/GaN HEMT.
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Fig. 2.8 Structure comparisons between AlGaN/GaN HEMT (on the left) and Al2O3 HEMT (MOS-HEMT) (on the right).
Fig. 2.9 Energy band gap versus Insulator constant diagram of oxides.
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Chapter 3
Experimental Methods of AlGaN/GaN MOS-HEMTs with Al
2O
3High-K Gate Oxide
The fabricated AlGaN/GaN MOS-HEMT with Al2O3 high-k gate oxide in this study brings together a novel design to enhance the electronic properties of the devices, the process flow of AlGaN/GaN MOS-HEMT with Al2O3 high-K gate oxide fabrication in this study includes several steps as shown in Fig 3.1, and they are:
1. Ohmic contact formation
2. Active region definition (Mesa isolation) 3. Atomic layer deposition (ALD) Al2O3 4. Gate formation
3.1 Ohmic Contact Formation
An ohmic contact is a low resistance junction formed in between metal and semiconductor. The purpose of an ohmic contact on semiconductor is to allow the electrical current to flow in and out of the semiconductor. A good ohmic contact is important for a better device performance such as lower power consumption, low noise and so on. An ohmic contact should obey the ohms law;
that is, it should have a linear I-V characteristic either under forward or reverse bias. Therefore, to obtain a low resistance ohmic contact, we have to create a
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heavily doped interface between metal and semiconductor. In addition, an ohmic contact not only should be stable over time and temperature, but also should have as small resistance.
First, the negative photoresist AZ5214E and I-line aligner were used to define the ohmic metal pattern after wafer cleaning by using ACE and IPA. Unlike the Si-based devices, the lift-off process is used for III-V based device because of the lack of appropriate etching selection between ohmic metals and III-V materials. The undercut profile of the negative photoresist AZ5214E will benefit the metal lift-off process. Then, the wafers underwent O2 plasma descum to remove residual photoresist and the dipped in HCl:H2O (1:4) solution for 15 s to remove the native oxide on the GaN surface before Ohmic metallization. ohmic metal was composed of Ti/Al/Ni/Au from the bottom to the top, and it was deposited by e-gun beam evaporation system. Finally, tcontacts were annealed by rapid thermal annealing (RTA) at 850℃ for 30s in N2 atmosphere after metal lift-off process as shown in Fig 3.1. The specific contact resistance was checked by the transmission line method (TLM) in the process control monitor (PCM). It containing a linear array of metal contacts with various spacings between them.
The distances between TLM electrodes are 3 μm, 5 μm, 10 μm, 20 μm, and 36 μm, respectively in this study. In general, the typical measured contact resistance must be less than 1 x 10-5 Ω-㎝2.
3.2 Mesa isolation
For III-V devices, the mesa isolation is to isolated devices from each other. In these specific areas, the current flow is restricted to the desired path. In addition,
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parasitic capacitance, parasitic resistance, and leakage current can all be reduced with effective isolation. A successful isolation provides sufficient insulating area to form passive elements such as transmission lines, capacitors, pads, etc.
First, the active areas were masked by Shipley S1818 photoresist, and then the dry etch process was conducted by inductive couple plasma (ICP) with Cl2 in Ar ambient. After the dry etch process, the etching depth should reach the buffer layer as shown in Fig 3.3. Finally, the photoresist was striped by ACE.
According to the device structure, the mesa was etched to the buffer layer to provide good device isolation. Finally, the etching depth was approximately 2500Å measured by p-10 surface profiler after the strip of photoresist, and the etching profile was carefully checked by scanning electron microscopy (SEM).
3.3 Atomic layer deposition (ALD) Al
2O
3In this study, the Al2O3 was deposited by ALD system. ALD developed in Finland by T. Suntolan in 1974, and this method is considered as an advanced variant of the CVD technique.
Before the Al2O3 deposition, the chemical surface treatment was used to remove the surface native oxides. Firstly, the wafers were immersed by HCl : H2O (1:4) solution to remove the native oxides, and followed by rinsing in the water for 30 s and blowing dry by N2 gas. Then, the wafer was directly immersed in (NH4)2S solution for 15 min at room temperate, and also rinsed for 30 s in water and blown dry by N2 gas after (NH4)2S treatment. After the chemical surface treatments, the wafer was loaded into the ALD chamber. The Al2O3 films (TMA/N2/H2O/N2 with periods of 0.2s/5s/0.2s/5s) were deposited
25
over 50 cycles and the thickness Al2O3 was about 10 nm as shown in Fig 3.4.
Finally, the post deposition annealing (PDA) was used to improve the interface quality. The PDA was performed at 400℃ for 5 min in N2.
3.4 Gate Formation
Schottky barrier gate is one of the most important elements of the HEMTs.
Both the dimension length and placement of the gate are very critical. For high speed and high frequency applications, short gate length is desired. Decreasing gate length (Lg) can increase the electronic field under the gate so as to accelerate the transport property of channel electron.
In this study, the 1.5 μm gate length was defined by AZ 2020 photoresist, and then the remnant photoresist was removed by ICP with Ar and O2 ambient.
Beside, the wafer was dipped into the HCl:H2O (1:4) solution for 15 s to remove the negative oxidation before the gate metal deposition. Here, the multilayer gate metals Ti/Pt/Au were deposited by the e-gum system. Finally, the wafer was immersed into the ACE for 30 min to lift –off the undesired metal, and the ICP was used to clean the wafer as shown in Fig 3.5.
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Fig. 3.1 the whole wafer
Fig. 3.2 Ohmic contact formation
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Fig. 3.3 Mesa isolation
Fig. 3.4 Atomic layer deposition (ALD) Al2O3
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Fig. 3.5 Gate formation
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Chapter 4
Fundamentals of Electrical Characteristization
After the device fabrication, DC and RF performances of the AlGaN/GaN HEMT and MOS-HEMT were evaluated by using on-wafer measurement. For the DC measurement, the I-V characteristics were obtained by using an HP4142B Modular DC source/monitor and SUSS PA200 semi-auto probe station. The TLM method was used for determining specific contact resistance was by the 4-wires measurement. The S-parameters were measured by HP8510XF vector network analyzer using on-wafer GSG probes from Cascade MicroTech. However, evaluating the RF behaviors of a device on a wafer was a complicated process. For conventional RF measurement of a packaged device, the wafer needs to be diced and then an individual die should be mounted into a text fixture. Discriminating between the die’s and the fixture’s responses became an issue. Furthermore, fixturing die was a time-consuming process, making it impractical for high-volume screening. On-wafer RF characterization can simplify the process [26].
The method of characterization of the AlGaN/GaN HEMT and MOS-HEMT devices are stated in the following section. In this study, de-embedding which must also be performed to obtain the true RF performance of the device is also performable.
4.1 DC Characteristics Measurment [27]
Before RF performance analysis, DC measurement was performed to