OUTLINE
8.0 Introduction………..
8.1 Pulse-IV Technique and Setup………
8.2 Transient Tunneling Currents of Capacitors………
8.2.1 SOS Capacitor…...……….………….……..…..……..
8.2.2 SNS Capacitor……..………..………..……….……….………
8.2.3 SONS Capacitor……..…………..………..………..……….…….……
8.2.4 Area and Temperature Dependence………..………..……..……….…….
8.2.5 SONOS Capacitor……..…………..………..………..……….…….……
8.3 DC and Transient Characteristics of Transistors………..……….……
8.3.1 DC-IV Characteristics…...……….………….……..…..
8.3.2 Pulse-IV Characteristics……….……….……….……..….
8.4 Applications in Quasi-Non-Volatile Memory……..……..………..……….………
8.4.1 Program/Erase Transient Characteristics...……….…………..
8.4.2 Endurance Characteristics……….……….….
8.4.3 Retention Characteristics……….……….……….….
8.5 Summary………..……….…
172 172 173 173 173 174 174 175 175 176 176 177 177 178 178 179
8.0 Introduction
Charge-trapping (CT) devices have gained great attention in non-volatile memory applications. However, it is hard to monitor the “real” trapped charge behaviors using conventional DC-IV measurement, especially for the memory with serious hysterisis.
Recently, pulse-IV techniques have been developed to characterize traps in high-k gate dielectrics of CMOS logic devices [8.1-8.4], and they mainly deal with drain current transient response and fast NBTI behaviors. However, few studies talked about the applications on SONOS-type memory.
In this chapter, we developed a memory-like operation with program/erase pulses, together with reading immediately after P/E or concurrently with the applied pulses. The transient tunneling current, fast program/erase/read operations, and fast retention relaxation can be accurately characterized. Using this new technique we have studied the transient behaviors of SONOS-type devices exhaustively. This new characterization method also opens a new pathway to study quasi-non-volatile memory for new applications.
8.1 Pulse-IV Technique and Setup
We designed different pulse-IV setup for characterizing large area (500µm × 500 µm) capacitors (n+ source/drain, p-well, and p+ poly gate) and small dimension (L ~ 50nm and W ~ 0.2µm) transistors.
The pulse-IV setup for transistors is shown in Fig. 8.1(a). The pulses are applied to the gate (VG) and drain (VD) while source current is measured immediately after P/E. The source current (IS), which is nearly equal to drain current (ID), is converted to voltage signal by using a fast current to voltage amplifier. Arbitrary waveforms can be generated to design any specific program/erase/read sequence. The oscilloscope can simultaneously collect VG and ID
waveforms.
For capacitors, the pulse-IV setup is shown in Fig. 8.1(b). The pulse is only applied to
gate while the drain, source, and body are connected together (capacitors in this study are fabricated with source/drain and body contacts). The total current of source, drain and body is then measured by the oscilloscope.
Detailed cable connection, shielding and impedance matching are carefully arranged to eliminate spurious responses.
8.2 Transient Tunneling Currents of Capacitors
In this section, we first discuss the transient tunneling currents of various capacitors, including SOS, SNS, SONS, and SONOS. In addition to investigate gate voltage and pulse width dependence, we also examine the area and temperature dependence. Therefore, the detailed transient charging behaviors of various SONOS-type capacitors will be discussed extensively.
8.2.1 SOS Capacitor
We first measured transient tunneling current of SOS (25Å) capacitor for a reference and calibration, as shown in Fig. 8.2. This standard gate oxide capacitor with no trapping layer shows no spurious response for various gate voltages (Fig. 8.2(a)) and pulse widths (Fig.
8.2(b)), indicating that our setup does not generate detectable noise. Figure 8.2(c) also shows the corresponding band diagram under +VG operation. Both substrate electron tunneling current and gate hole tunneling current contribute to total tunneling current.
8.2.2 SNS Capacitor
Next, we measured the transient tunneling current behavior of SNS (133Å) capacitor, which does not have B.O. and T.O., as shown in Fig. 8.3. The tunneling current is initially high but then gradually decreases and saturates. The transient behavior is independent of pulse width (Fig. 8.3(b)), and similar for all gate voltages (Fig. 8.3(a)). The pulse width
independence suggests a transient behavior, such as trapping. A reasonable explanation is that during the tunneling current measurement, some electrons are trapped in the bottom portion while holes are trapped in the top portion of the nitride (section 4.1.3). Therefore, the substrate electron tunneling current decreases as electrons are trapped near the bottom portion of the nitride while gate hole tunneling current also falls at the rate of hole trapping in the top portion of the nitride (the corresponding band diagram is shown in Fig. 8.3(c)). The decreased substrate electron tunneling current and gate hole tunneling current result in decreased transient tunneling current.
8.2.3 SONS Capacitor
The transient tunneling current of SONS (54/114Å) capacitor is shown in Fig. 8.4.
Interestingly, it behaves quite differently from the SNS. The tunneling current gradually increases and then saturates. Even though there is no T.O., we still expect the tunneling current of SONS comes mainly from electron tunneling from the substrate. On the other hand, because there is substantial gate hole injection, some hole trapping occurs (section 4.1.3). This hole trapping leads to enhanced electron tunneling and in turn increases transient tunneling current. Figure 8.4(c) shows the corresponding band diagram.
8.2.4 Area and Temperature Dependence
We have successfully demonstrated that the transient behaviors of electron/hole trapping can be directly monitored by our pulse-IV technique. In order to further confirm these transient behaviors we also investigate the area and temperature dependence of SNS and SONS, as shown in Fig. 8.5. For the area dependence (Fig. 8.5(a)), in order to fairly compare the Itotal is normalized to area (Jtotal = Itotal/area). We find that all transient tunneling currents of different area almost merge together, implying that these transient behaviors are independent of area. For the temperature dependence (Fig. 8.5(b)), the increased temperature enhances the
tunneling current but the transient behaviors are almost the same. Therefore, we further demonstrate that our pulse-IV technique can be adequately used to monitor the “real” charge transient behaviors.
8.2.5 SONOS Capacitor
The transient tunneling current of SONOS (54/77/50Å) capacitor is shown in Fig. 8.6.
Figure 8.6(a) shows that the CV curve has a large shift owing to the trapped charges. Contrary to SNS and SONS, the transient tunneling current rises initially but then drops sharply and decreases to almost zero. This very different transient behavior (from SNS and SONS) may be explained by the T.O. in SONOS. The T.O. greatly reduces gate hole injection and thus allows the accumulation of trapped electrons in the nitride. In turn the trapped electrons suppress the tunneling current eventually. On the other hand, both SNS and SONS have simultaneous gate hole injection that limits the trapped electron density. As a result, the tunneling current of SNS and SONS is not limited.
Previously, we have shown that SONOS with thicker nitride (>70Å) exhibits high capture efficiency characteristics [5]. Therefore, we used the theoretical model (based on the fully captured assumption) shown in Table 2 to simulate the transient behavior of SONOS (54/77/50Å). Figure 8.6(b) shows that the experimental Itotal can be well fitted by using reasonable parameters (φB = 3.1eV and mox = 0.5m0). This result further supports that SONOS with sufficient nitride thickness indeed can capture most of the injected electrons.
From above results, we find that the transient tunneling currents are strongly related to the detailed charge trapping behaviors as well as the device structures.
8.3 DC and Transient Characteristics of Transistors
After discussing the transient tunneling currents of various capacitors, we next investigate the DC and transient characteristics of small area transistors. For the practical