BASIC OF SONOS-TYPE MEMORY
2.4 Trapped Charge Location Characterization
After understanding the basic equations, models, and carrier transport mechanisms, we will briefly introduce some studies on trapped charge locations of SONOS-type devices for both lateral and vertical directions. Since the trapped charge behaviors determine the characteristics of SONOS-type devices, a deep knowledge of trapped charge distribution is critical for program/erase bias optimization, reliability predictions, and future technology scaling.
2.4.1 Trapped Charge Lateral Location
Some SONOS-type devices use CHE injection for programming and BBHH injection for erase. In these devices, one of the important parameters is the lateral trapped charge profile, which must be determined accurately to predict the overlap of electron/hole profiles during
programming/erasing and the minimum possible gate length for 2-bit storage. Therefore, there have been many works studying the trapped charge lateral profile so far.
H. Pang et al [2.18-2.20] and L. Sun et al [2.21] proposed a new charge pumping (CP) method, which combines both CVb method: constant Vb (the base level of the gate pulse) and CVh method: constant Vh (the high level of the gate pulse) to obtain the more precise distribution of injected charges. The standard CP measurement setup is shown in Fig. 2.11(a) [2.22], where the pumping pulse is applied to gate, and the charge pumping current (Icp) can be measured from drain or source side with source or drain floating. For the VT profile of a CHE programmed charge trapping (CT) memory, as shown in Fig. 2.11(b), where four regions marked are consistent with the Icp curves measured by CVb and CVh methods, as shown in Fig.
2.11(c) and (d), respectively. Since only the lower Icp provides the more precise data, combining two methods could acquire the most complete and reliable trapped charge lateral profile. The extracted equations are shown below.
,max
( )
cp h
cp
LI V
x= I (2-51)
1 cp h
ntr
h
d I dV
N qfW dV dx
= ∆ (2-52)
where f means the frequency of the pulse, W refers to the effective channel width, L is the channel length, and Nntr is the trapped charge density in nitride. By replacing Vh with Vb, the above equations can be used in CVh method to get the Nntr curve. Using this new method, they studied the CHE program as well as the BBHH erase of SONOS devices. The program/erase charge profiles and the redistribution for different reliability issues were also discussed extensively. However, the Icp is very sensitive to interface/near interface trapped charges, and this spurious Icp cannot be easily eliminated, especially for the post-damaged devices.
Therefore, other methods should be introduced to decompose the contribution of interface/
near interface trapped charges.
P. R. Nair et al [2.23] and P. B. Kumar et al [2.24] put non-uniform trapped charges (maximum near the gate edges, decreasing gradually towards the center of channel) in device simulators and simulated the linear I-V (LIV) and sub-threshold I-V (SIV) of SONOS devices, as shown in Fig. 2.12. They found that for the charges are placed on rectangular packets from the gate edge (Fig. 2.12), channel charges degrade VT and S.S. (sub-threshold slope) while overlap charges degrade the linear slope of ID-VG curves, but do not affect SS significantly.
Compared with CP measurement and Monte Carlo simulation, they announced that they could accurately determine the trapped charges in gate/drain overlap and channel (near the drain junction). Nevertheless, their method needs complex device simulation, where the detailed device structure and doping profile should be given. Moreover, the I-V curve is very sensitive to the device geometry such as STI effect. Therefore, the geometry effect should be taken into account.
L. Avital et al [2.25] and A. Padovani et al [2.26] also utilized similar method to investigate the temperature effects on ID-VG curves as well as the hole injection for erase.
However, their method suffers from the same issues as previous method sine they also needed to simulate the ID-VG curves.
2.4.2 Trapped Charge Vertical Location
For the SONOS-type devices which are operated by uniform charge injection, the trapped charge vertical location is more meaningful than lateral location. For example, the NAND Flash, which is the main memory product of the market today, uses uniform FN program and erase. Therefore, there have been a large number of papers investigating the trapped charge vertical location.
E. Suzuki et al [2.27] compared the maximum flat-band voltage shifts (∆VFBmax), which is extracted from CV hysteresis measurement, of various MONOS (metal-oxide-nitride-oxide- semiconductor) capacitors with different fractions of nitride conversion (γ). From the
relationship between ∆VFBmax and trap density, they could further extract the trap density.
where the TN is the initial nitride thickness, α is the volume ratio of oxide to nitride, β is the ratio of dielectric constant of nitride to oxide, γ is the fraction of the nitride converted by oxidation, Nt is the trap density which is assumed to be uniformly distributed in the nitride layer, and Non is the trap density which is assumed to be created at the T.O./nitride interface.
By comparing the theoretical calculation with the experimental results for different TN, as shown in Fig. 2.13, they concluded that the electrons are mainly trapped at the T.O./nitride interface, and the number of traps is insensitive to TN while the bulk trap density could be almost ignored. In this method, the trap density of various MONOS capacitors is assumed to be the same. However, the ∆VFBmax of a capacitor is also a function of applied voltage, thus these results may be equivocal. Moreover, they used MNOS sample to extract the bulk trap density. However, since the MNOS devices do not have T.O. to block the external charge injection, in these devices the gate injection is considerable. That would cause underestimated bulk trap density and wrong results.
T. Ishida et al [2.28] also compared the saturated flat-band voltage shifts (∆Vsat) of various MONOS capacitors. They used a special avalanche charge injection [2.29] to inject the electrons, therefore, in their devices the impurity concentration of Si-sub should be controlled by ion implantation to the order of 1017cm-3. They assumed three trap regions in the MONOS structure: (1) Ntop: at the T.O./nitride interface (top interface), (2) NSiNbulk: in the bulk nitride, and (3) Nbottom: at the nitride/B.O. interface (bottom interface), as shown in Fig.
2.14(a). They also assumed that trap distributions in these three regions were uniform. Under these assumptions, the ∆Vsat can be expressed as
0 0
2
0 0 0 0 0
( )
2
top SiNbulk top top top bottom
SiNbulk bottom
However, in Eq. (2-54) there are three variables needed to be solved. In order to diminish the fitting error, three parameters are estimated in two steps. First, they estimated NSiNbulk and Nbottom by using MNOS capacitors. In these devices, xSiN is varied by substituting zero for Ntop
and xtop in Eq. (2-54).
Second, they took the results of MNOS capacitors into consideration to analyze the MONOS capacitors and to estimate the Ntop. By comparison of MNOS and MONOS capacitors with various film stacks, as shown in Fig. 2.14(b) and (c), they also concluded that the electrons are mostly trapped at the interfaces of nitride and oxide while bulk electron traps are negligible. However, this method suffers from the same issues as previous method. Moreover, the fitting of experimental data is artificial, and the results obtained under a special operation may not be practical.
The above two methods only gave an estimation of saturated trap density but not the trapped charges under practical operations. The limitation of above techniques originates from the difficulty of finding both the total trapped charge density (Q) and the mean vertical location (x) using only one equation. Therefore, another equation must be added to solve for both variables.
M. H. White et al [2.30-2.32] proposed a linear voltage ramp technique, which simultaneously measured the flat band voltage shifts (∆VFB) and the injected charges at different terminals. The measurement system is illustrated in Fig. 2.15, where the linear voltage ramp with a symmetrical triangular form is applied to gate, and the source/bulk currents are measured by electrometers, and are recorded simultaneously as a function of gate voltage. Based on the measured currents (shown in Fig. 2.16) and ∆VFB, the charge centroid can be further extracted from the slope of ∆QN vs. ∆VFB curves.
[ / ( ) / ]
FB N TOX OX N N
V Q T ε T x ε
∆ = −∆ + − (2-56) where ∆QN is the charge per unit area in the nitride, x is the charge centroid measured from the B.O./nitride interface. They concluded that for SONOS/MONOS devices the charge centroid is deep into the nitride layer at lower injection levels and then moves toward the center of nitride as the injection level is increased.
A. Arreghini et al [2.33-2.34] also proposed a method to directly measure the injection current during DT programming/erasing for a capacitor. For a SONOS device shown in Fig.
2.17(a), where xC denotes the centroid of the trapped charges measured from the T.O./nitride interface, the threshold-voltage shift (∆VT) caused by the charge QN (uniformly injected over the device with an area = A) can be calculated as
0 nitride thickness, respectively. Therefore, if ∆VT and QN are known, the xC can be determined by holes can be detected at bulk termial, carrier-separation technique can be well performed. On the other hand, in order to eliminate the displacement currents from the overall current integration, an accurate QN measurement with three-level shapes (Fig. 2.17(b)) should be required. Therefore, a complex setup should be needed. They found that the charge centroid is located at the center of nitride, and it is quite insensitive to the program/erase conditions and the gate-stack compositions.
In this method, they also assumed that the injection current is fully captured by SONOS
devices, but it is not practical. Moreover, the xC in Eq. (2.58) is proportional to 1/QN, therefore, the small error QN in will result in incorrect xC. Moreover, the injection current during DT programming/erasing is a fast transient response (~ µsec), which is difficult to measure accurately. On the other hand, this method cannot be applied to the long-term retention test because the de-trapping current is too small for detecting. These limitations greatly affect the accuracy of this method.
H. T. Lue et al [2.35] proposed a simple transient analysis method to characterize the trap vertical location. This method required only measuring the time dependence of gate injection at various gate voltages on “single” sample. Then, the transient current (J) and the instantaneous T.O. e-field (ETox) can be directly obtained based on various cases of trap location. Comparisons can be made to check which case has the best consistency for the J vs.
ETox behaviors. The only assumption in this method is that the J vs. ETox should follow a consistent tunneling relationship at different gate voltages. The experimental results showed unequivocally that electrons are trapped at the interface between T.O. and nitride for oxide grown by thermal conversion, as shown in Fig. 2.18(a). However, for the direct-deposited T.O.
(HTO) the electrons are close to the center of nitride, as illustrated in Fig. 2.18(b). Although this method is a simple and convincing tool to detect the nitride trap vertical location, it is only suitable for gate-injection operated SONOS-type devices. That is because for the channel-injection operated SONOS-type devices the B.O. e-field (EBox) is independent of the trapped vertical location. Therefore, comparing different vertical location assumptions becomes invalid.
In this dissertation, we proposed an accurate and unequivocal way to solve the above difficulties. We introduced an additional gate-sensing (GS) capacitor to be compared with the conventional channel-sensing (CS) one. This GSCS method provides two equations to solve total trapped charge density (Q) and mean vertical location (x) simultaneously. Only simple CV measurement is required, and there is no complicated setup or noise compensation.
Moreover, we also provided an effectively “real-time” measurement method since Q and x can be tracked directly during programming/erasing and retention testing. Both channel-injection and gate-injection operated SONOS-type devices can be investigated successfully. In the next chapters, we will discuss this GSCS method in detail.
B
Fig. 2.1 (a) Storage principle of non-volatile memory devices can be simplified as the charges (QT) are trapped in the gate insulator of a MOSFET. (b) Influence of trapped charges in the gate insulator on the threshold voltage (VT) shift of a MOSFET.