Summary

In this chapter, works on MIS solar cells with p-Si have been discussed at different cases. From the data shown above, post-oxidation annealing in hydrogen atmosphere is a must for cells with sputter oxide due to the high defect density in film. Although film quality can be modified by post annealing, the thickness and sputtering working pressure are also key factors in MIS solar cells, and the best case is sputtered 160s with RF power 50W and working pressure 20mTorr. Finally, we change the thin collecting metal thickness and analyze its properties; cells with aluminum thickness 10nm in our structure have highest efficiency. Although there is only a slightly enhancement in Voc

with decreasing metal thickness from 15nm to 10nm, higher efficiency because of higher Jsc do help the performance of MIS stacked solar cells.

solar

4.1 Photovoltaic Properties with Annealing Process

In p-type MIS solar cells, post-oxidation annealing is necessary to get good photovoltaic characteristics (Fig 3.1 and Table 3.1), so the same annealing process annealing at 500 for 1hr in hydrogen atmosphere is also done. Better photovo℃ ltaic characteristics as shown in Fig4.2 after H-annealing are obtained without doubt.

Different from p-type MIS solar cells, the cell with no treatment has a not bad fill factor 50.7%, still lower than that with H-annealing though. With C-V analysis (Fig.4.3), the curve drop of as-dep. sample at accumulation region is not as much as that of p-type sample, so n-type MIS solar cells without annealing have better photovoltaic properties.

After H-annealing process, though the curve still has a small drop at accumulation region, the right shifted curve indicates the rise of barrier height due to passivation by the formation of Si-H bonds, and then the Voc after H-annealing increases from 313mV to 422mV. However, this value is still lower than that of p-type cells because of the smaller barrier height mentioned in the beginning of chapter4.

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 -4

0 4 8 12

16

Au 20nm/20mT SiO2 389s/n-Si

Current Density (m A/cm

2

)

Voltage (V)

as-dep.

H-annealing

Fig 4.2: Photovoltaic properties of cells with and without H-annealing

Post Annealing V_oc (mV) J_sc(mA/cm²) FF(%) Efficiency

as-dep. 313 13.4 50.7 2.13%

H2 500℃ 1hr 422 14.4 58.4 3.55%

Table 4.1: Photovoltaic properties of cells with and without H-annealing

-3 -2 -1 0 1 2 3 0.0

0.2 0.4 0.6 0.8 1.0

Au 20nm/20mT SiO2 389s/n-Si

C/ C

max

Voltage (V) As-dep.

H-annealing

Fig 4.3: C-V measurement of cells with and without H-annealing

4.2 Photovoltaic Properties with Different Oxide Thickness

As discussed in section 3.2, insulating thickness is critical for cell efficiency. We change the sputter time to control the same film thickness as what we do on p-type cells.

As shown in Fig4.4 and Table4.2, the tendency from 389s to 778s exhibit lowering tunneling probability and a large voltage drop on thick oxide. The increase in Voc from 160s to 389s can be explained by the increasing Schottky barrier height with the increasing oxide thickness^[18-20] and better interface defect passivation.

The best tunneling oxide thickness of n-type MIS solar cells is sputtered 389s (Fig4.4 and Table4.2), thicker than that of p-type in our work. Try to explain this huge

difference with the transport mechanism, in p-type MIS solar cells under illumination, the majority carrier holes are easily blocked by thin oxide due to lower diffusion constant in Si and minority carrier electrons are tunneling through oxide film to produce light current. On the contrary, in n-type MIS solar cells, majority carriers are electrons which are more difficult to be blocked with higher diffusion constant. Therefore, a thicker oxide is needed in MIS solar cells on n-Si.

-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6

-4 0 4 8 12

16

Au 20nm/20mT SiO2/n-Si

Current density (m A/cm

2

)

VA (V)

160s 389s 583s 778s

Fig 4.4: Photovoltaic properties of cells with varying thickness

Sputter Time (s) V_oc (mV) J_sc(mA/cm²) FF(%) Efficiency

160 295 14.0 54.7 2.25%

389 366 13.4 56.4 2.76%

583 346 11.6 35.9 1.44%

778 320 11.1 22.3 0.80%

Table 4.2: Photovoltaic properties of cells with varying thickness

4.3 Photovoltaic Properties with Different Working Pressure

In Fig. 4.5 and Table 4.3, the tendency of Voc of n-type cells with increasing working pressure is the same as that of p-type. However, in Fig. 4.6, the C-V curves shift is not apparent between 30mT and 40mT, indicating almost the same barrier heights and Voc. However, cells with working pressure 20mT show no rising at point A and steep slope in transition from inversion to accumulation, demonstrating lower defect density in oxide film and interface. Therefore, the Voc of n-type cells with working pressure 20mT reach 422mV, which is the best value in our work, greatly larger than cells with 30mT and 40mT.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 -4

0 4 8 12 16

20

Au 20nm/SiO2/n-Si

Current Density (mA/cm2 )

Voltage (V)

20mT 30mT 40mT

Fig 4.5: Photovoltaic properties of cells with varying working pressure

Pressure (mTorr) V_oc (mV) J_sc(mA/cm²) FF(%) Efficiency

20 422 14.4 58.4 3.55%

30 339 14.7 55.5 2.77%

40 313 14.2 59.9 2.66%

Table 4.3: Photovoltaic properties of cells with varying working pressure

-3 -2 -1 0 1 2 3 0.0

0.2 0.4 0.6 0.8 1.0

Au 20nm/SiO2/n-Si

C/C max

Voltage (V) 20mT

30mT 40mT

Fig 4.6: C-V measurement of cells with varying working pressure

4.4 Photovoltaic Properties with Different Metal Thickness

As discussed in section 3.4, the thickness of metal film is a tradeoff between collection efficiency and reflection. In n-type cells, we use gold as front electrode to form MIS junctions. Since the reflection of gold is different from aluminum, the optimum thickness is also different. As shown in Fig 4.7 and Table 4.4, Jsc reaches about 14.3mA/cm² with 15nm gold film, and keeps no change while increasing to 20nm.

Therefore, an optimum thickness between 15nm and 20nm of gold film on n-type MIS solar cells can be expected. However, there is 40mV difference between 15nm and 20nm, which is not present in p-type solar cells (Fig 3.6 and Table 3.4). This phenomena

A

result from the nickel deposited on the gold film, which lowers the work function of gold while gold is thinner than 20nm. Since the barrier height is lowered by the lower work function, the Voc is reduced.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5

-4 0 4 8 12 16

20

Au/20mT SiO2 389s/n-Si

Current Density (mA/cm2 )

Voltage (V)

20nm 15nm 10nm 5nm

Fig 4.7: Photovoltaic properties of cells with varying thickness of Au film

Metal Thickness (nm) V_oc (mV) J_sc (mA/cm²) FF(%) Efficiency

5 196 0.91 36.6 0.07%

10 329 7.17 40.7 0.96%

15 381 14.3 54.0 2.95%

20 422 14.4 58.4 3.55%

4.5 Summary

In this chapter, n-type MIS solar cells are realized and analyzed with different parameters. The best tunneling oxide thickness is sputtered 389s with working pressure 20mTorr, thicker than that of p-type cells, and this phenomena can be explain with transport mechanism discussed in section 2.2.

As same as the tendency with the change of annealing process, oxide thickness, metal thickness and working pressure, we get the optimum fabrication parameters and achieve the Voc 422mV.

Chapter 5 Experiments of MIS Stacked Solar Cells

5.1 Tunneling Diode 5.1.1 General Description

Tunneling diode also referred as Esaki diode^[21-23], is one of the most important issues affecting stacked solar cell performance. The problem of tunnel junction formation is related to the demand of obtaining uniformly highly doped layer without defects which result in carrier recombination and leakage current in depletion regions.

In a common tunneling diode, degenerate semiconductors^[17,24] are used to increase tunneling probability through depletion region.

E − E = kT ln (Eq. 5.1) E − E = kT ln (Eq. 5.2)

Where Nc and Nv are referred to as effective density of states, n0 and p0 are doping density. From Eq. 5.1 and Eq. 5.2, degenerate semiconductor can obtain with n0 and p0

lager than Nc and Nv.

The current-voltage properties of a tunneling diode is shown in Fig 5.1, different from conventional p-n junction, the I-V curve is ohmic at small voltage while negative differential resistance (NDR) appears with increasing forward bias. The current-voltage characteristic of a tunneling diode can be explained using the band diagram and J-V characteristic shown schematically in Fig 5.1. When a reverse bias is applied, Fig 5.1(a),

current flows by electron tunneling from occupied states on the p-side valence band into unoccupied states in the n-side conduction band. In equilibrium, with no applied bias, shown in Fig 5.1(b), the net tunneling current is zero. With a small forward bias, current flow by electron tunneling gives rise to a peak current Ip at voltage Vp, as labeled in Fig 5.1(c). When the conduction band minimum on the n side is raised above the valence band maximum on the p side, the valley current Iv results at a voltage Vv in Fig 5.1(d).

With further increase in the voltage, the current increases due to tunneling through defect states in the depletion layer and thermionic emission over the diode internal barrier, Fig 5.1(e).

Fig 5.1: Schematic energy band diagram and current-voltage property of tunneling diode with varying bias (From Y. Yan^[25])

In a tunneling diode, the doping profile is key point for the performance^[25-27]. Once an abrupt doping profile is obtained, the resistance at the junction is decreased. In other words, less voltage loss in a stacked solar cell with a higher Voc could be achieved. On the contrary, the broadening of the abrupt doping profiles increases the tunneling diode depletion region and significantly reduces the tunneling probability through depletion region. Consequently, stacked solar cell performance will dramatically be degraded.

With ion implantation, a common way to achieve tunneling diode, the doping profile of junction is hard to control. Therefore, we use direct wafer bonding to realize a good tunneling junction between two MIS solar cells.

5.1.2 Bonding Theorem

Direct wafer bonding generally refers to a process which two cleaned wafers adhere to each other without intermediate medium. If two polished wafers are brought into close sufficiently, attractive forces could pull the two bodies together into intimate contact so that bonds can form across the interface. Nevertheless, the bonding force is too weak that wafer would debond during suffering a small shear force. To strengthen the bonds across the interface, the room temperature bonded wafers have to undergo a high temperature annealing, and then two wafers can adhere to each other permanent.

Direct wafer bonding depends on types of interaction: van der Waals forces,

hydrogen bonds or strong chemical bonds of metallic, ionic or covalent may mediate the adhesion. At room temperature, the attraction between two contacted cleaned wafers is seen as a van der Waals forces or hydrogen bonds^[28]. After the subsequent heat treatment, the chemical bonds will be formed gradually at the interface, increasing the bonding energy.

The bonding energy is determined by substrate, annealing temperature, surface cleaning, and surface treatments and so on. Among these process parameters, surface cleaning is the most important. In the research, a particle with diameter 0.5um makes diameter 2.5 mm unbounded areas, so wafer cleaning in clean-room before bonding is a better way to enhance the yield and bonding quality. In reality, the bonding strength and electrical properties can even close to a bulk material with carful cleaning process and high temperature annealing.

5.1.3 Fabrication of Tunneling Diodes

The fabrication processes of a tunneling diode by direct wafer bonding are listed as follows

(1) Wafer are cleaned with RCA clean (2) Ion implantation at the polished side

(3) Dopants activated with rapid thermal annealing (RTA) 1050 30s℃ (4) Furnace 600 30 min in N2 to reco℃ very implantation damage

5.1

damage, the lower current is attained without doubt. Moreover, the forward bias current is lower than reversed bias current. After furnace annealing, current raises at least two orders at reversed bias and about four orders at forward bias (Fig 5.3), and J-V curves shows no NDR in tunneling diode but a typical characteristic of a diode with large reversed saturation current.

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2

1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Curre nt De ns ity (A/c m2 )

Foward Bias (V)

RTA

RTA+Furnace

J-V Properties of Bonding Junction

Fig 5.3: Current-Voltage properties of bonded samples in dark with and without furnace annealing

To explain these strange J-V properties, we measure the junctions between ion implantation regions and wafers. From Fig 5.4, we can conclude that without furnace annealing, the junctions between ion implantation regions and wafers, corresponding to

n-n⁺ and p-p⁺ internal junctions, dominate the J-V properties and exhibit the opposite trend. With Furnace annealing, junctions vanished due to dopants diffusion and an ohmic curve with large current density are obtained because of defects diminishing.

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2

1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1

Current Density (A/cm2 )

Forward Bias (V)

RTA

RTA+Furnace

Fig 5.4: Current-Voltage properties of single wafer under dark with and without furnace annealing

Although the bonded sample shows no NDR in J-V curve (Fig 5.3), indicating insufficient doping activation or defects in the central junction, the current density reaches 10mA/cm² with 20mV voltage drop, which would only slightly degrade the performance of MIS stacked solar cells. Therefore, we use this junction as the central

junction for MIS stacked solar cells.

5.2 Fabrication of MIS Stacked Solar Cells

To realize a MIS stacked solar cell, we should integrate three different junctions discussed early together. Starting from a bonded sample first, n-type and p-type MIS junctions are fabricated on both sides. However, 4-inch Si wafers has a thickness about 525um, which is thicker than the skin depth of visible light, so the cell on the back side under illumination can absorb light hardly. From point of current matching, net current output would be limited by bottom cell which generates less current. Consequently, a thinning process of bonded sample has to be done before two MIS junction fabrication to increase current in stacked cells. Although bonded sample can suffer mechanical thinning process, huge amount of defects at the surface are produced simultaneously.

Hence, additional chemical etching process is introduced to remove surface defect and thin the wafer at the same time. The fabrication processes of MIS stacked solar cell are listed below:

(1) Bonded samples thinning with sand paper

(2) Dip samples into Si etchant (HF:CH3COOH:HNO3=6:7:20) to remove surface defects and thin the samples at the same time

(3) Deposit tunneling oxide with sputter at both sides

F

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1E-6

1E-5 1E-4 1E-3 0.01 0.1 1 10

100

MIS Stacked Solar Cells (Dark)

no thinning n-thinning p-thinning Current Density (mA/cm2 )

Forward Bias (V)

Fig 5.6: Current-voltage properties of MIS stacked solar cells in dark with (a) no thinning process (b) n-type cell thinning on the top (c) p-type cell thinning on the top

The current-voltage characteristics of MIS stacked solar cells under AM1.5g are shown in Fig 5.7 and Table 5.1. The cell without thinning process exhibits low Jsc

5.25mA/cm² because the current is limited by bottom cell discussed in section 5.2. After thinning the top n-type cell to 50nm approximately, a much higher Jsc 16.5mA/cm² is obtained. However, the large leakage current suppresses the photovoltaic performance and the cell with n-type thinning on the top reaches the Voc 414mV.

Since the cell with p-type thinning on the top reveals a low leakage current, the Voc

would not be suppressed and reaches V 593mV. This value is larger than single

junction MIS solar cells discussed in Ch3 and Ch4, demonstrating the utility of stacked cells. In this structure, the bottom cell is n-type MIS solar cells; the photo current of n-type cells are determined by minority carriers, holes, which have a lower mobility and cannot be collected by electrodes as easily as electrons. Hence, better photovoltaic properties of cells with n-type thinning on the top can be expected.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -4

0 4 8 12 16

20

MIS Stacked Solar Cells (illumination)

Current Density (mA/cm2 )

Voltage (V)

n-type on the top without thinning n-type thinning on the top

p-type thinning on the top

Fig 5.7: Current-voltage properties of MIS stacked solar cells under illumination

Cell Voc (mV) Jsc (mA/cm²) FF(%) Efficiency

No thinning 437 5.25 23.6 0.54%

n-thinning 414 16.5 25.2 1.71%

p-thinning 593 4.74 41.1 1.15%

5.4 Summary

In this chapter, tunneling diode fabrication using direct wafer bonding is realized first. Although the bonded samples show no NDR which should present in tunneling diode, high reversed saturation current diodes are achieved with only 40mV loss while current density reach 10mA/cm². Finally, we integrate n-type and p-type MIS solar cells on bonded sample to realize MIS stacked structure. The Voc of MIS stacked cells reach 593mV, lager than that of p-type and n-type cells, demonstrating that the structure is practical and have its potential to achieve water splitting.

Chapter 6 Conclusion and Future Work

6.1 Conclusion

In this thesis, MIS stacked solar cells are introduced and achieved in order to reach high voltage output.

First, we give general description of the transport mechanism of MIS solar cells in Chapter2. We also study the MIS solar cells on n-type and p-type of substrates in chapter3 and chapter4. The influence of fabrication parameters such as annealing process, tunneling oxide thickness, working pressure and metal thickness on MIS solar cells are investigate. With the best conditions, we get the Voc equals to 475mV on p-type cells and 422mV on n-type cells.

In the beginning of chapter5, we introduce the fabrication of tunneling diode by direct wafer bonding. Although the bonded samples exhibit no NDR at small forward bias, diodes with high reversed saturation current are accomplished and can be used in the MIS stacked solar cells. Afterwards, MIS stacked solar cells are realized by integrating two types of MIS solar cells on bonded samples and best Voc equals to 593mV in our experiment is obtained.

6.2 Future Work

Since best V in our cells is 593mV, lower than theoretic V equals to 0.9V, there

are still many issues to be investigated. First, the voltage drop at the central junction could be lowered by further improving the tunneling current with proper doping activation and defect passivation. Moreover, the thickness of upper cells and bottom cells in stacked cells should be precisely controlled and the current matching could be achieved.

Afterward, in order to enhance the efficiency, Jsc is the important issue to be improved. Surface texturing by chemical etching is a common way to reduce surface reflection while some researches indicate that Voc would slightly decrease. Besides, transparent conductive oxide such as ITO and ZnO can be introduced in our structure with the aid of sputter to further increase Jsc[29].

Finally, though the combination between solar cells and fuel cells is still a big challenge, our research does help the development of solar cells and the living of human beings.

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Vita

Hsin-Yu Lee was born at 25, Aug. 1986 in Tainan, Taiwan. He

received the B.S. degree in Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2007. The M.S.

degree will receive in Department of Photonics, National Chiao Tung University, Hsinchu, Taiwan in 2009. His research include the analysis and fabrication of MIS stacked solar cells.

Publications:

[1] Hsin-Yu Lee, Yi-Shian Max Lin, Kuang-Yang Kuo, Tzu-Yueh Chang, and Po-Tsung Lee, “Post-annealing Temperature Effect on the Optical and Electrical Properties of the Nano-structured Si/SiO2 Multilayer”, ISSCT’08, Taipei, Taiwan (2008)

在文檔中 疊合式金氧半太陽能電池之研究 (頁 40-0)