Synthesis and Field Emission of Chromium Carbide capped Carbon

In chapter 3, the fabrication process of the gated structure using Pt and Ti as conductive layer has been shown. Generally the structure can also be achieved by using n⁺ poly-Si as the gate material. Fig. 4.36 shows the schematic diagram of the fabrication processes. Compare to the processes using metal as the gate material, several steps were reduced when using poly-silicon. It is due to that only one photolithography step is required since the patterned poly-Si can easily be removed by reactive ion etcher. The poly-Si and oxide can therefore be etched away in a single step. Also the pattern for the etching of poly-Si and silicon oxide can also be used as the pattern for Cr deposition. The photoresist is removed at the last fabrication step. Though the n⁺ poly-Si simplifies the fabrication process, however, the material caused problem in the growth step of the chromium carbide capped carbon nanotips. Fig. 4.37 shows the surface morphology of the structure. In Fig. 4.37(a) and (b), it is obviously seen that the carbon tend to deposit on the edge of the hole pattern. It should be due to the poor conductivity of the poly-Si (compare to metals) that the negative charges tend to pile up at the edge and creates a preferential site for the deposition. The charges also contributed to irregular growth inside the hole. There’s a more serious problem which can be seen in Fig.

4.37(b). Half of the poly-Si is etched away during a 30min growth and only 100nm of poly-Si left. Hence, we preferentially used Pt as the gate material to prevent such problems, only we had to tune the parameters to prevent the deposition of carbon on the Pt in which the poly-Si has fewer problems.

Fig. 4.38 shows the gated structure with chromium carbide capped carbon nanotips grew inside. Fig. 4.38(a), (b) show the structure with 4µm diameter and Fig. 4.38(c), (d) show the structure with 8µm diameter. The growth was achieved with bias of 150V and H2/CH4=50/10 and duration for 15min with 15min of H2 pretreatment. The parameters show that the three dimension structure induced a barrier for the gas diffusion and higher hydrogen flow was

needed. Besides, the images show that there’s no much difference for the two pattern size. Fig.

4.39 shows the cross-section image of the nanotips in the hole. The interface between the nanotips and the silicon wafer indicates a selective growth behavior instead of directly etching of the wafer. As for the planer case, the material also exhibits vertical alignment in the hole-structure. However, due to the poor diffusion inside the structure, the nanotips only grow for maximum length of 0.5µm which is much shorter than the 1.5µm for the planer case.

In order to further increase the length of the nanotips in the gated structure which also means to decrease the distance between the tip and gate, we make efforts on the effects of the applied biases. Fig. 4.40 shows the cross-section images of the 8µm structure. The results show that the applied biases can further increase the tip length; however, the augmentative length is due to the etching of the Si substrate [Fig. 4.40(b), (c)] and the tip-to-gate distance remains the same. Besides, the deposition of carbon on Pt has many disadvantages for the further field emission measurements. Here we suggest that a bias of 150V [Fig. 4.40(a)] is the optimized bias for the growth of nanotips in the structure.

The result of field emission measurement of the structure is shown in Fig. 4.41. Fig. 4.41 shows the typical I-V curve. We can obtain that when the voltage is 3.30V, a current of 10µA can be achieved. Fig. 4.41(b) shows the F-N plot of the device showing a field emission behavior. Since there are some argues about the definition of the field emission area for the gated device due to the field distribution,^[175] we defined the turn-on field from the F-N plot which demonstrates in Fig. 4.41(b), a value of 2.63V (or 5.26V/µm) could be obtained. Fig.

4.42 shows the images of chromium carbide capped carbon nanotips grew on a planer surface.

The images show the selective growth behavior from a pre-pattern silicon wafer. The gaps between the two sides of nanotips are 6µm, 10µm and 20µm, respectively. The approaches may be applied to another field emission device that the controlling gate is located on the same plane. The SED or SCE^[176] (Surface conducted emission device) makes it even more easy to fabricate the devices.

1. 6” n-type (100) Si wafer

2. Wet oxidation (5800Ǻ) by furnace

3. Deposit n+ poly-Si by furnace

4. Define photoresist

5. Etch of poly-Si and silicon oxide

6. Cr coated by PVD

7. Photoresist life-off

8. Selective growth of Carbon nanotips by MPCVD

Si SiO2 PR Cr

n+ poly-Si Nanotips

Fig. 4.36 Fabrication process of the gated structure using n⁺ poly-Si.

(b) (a)

Fig. 4.37 SEM images of the gated device with n⁺ poly-Si layer showing (a) carbon deposit on the edge of the poly Si and (b) the poly-Si is etched away in plasma.

(a) (b)

(c) (d)

Fig. 4.38 SEM images of chromium carbide capped carbon nanotips grow in the gated structure.

Fig. 4.39 SEM image of the chromium carbide capped carbon nanotips showing high alignment.

(a)

300nm

500n

(b)

1100n

(c)

Top-View Cross-section View

Fig. 4.40 SEM images of chromium carbide capped carbon nanotips grow in triode structure with bias of (a) 150V (b) 200V (c) 250V, respectively.

0 1 2 3 4 5 6 7 0.00000

0.00002 0.00004 0.00006

Current (A)

Voltage (V)

0.1 0.2 0.3 0.4 0.5 0.6 0.7

1/V

(b) (a)

Fig. 4.41 Field emission measurements of the gated structure: (a) I-V and (b) F-N plot.

(a) (b)

(c)

Fig. 4.42 Selective growth of chromium carbide capped carbon nanotips on planer surface with gaps of (a) 6µm, (b) 10µm and (c) 20µm.