Comparisons

Table 2.4.2 shows the comparisons of this work simulation result and recent LNA papers.

Table 2.4.2 The comparisons of this work simulation result and recent LNA papers.

Tech. Freq.

(GHz) S11(dB) S22(dB) S21(dB) NF(dB) IIP3

(dBm) Vdd(V) Power (mW) this

work 0.18μm CMOS 5.8 -20 -24 10.2 3.4 -3 0.7 4.6

[27] 0.18μm CMOS 5 -15 -21 20 1.4 -29 0.65 1.9

[3] 0.18μm CMOS 5.75 <-10 -8 14.2 0.9 0.9 1 16

[28] 0.18μm CMOS 5.8 -5.3 -10.3 13 2.5 - 1 22

Chapter 3 3.1-10.6GHz CMOS Ultra-wideband low

noise amplifier

3.1 Introduction

The ultra-wideband (UWB) system is a new wireless technology capable of transmitting data over a wide spectrum of frequency bands approved by Federal Communication Commission (FCC) in 2002. Because the UWB system transmits information using very low power and high date rate over a wide band, it becomes more and more popular for wireless communication. The UWB standard IEEE 802.15.3a is defined by FCC, and most of the proposed applications are allowed to transmit in a band between 3.1- 10.6GHz due to its versatility in almost all of the approved UWB application. Because FCC doesn’t define all spectrums completely various methods can be employed to utilize the vast spectrum. Two proposal have been refined for the final decision: Direct-sequence UWB(DS-UWB) and multi-band orthogonal frequency division multiplexing UWB(MB-OFDM UWB). The DS-UWB divides the 3.1-10.6GHz band into two discontinuous bands while the MB-OFDM UWB proposal divides the whole band into 14 528-MHz sub-bands that are grouped into five main bands. In many ways, UWB benefits from existing wireless techniques and standards, as modulation schemes, multiple-access techniques, and transmitter/receiver architectures are adapted for UWB.

3.2 Numerous topology of UWB LNA

The noise performance of an LNA is directly dependent on its input matching. The wide-band input matching is intrinsically noisier than narrow-band counterparts as the noise performance can not be optimized for a specific frequency. Thus the designer has to be trade off between

the input matching and noise. The Fig. 3.2.1 shows four basic 50Ω input matching techniques[5][6][7][8][9].

Fig. 3.2.1 Basic input matching topology. (a)Inductive source degeneration.(b)Direct resistor termination.(c)Shunt-series feedback.(d)Common-gate 1/gm termination

The four input matching is only suit for narrow band amplifier. In wireless mobile communications systems, silicon integrated circuits have been widely employed in narrow-band systems, where limited gain and increased parasitic is tolerable due to lower operation frequency and the application of tuned networks.

There are few examples of development of high-frequency wideband amplifiers employing silicon transistors, in particular in CMOS technology.

z Distributed amplifiers [10]

The Fig. 3.2.2 shows a basic four-stage single-ended distributed amplifier.

Fig. 3.2.2 Basic four single-end distributed amplifier

The distributed amplifiers normally provide wide bandwidth characteristics but they consume large dc current due to the distribution of multiple amplifying stages, which make them unsuitable for low-power application. And the distributed amplifiers are not optimized for noise. This bring the challenge of finding a low-power topology that satisfies all the other design requirements, the most stringent one being the input match.

z Resistive shunt-feedback amplifiers

In Fig. 3.2.3 a conceptual schematic of a shunt feedback amplifier is shown[11].

Fig. 3.2.3 Conceptual schematic of a shunt feedback amplifier.

In the resistive shunt-feedback amplifier, input resistance is determined by the feedback

resistance divided by the loop-gain of the feedback amplifier. The input impedance is

resistive shunt-feedback amplifier has better bandwidth than conventional low noise amplifier but it has limited input match at higher frequencies due to the parasitic input capacitance. As consequence, the maximum input capacitance that can be tolerated to achieve an input reflection coefficient equal to -10dB at ƒ = 10 GHz is as low as

(

¹

)

^Γ2

(

^{1− Γ2}

)

= R f

C π _s =200fF. To satisfying this requirement with a CMOS amplifier stage while achieving sufficient gain and low noise is difficult. Some paper has been present by using this topology over the low band of UWB(3-5GHz)[12] shown in Fig.3.2.4.

Fig. 3.2.4 UWB LNA topology. (a) Overall schematic. (b) Small-signal equivalent circuit at the input.

In this topology, one of the key role of the feedback resistor Rf is to reduce the Q-factor of the resonating narrowband LNA input circuit. The Q-factor of the circuit can be approximately given by

. According to this equation, the

narrowband LNA input matching can be converted into a wideband amplifier by the proper

selection of Rf. The feedback resistor helps to extend the bandwidth of the amplifier as well as the gain flatness, while contributing a small amount in NF degradation.

z Ultra-wideband low noise amplifier using LC-ladder filter input matching network [11][13]

Recently another topology of wideband LNA has been present. It expands the conventional narrow-band LNA using source degeneration by embedding the input network of the amplifying device in a multisection reactive network so that the overall input reactance is resonated over a wider bandwidth. Fig. 3.2.5 shows a typical narrowband cascade LNA topology and its small-signal equivalent circuit.

Fig. 3.2.5. Narrowband LNA topology. (a) overall schematic. (b) Small-signal equivalent circuit at the input The inductor Ls is added for simultaneous noise and input matching and Lg for the impedance matching between the source resistance Rs and the input of the narrowband LNA[14]. Fig.

3.2.5(b) shows the equivalent small-signal circuit. Assume the gate-drain Cgd can be ignore the impedance of the gate terminal is a series RLC circuit. The reactive part of the input impedance is resonated at the carrier frequency in narrowband design. The basic concept of the LC-ladder input matching is expanded from the input impedance of the narrowband which is a series RLC circuit. Consider a fourth-order bandpass ladder filter, shown as in Fig. 3.2.6.

Fig. 3.2.6 Fourth-order bandpass ladder filter used for impedance matching.

The right part of the bandpass filter looks similar to the equivalent circuit of the inductively degenerated transistor in Fig. 3.2.5(b). Therefore, the bandpass filter can embed the inductively degenerated transistor and obtain the desire input impedance. The LC-ladder filter input matching of wideband LNA has two significant drawbacks. Because the LC-ladder filter at the input mandates a number of reactive elements, which could lead to a larger chip area and noise figure degradation in the case of on-chip implementation.

z Ultra-wideband low noise amplifier using the common-gate as the first stage.[15]

The common-gate architecture that is illustrated in Fig. 3.2.1(d) has highest potential to achieve the wide-band input matching. In traditional narrow-band receiver the common-gate is not used widely due to its relatively lower gain and higher noise figure than a common-source amplifier. The actual configuration of common-gate stage is shown in Fig.

3.2.7(a).

Fig. 3.2.7 (a) Configuration of a common-gate input stage. (b) The small-signal equivalent circuit.

From the Fig. 3.2.7(b),we can derive the input impedance inductors and capacitors and can be regarded as purely reactive within the frequency band of

interest. // // ( )

After some mathematical calculation

))

Since gm1Xo2(ω)<<Ro2+Xo2(ω),the real part in the denominator will remain relatively constant within the 3.1-10.6GHz UWB band. The imperfect matching of the common-gate stage throughout the band arise from the frequency dependent Xs(ω) that dominates the imaginary part in the denominator. To get a good matching over the wide band , the LC tank of Xs(ω) formed by Ls and Cgs should be selected such that they resonate at the center of the 3.1-10.6GHz, leaving only a 50Ω real input impedance. The noise figure of the common-gate input stage UWB LNA can be improved by increasing gm1 but it will degrade the input matching.

z Reactive-feedback wideband amplifier [16][17]

An alternate approach to the modified UWB LNA is a negative-feedback amplifier. Feedback offers numerous benefits for broadband application, including gain, stability over processing and supply variations, lower distortion and the ability to get port impedances for noise and impedance matching. However the simple feedback stage is difficulty to achieve a 50Ω input match, low noise figure and low power consumption in simultaneous. Broadband resistive feedback also meets the bandwidth target, but the reactive-feedback using transformer contributes less noise as losses are relatively small in the transformer windings. The

schematic shown in Fig. 3.2.8 is present recently [16].

Fig. 3.2.8 Reactive feedback UWB LNA.

The transformer in the first stage give a broadband input match without multi-inductor network which will add noise and require more chip area. The current-reuse is also approved in this design for lower DC power consumption. The transformer of second stage provides a broadband output match relatively close to 50Ω so the output buffer is not need for output match.

z Wideband matching using the transistor intrinsic gate-drain capacitor [18]

Recently a novel wideband input match has been present. It considers the gate-drain capacitor has significant effect on the circuit performance. The Fig. 3.2.9 show a simple common source amplifier with source degeneration inductor and the drain loaded an equivalent capacitor and resistor from the next stage.

Fig. 3.2.9 The small signal equivalent circuit of common-source with inductive source degeneration

The Cgd and ro are neglected in conventional analysis of low noise amplifier. It is inaccurate numerically. If both Cgd and ro are considered we will find that the input match at high frequency is depend on the resistive load and at low frequency is depend on the capacitive load. We can achieve wideband match without external input match network. It also can achieve low noise match.

3.3 Design consideration

3.3.1 Wideband match technique[18]

Consider a small signal equivalent circuit of a source degeneration low noise amplifier which is shown in Fig.3.3.1 CL and RL present the parasitic capacitance and resistance which is contributed from the next stage.

Fig. 3.3.1 The small signal equivalent circuit of source degeneration

To derive the input impedance we consider that the load of the circuit is divided into two parts, one of which is only a resistor RL which dominates at the high frequency and another is the capacitor CL dominates at the low frequency. The circuit of resistive loading is shown in Fig.

3.3.2.

RL

Fig. 3.3.2 The equivalent small signal circuit of resistive loading

While we assume that _{s L}

gs

s L R

L << C ω <<

ω ω1

we can find the input impedance )]1 the input impedance will approach the 50Ω when the inductor Ls is designed properly. To derive the input impedance of the capacitive loading, which is shown in Fig.3.3.3, we divided this circuit into two branches and replace the current source by voltage source.

Fig. 3.3.3 The equivalent circuit with capacitive loading

One of the two branches is looking into the capacitor Cgs and another is looking into the capacitor Cgd. Yα is the impedance looking into the Cgd and Zβ is the impedance looking into the Cgs. Assuming that the current flowing the capacitor Cgd and Cgs is smaller than the induced current gmVgs, the Yα can be derived. Thus 1 ) ¹

with (1 _{m o})

The input impedance of the capacitive loading circuit can be found out as follow ) 1

Z_in . According to above the equations the input impedance can be rearranged as a simpler RLC circuit as shown in Fig.3.3.4.

Rα Cα Lα

Cgs Cgd

Rβ

Cβ

Lβ

Fig. 3.3.4 the equivalent circuit of the input impedance

The Cgd branch is the critical branch that is a series component of RLC and its resonate frequency is

loading is matched and the capacitive loading is matched at the comparatively low frequency.

Thus the composite RLCL load circuit is matched over a wide bandwidth.

3.3.2 3.1-10.6GHz CMOS Ultra-wideband low noise amplifier

Fig. 3.3.5 shows a UWB LNA using transistor’s intrinsic gate-drain capacitor to achieve input matching. In this design we add an inductor to the original RLCL loading circuit, as shown in figure Fig. 3.3.6.

Fig. 3.3.5 The schematic of proposed UWB LNA

Ls

CL RL Li

Cex

R_d

Ld

Vdd

Fig. 3.3.6 The equivalent circuit of the first stage UWB LNA

In this circuit the external Cex is added to increase the equivalent gat-drain capacitance, thus allowing a smaller transistor to get better input match but it effect the noise figure at lower frequency. The inductor Li can improve the input matching. From the simulation result we can find add the inductor can help S11 contour around the original point (i.e. 50Ω ) in the smith chart. The Fig. 3.3.7 shows this simulation result.

freq (100.0MHz to 12.00GHz)

S(1,1)

L=0nH

freq (100.0MHz to 12.00GHz)

S(1,1)

L=2nH

freq (100.0MHz to 12.00GHz)

S(1,1)

L=1.5nH

freq (100.0MHz to 12.00GHz)

S(1,1)

L=2.5nH Fig. 3.3.7 The input return loss for different Li

To improve the input match at lower frequency the gate inductor is added and it will influence the noise figure. Shunt-series-peaking is a bandwidth extension technique [19] which is used in this circuit to extend bandwidth by the inductor Ld, Li and resistor Rd. To achieve a flat gain over whole frequency range we cascade three stages.

The concept of this design is that we design the first stage with a capacitive, resistive and inductive load to achieve the input return loss first. The transformer is added to improve the input retune loss and flatter gain but it may make the circuit become a little unstable and it has to be design carefully. The value of capacitive load is approximated to the next input impedance of next stage. Due to the input impedance of the common source topology is the series resistance, capacitor and inductor it is suited to be the consequence stage. We use the common source topology to be the second and third stage. Then we replace the resistance by

the common source stage with a capacitive, inductive and resistive load and fine tune all element to get input return loss and output return loss. And the third stage is designed by the same way. Finally we fine tune the drain inductor to improve the flatter gain. The three stages are response for different band of gain to maintain the flatter gain over whole wide band.

3.4 Chip implementation and measurement results

3.4.1 Layout considerations

The chip layout and photo of the UWB LNA is shown in Fig. 3.4.1. The power supply (Vdd) is 1V. The 0.18μm (minimum) gate length was chosen to get the highest speed. The MIM (Metal-Insulator-Metal) capacitors without shield and hexagonal spiral inductors (the Q-value is below 18) are used in this work. Guard-rings are added with all elements to prevent substrate noise and interference. A shielded signal GSG pad structure is used in RF input and RF output to reduce the coupling noise from the noisy substrate. All interconnections between elements are taken as a 45° corner. The RF input and the RF output are placed on opposite sides of the layout to avoid the signals coupling. The chip size is 1.314x0.89mm². All connection wire are simulated by ADS momentum to extract parasitical effect.

(a)

(b)

Fig. 3.4.1(a) chip layout (b) chip photo of UWB LNA.

3.4.2 Measurement considerations

The UWB LNA is designed for on-wafer measurement so the layout must follow the rules of CIC’s (Chip Implementation Center’s) probe station testing rules. This circuit needs four 3-pin DC PGP probe and two RF GSG probes for on-wafer measurement. A large coupling capacitor is needed in the input of the LNA to isolate the dc between circuit and equipment.

Fig. 3.4.2 ~ Fig. 3.4.5 show the measurement setup for S-parameters, noise figure, 1dB compression point and third-order intercept point. We will discuss the experimental and simulation resultsof this circuit in following sections.

Fig. 3.4.2 Measurement setup for S-parameters Fig. 3.4.3 Measurement setup for noise figure

RFin RFout

Fig. 3.4.4 Measurement setup for P1dB

DUT

DC PAD

DC PAD Signal

generation 1

Spectrum analyzer Signal

generation 2

Balun

Fig. 3.4.5 Measurement setup for IIP3

3.4.3 Measurement results and discussion

The Ultra-wideband low noise amplifier is simulated by ADS. The simulation and measurement results are shown in Fig. 3.4.6(a)~(d), where the simulation S11 < -10dB and S22<-10dB from 3.1GHz to 10.6GHz. The simulation maximum and minimum power gain (S21) are 13.2dB at 4.4GHz and 12.138dB at 10.6GHz, respectively

0 2 4 6 8 10 12 14 16 18 20 frequenc(GHz)

-40 -35 -30 -25 -20 -15 -10 -5 0 5

dB

S11_sim. S11_meas.

Fig. 3.4.6(a) simulation and measurement result of S11

0 5 10 15 20

frequency(GHz) -45

-40 -35 -30 -25 -20 -15 -10 -5 0

dB

S22_sim. S22_meas.

Fig. 3.4.6(b) simulation and measurement result of S22

0 2 4 6 8 10 12 14 16 frequenc(GHz)

-200 -180 -160 -140 -120 -100 -80 -60 -40 -20

dB

S12_sim. S12_meas.

Fig. 3.4.6(c) simulation and measurement result of S12

0 2 4 6 8 10 12 14 16

frequenc(GHz) -40

-35 -30 -25 -20 -15 -10 -5 0 5 10 15

dB

S21_sim. S21_meas.

Fig. 3.4.6(d) simulation and measurement result of S21

3 4 5 6 7 8 9 10 frequency(GHz)

4 6 8 10 12 14

nf_sim nf_meas

Fig. 3.4.6(e) simulation and measurement result of NF

The simulation and measurement result of P1dB are shown in Fig. 3.4.7 (a)~(c).

-30 -25 -20 -15 -10 -5 0 5 10

input power(dBm) -25

-20 -15 -10 -5 0 5 10 15

dB

P1dB_sim P1dB_meas

P1dB_sim.=-15dBm P1dB_meas.=2.5dBm

f=4.1GHz

Fig. 3.4.7(a) simulation and measurement result of P1dB at 4.1GHz

-30 -25 -20 -15 -10 -5 0 5 10 input power(dBm)

-25 -20 -15 -10 -5 0 5 10 15

dB

P1dB_sim P1dB_meas

P1dB_sim.=-14.8dBm P1dB_meas.=4dBm

f=6.1GHz

Fig. 3.4.7(b) simulation and measurement result of P1dB at 6.1GHz

-30 -25 -20 -15 -10 -5 0 5 10

input power(dBm) -20

-15 -10 -5 0 5 10 15

dB

P1dB_sim P1dB_meas

P1dB_sim.=-13dBm P1dB_meas.=5.5dBm

f=8.1GHz

Fig. 3.4.7(c) simulation and measurement result of P1dB at 8.1GHz

The simulation and measurement results of IIP3 are shown in Fig. 3.4.8(a)~(f)

Fig. 3.4.8 (a) the simulation of IIP3 at 4.1GHz (b) the measurement result of IIP3 at 4.1GHz

-30 -25 -20 -15 -10 -5 0 5

Fig. 3.4.8 (c) the simulation of IIP3 at 6.1GHz (d) the measurement result of IIP3 at 6.1GHz

-30 -25 -20 -15 -10 -5 0 5

Fig. 3.4.8 (e) the simulation of IIP3 at 8.1GHz (f) the measurement result of IIP3 at 8.1GHz The simulation and measurement result is summary in Table 3.4.1.and comparison with recent papers in Table 3.4.2.

Table 3.4.1 Performance summary of Ultra-wideband LNA

Specification Measurement Post Simulation

S11 (dB) <-5 <-10

S22 (dB) <-5 <-10

S21 (dB) -10(average) 12dB(flat gain)

S12 (dB) <-30 <-40

Noise Figure (dB) 5(min) 4.5(min.)

4.1GHz 6.1GHz 8.1GHz 4.1GHz 6.1GHz 8.1GHz P1dB (dBm)

2.5 4 5.5 -15 -15 -13

IIP3 (dBm) 6 5.5 6.8 -7 -6 -4

Vdd (V) 1 1

LNA Power (mW) 17 18.12

Table 3.4.2 The comparisons of this work simulation result and recent LNA papers.

The measurement results reveal that the input return loss is not good and no power gain.

We consider the layout of the UWB LNA to find the possible problem. The simplified chart of layout is shown in Fig. 3.4.9.

Fig. 3.4.9 simplified chart of UWB LNA layout

We find that the all Vss Pads of internal chip layout are not connected each other. They

connect each other by external measurement machine and along this path may be suffer from some unknown parasitical impedance. Thus it lets the expected ground node to become imperfect ground. We add this parasitic impedance at this Vss node and the modified simulation can reveal that the imperfect ground may effect the performance of this UWB LNA, which is shown in Fig. 3.4.10(a)~(d).

0 2 4 6 8 10 12 14 16 18 20

Fig. 3.4.10(a) modified and measurement result of S11.

0 2 4 6 8 10 12 14 16 18 20

Fig. 3.4.10(b) modified and measurement result of S22

0 2 4 6 8 10 12 14 16 18 20 GHz

-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15

dB

S21_modified S21_meas.

Fig. 3.4.10(c) modified and measurement result of S21

0 2 4 6 8 10 12 14 16 18 20

GHz -160

-140 -120 -100 -80 -60 -40 -20

dB

S12_modified S21_meas.

Fig. 3.4.10(d) modified and measurement result of S12

According to the above figures it can be found that the issue of non-connection between Vss PAD is the possible problem of this circuit. Thus we use the external PCB board to

connect the Vss PAD. The PCB trace and bond wire induce additional parasitical effect. The trace on the board can be approximate microstrip line. The height of substrate is 0.8mm, dielectric is 4.4 and loss tangent is 0.02. The metal is copper which conductivity is 5.8x10⁷. The inductor of bond wire is above 0.8nH/mm. The Fig. 3.4.11 shows the approximately simplified circuit of the chip bonded on PCB board. The PCB layout is shown in Fig. 3.4.12.

and the photo of PCB board and bonded chip is shown in Fig. 3.4.13(a),(b).

We consider the bond-wire and PCB-trace effect and the modified simulation result are shown in Fig. 3.4.14(a)~(d).

Vbias Vss Vdd Vss Vdd

Vss

Vss

Vss Vbias Vss

Vout Vss

Vss Vin

Fig. 3.4.11 approximately simplified circuit of UWB LNA

Fig 3.4.12 PCB layout

Fig. 3.4.13 (a) photo of PCB board Fig. 3.4.13 (b) photo of bonded chip.

0 2 4 6 8 10 12

GHz -35

-30 -25 -20 -15 -10 -5 0

dB

S11_modified S11_PCB_meas.

Fig. 3.4.14 (a) modified and PCB_meas. result of S11.

0 2 4 6 8 10 12 GHz

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0

dB

S22_modified S22_PCB_meas.

Fig. 3.4.14 (b) modified and PCB_meas. result of S22.

0 2 4 6 8 10 12

GHz -35

-30 -25 -20 -15 -10 -5 0 5 10

dB

S21_modified S21_PCB_meas.

Fig. 3.4.14 (c) modified and PCB_meas. result of S21.

0 2 4 6 8 10 12 GHz

-200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0

dB

S12_modified S12_PCB_meas.

Fig. 3.4.14 (d) modified and PCB_meas. result of S12.

Fig. 3.4.14 (d) modified and PCB_meas. result of S12.

在文檔中 應用於無線網路之低電壓(0.7V)變壓器迴授低雜訊放大器與應用於超寬頻系統之低雜訊放大器之設計 (頁 40-0)