5 Circuit Design of Transmitter
5.5 Transmitted signal strength indicator (TSSI)
In Figure 5-11, an on-chip transmitted signal strength indicator (TSSI) is implemented to measure the transmitter output power. The TSSI consists of three stages. The first stage is a voltage amplifier (NM1 and R1) that increases the detecting sensitivity. The second stage is a peak detector (NM2 and C2) configured as a source follower with a capacitive load. The equivalent 1/gmNM2 resistor provided by NM2 is connected in series to the capacitive load (C2) to form a RC rectifier for detecting the rms voltage of the incoming RF signals. NM3 and C3 are used to provide a reference voltage. The third stage is a comparator (NM4-NM5, PM6-PM7 and R2-R3) that compares the rms
voltage of the incoming RF signals with the reference voltage. Finally, PM8 and R4 are used to transform the output current of the comparator into an output voltage.
Figure 5-11: Schematic of the TSSI.
Chapter 6
Receiver Measurement
6.1 Low noise amplifier (LNA) and 3
th-Order Notch Filter
The fabricated LNA with notch filter was bonded on FR4 PCB and tested by Agilent N5230A network analyzer for S-parameter and by N8975N noise figure analyzer for NF measurement. The chip photo is shown in Figure 6-2. Total current assumption including output buffer and notch filter is 22 mA under 1.2V supply. In Figure 6-2, the measured input return loss (S11) is less than -10dB at frequency range from 2.5 ~ 5.2 GHz and power gain (S21) has 10.75 dB difference at 3.5GHz between high and low gain mode switch. Band switch function is shown in Figure 6-3, the measured power gain is 13.56dB at 3432MHz (LG=0001), 15.86 dB at 3960MHz (LG=1000) and 15.87 dB at 4488MHz (LG=1111). The measured noise figures are 3.9 dB at 3432MHz, 3.19 dB at 3960 MHz and 4.7 dB at 4488MHz. When F_Tune=1.3V, the NF at 4488MHz will be improved by 0.5 dB and notch frequency will move to 5.85 GHz with gain degraded to -24.73 dB as shown in Figure 6-4 and 6-5.
Figure 6-1: Chip photo of the LNA with notch filter.
Figure 6-2: Measurement results for input return loss and high/low gain switch.
Figure 6-3: Measurement results for band group1 switching.
Figure 6-4: Measurement results of NF under different notch frequency.
Figure 6-5: Measurement result of highest notch frequency setting.
The nonlinearity of LNA is assembled by input 1-dB compression point (P1dB) and IIP3. The measured P1dB at 4488 MHz are -16.82 / -6.98dBm at high/low gain mode as shown in Figure 6-6. Figure 6-7 shows the improvement value of IIP3 with proposed notch filter under two-tone test (5.25GHz and 5.85 GHz) that represent interference signals of 802.11a WLAN system. The measured IIP3 at 4.65GHz is 4.04 dBm; as notch frequency moves to 5.85 GHz (F_Tune=1.3V), IIP3 becomes 8.74 dBm. So the IIP3 at 4.65 GHz (4488MHz band) can be improved 4.7 dB by the proposed third-order active notch filter. Table IV summarizes the measurement results and compares them with previous wide-band LNA designs. [33] and [34] are the LNA designs with notch filter. There may be some stability problems due to the cross-coupled topology of notch filter, but it doesn’t occur in this work. The IIP3 after
improved in this work is 8.74dBm which is 4.14 dB greater than that of [33] and 19.54 dB greater than that of [34]. So the proposed notch filter can be used to improve IIP3 of wide-band LNA successfully under out-band interferences.
Figure 6-6: P1dB measurement of high gain mode and low gain mode.
TABLEIV. BENCHMARK OF ULTRA-WIDE-BAND LNA DESIGNS
References [40]MWCL2006 [41]JSSC2004 [42]JSSCC2005 [43]ISSCC2007 [44]RFIC2007 This work Process CMOS 0.13µm CMOS 0.18µm CMOS 0.18µm CMOS 0.13µm CMOS 0.18µm CMOS 0.13µµµµm
Architecture LC ladder LC ladder
Resistive shunt feedback
Inductive-degen eration
Three-stages LC ladder
Frequency(GHz )
2~4.6 2.3~9.2 2~4.6 3~8.2 3.5 5.5 7.2 3.43 3.96 4.49
S21(dB) 9.5 9.3 9.8 18.5 20 10 15 13.56 15.86 15.87
NF (dB) 3.5 4 2.3 3.5 4 6.2 5.1 3.9 3.19 4.7
S11(dB) <-10 <-9.9 <-9 <-10 -18 -12 -10.5 -12 -14 -20
PDC (mW) 16.5 9 12.6 31.5 21.6 26.4
IIP3 (dBm) -0.8 -6.7 -7 4.6 (4.6GHz) -18.5 -10.8 -15.5 8.74 (4.65 GHz)
FoM (/mW) -3.6 -2.03 0.3 2.59 4.87 -8.34 -1.83 -2.27 1.3 -1.24
Figure 6-7: Nonlinearity measurement results of IIP3 under out-band interferences test.
21 diss
ie: FOM = S F− ⋅− ⋅− ⋅− ⋅1 P
6.2 Analog baseband
The baseband chain has been implemented in a 1.2 V 0.13 μm CMOS technology.
The chip micrograph is shown in Figure 6-8. It is embedded in a RF transceiver and occupies 0.8 mm2. Figure 6-9 shows the measured frequency response of the analog baseband with comparing to the simulated frequency response of the 6th Gm-C filter and the analog baseband (SK LPF+6th Gm-C filter). The measured pass-band edge frequency is 250 MHz with 1 pF of probe capacitance. As shown in Figure 6-10, measured out-band IIP3 (f1=400 MHz, f2=790 MHz) of the filter is -6 dBV under voltage gain of 73 dB and pass-band edge frequency of 250 MHz. The high linearity performance is achieved under 1.2 V supply by the current-mode PGAs and the proposed current-mode SK LPF. Measured in-band IIP2 (f1=40 MHz, f2=50 MHz) of the filter is -59 dBV under voltage gain of 68 dB and pass-band edge frequency of 250 MHz. The measured out-of-band IIP2 (f1=400 MHz, f2=410 MHz) is −5 dBV under the voltage gain of 68 dB and the pass-band edge frequency of 250 MHz (Figure 6-11). Therefore, the issue of current amplifiers indicated by poor HD2 performance is improved by the proposed architecture and the DC-offset calibration.
The measured Noise Figure (Figure 6-12) is 12~14 dB within the BW at the maximum gain setting of 73 dB. Performance summary and comparison to [12] are listed in Table V.
Figure 6-8: Die photo of the baseband chain in 0.13µm CMOS technology. The baseband chain comprises SK LPF, current-mode PGAs, 6th–order Chebyshev Gm-C filter and circuitry for Gm-C and DC-offset calibration.
Figure 6-9: Measured frequency response of the baseband chain. The measured pass-band edge frequency can be varying from 250MHz to 300MHz with 1pF of probe capacitance.
Figure 6-10: Measured out-band IIP3 (f1=400MHz, f2=790MHz) of the baseband chain under voltage gain of 73dB and pass-band edge frequency of 250MHz.
Figure 6-11: Measured out-band IIP2 (f1=400MHz, f2=410MHz) of the baseband chain under voltage gain of 68dB and pass-band edge frequency of 250MHz.
Figure 6-12: Measurement noise figure of the baseband chain under voltage gain of 73dB and pass-band edge frequency of 300MHz.
TABLE V: Performance summary of the baseband chain and compare to [12].
[12] This work
Technology 0.13µm CMOS 0.13µm CMOS
Supply Voltage 1.2V 1.2V
Filter order 5 6
Passband edge frequency 240MHz 250~300MHz
Voltage Gain at 10MHz 12.9~47.6dB -9~73dB
Gain Resolution (dB) N.A. 0.5
Input-referred noise figure 7.7nV/√Hz (22dB) 14dB In-band IIP3 (f1=30MHz,
Chapter 7
Transmitter Measurement
The UWB RF transmitter is implemented in a 1.2 V 0.13 µm CMOS process. The photograph of the chip is as shown in Figure 7-1. The RF circuits and the analog baseband occupy an active area of 1.2x0.4mm2 and 0.9x0.35mm2, respectively. The following measurement results are based on the bias condition of current consumption of 55 mA from a 1.2 V supply. The frequency response of the analog channel-selection filter was measured, as shown in Figure 7-2. The measured corner frequency is 250 MHz. The pass-band ripple is less than 1 dB. The measured out-of-band rejection is over 35 dB at 500 MHz offset. The output impedance of the transmitter was matched to 50Ω over 3-8 GHz. As shown in Figure 7-3, the measured output return loss is better than -9.3 dB in the frequency range of 3-10 GHz.
The IQ modulation accuracy is demonstrated by the parameters of sideband, carrier suppression and error vector magnitude (EVM). In Figure 7-4, the measured output power, sideband and carrier suppression at frequency of 3432 MHz are -5.1 dBm, 46.1 dBc and 31.6 dBc, respectively. In Figure 7-5, the measured output power, sideband and carrier suppression at the frequency of 7656 MHz are -9.7 dBm, 29.1 dBc and 43 dBc, respectively. In Figure 7-6, the measured EVM is -28 dB under the data rate of 480 Mbps in MB-OFDM modulation as output power of -10 dBm at 3432 MHz. Linearity performance is demonstrated by the parameter of output 1-dB
compression point (OP1dB). A one-tone test for extracting the output 1-dB compression point by sweeping the voltage swing of baseband signals is performed, and output power levels of the power amplifier are monitored by the spectrum analyzer. The measured output 1-dB compression point for each frequency in band group 1 and 3 is listed in Table VI. In the worst-case, the output 1-dB compression point is -0.6dBm in 7656 MHz. Table VI also lists the measured sideband and carrier suppression for each frequency from 3.4 GHz to 7.6 GHz. Table VII summaries the performance of this works and compares with the reported UWB transmitters.
A UWB transmitter need to provide the transmit power tuning to regulate the transmit power spectral density, while still providing a reliable link for the data transfer. The linear-in-dB gain tuning function is verified by sweeping the tuning voltage, which is described in Figure 7-7. The VGA exhibits a 14 dB linear-in-dB gain tuning curve within the tuning voltage of 0.4-0.95 V. An on-chip TSSI is implemented to measure the output power. The power detection function is examined by sweeping the baseband signals level, and Figure 7-8 shows the detection curve of the TSSI. The effective power detection range is from -24 dBm to -3 dBm.
Figure 7-1: Photograph of the chip.
Figure 7-2: Measured frequency response of the analog channel-selection filter.
Figure 7-3 Measured output return loss of the transmitter front-end.
Figure 7-4: Measured output power, carrier suppression and sideband suppression performance at 3432MHz.
Figure 7-5: Measured output power, carrier suppression and sideband suppression performance at 7656MHz.
Figure 7-6: Measured error vector magnitude (EVM).
TABLEVI
PERFORMANCE SUMMARY
3432MHz 3960MHz 4488MHz 6600MHz 7128MHz 7656MHz Pout,max
(dBm)
-5.17 -5.36 -6.06 -6.3 -8.8 -9.71
OP1dB (dBm)
1.5 1.3 1.7 0.2 0.4 -0.6
Sideband Suppression
(dBc)
46.1 43.7 40.4 30.4 30.1 29.1
*Carrier Suppression
(dBc)
31.6 29.4 27.6 21.0 25.5 43.7
* Carrier suppressions are shown before calibration. After calibration, Carrier suppressions are all over 40dBc.
TABLEVII
* Includes power consumption of Synthesizer.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
-4
-2 0 2 4 6 8 10 12 14 16
C o n ve rsi o n G a in ( d B )
Control Voltage (V)
Figure 7-7: Measured voltage gain versus gain control voltage.
-30 -25 -20 -15 -10 -5 0 0.0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
D et e c to r V o lt a g e ( V )
Output power (dBm)
Figure 7-8 Measured detector voltage versus output power.
Chapter 8
Conclusion
A 3~5 GHz wideband, interference-robustness RF receiver had been designed and implemented in a 1.2 V 0.13 µm CMOS process. In the RF front-end, a differential LC ladder LNA with proposed 3-order active notch filter was designed in the receiver.
There are many functions of band selection, gain switch, notch frequency selection and Q-factor tuning of notch filter are integrated in the LNA. The proposed notch filter was proved to eliminate the interference signal at 5.85 GHz and to increase IIP3 by 4.7 dB successfully under test interferences at 802.11a system to avoid saturating desired signals at 4488 MHz band. The LNA provides maximum power gain of 15.87 dB at 4488MHz, P1dB of -16.82dBm at 4488MHz and minimum NF of 3.19 dB at 3960MHz.
An analog baseband chain with features of wide-bandwidth and wide dynamic range of gain, as well as low noise and high linearity for UWB has been presented.
Current-mode PGA gives excellent noise figure and IIP3 performance.
Digital-assisted DC offset calibration solves the problem of poor IP2 performance associated with DC offset of the current-mode PGA. The bandwidth of the current-mode PGA and Gm-C filter can be further extended by using nanometer CMOS process. This work demonstrates a realization of a baseband chain applied for wideband communication systems.
A low-power, high-linearity 3-8 GHz wideband RF transmitter for UWB applications had been designed and implemented in a 1.2 V 0.13 µm CMOS process.
An OP1dB of +1.5 dBm, maximum output power of -5 dBm and carrier leakage suppression of 31.66 dBc is achieved at the frequency of 3432 MHz. An OP1dB of -0.6 dBm, maximum output power of -9.7 dBm and carrier leakage suppression of 43 dBc is achieved at the frequency of 7656 MHz. The entire transmitter draws a current of 55 mA from a 1.2 V supply. The design techniques for realizing a low-power, high-linearity wideband RF transmitter are addressed in this work.
Further Work
1. The proposed current-mode wideband analog baseband implemented by using nano-meter CMOS process can extend its operating bandwidth up to over 1 GHz for 60 GHz UWB applications.
2. Gain and phase mismatch between in-phase and quadrature-phase paths of the analog baseband will lead to degradation of bits error rate (BER) performance of the entire receiver. Therefore, calibration schemes for compensating the gain and phase mismatch of the analog baseband need to be developed in the further works.
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Horng-Yuan, Shih ( (( (施鴻源 施鴻源 施鴻源 施鴻源) )) )
EDUCATION:National Chiao-Tung University, HsinChu, Taiwan.
Institute of electronics (June 2004~Present)
Currently pursuing PhD degree with a concentration in RF and analog circuits design for wireless communication and frequency
synthesizers.
Advisor: Prof. C. N. Kuo (郭建男)
National Chiao-Tung University, HsinChu, Taiwan.
Master of Science in Communication Engineering, June, 2000.
Horng-Yuan Shih (M’03) was born in Taipei, Taiwan, in 1976. He received the B.S.
degree in electrical engineering from Tamkang University, Tamsui, Taiwan in 1997, and the M.S. and Ph.D degree in communication engineering and electronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 2000 and 2010, respectively.
In 2001, He joined System-on-Chip (SoC) Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. From 2001 to 2002, he was a RF design engineer. He designed power amplifiers for GSM system in a GaAs HBT process, a low phase noise 1.8 GHz LC-VCO for fulfilling strict requirement of GSM/DCS system in a 0.18 µm CMOS process and an RF transmitter for W-CDMA system in a 0.35 µm SiGe BiCMOS process. From 2003 to 2006, he was as a section manager and was responsible for developing a RF transceiver for W-CDMA system.
He also designed a fractional-N synthesizer for a multi-mode RF transceiver (GSM/DCS and WLAN) in a 0.13 µm process. From 2007 to 2008, he was responsible for designing a wideband RF transceiver for UWB applications. He is now as a technical manager in STC, ITRI. He also serves as an adjunct lecturer in department of electrical engineering, Tamkang University.
He had published eleven conference and journal papers, one in the area of electromagnetic field and ten in the area of RF/analog circuits. Moreover, He holds two U.S. patent and three R.O.C. patents. His research interests include RF and analog circuit design for wireless/wireline transceivers and frequency synthesizers.
EXPERIENCE:
RF Design Engineer, Industrial Technology Research Institute. (Jan. 2001~Nov. 2003) Jan. 2001 – Dec. 2002
Design power amplifier test circuit for GSM system in GaAs HBT process.
Design a low phase noise 1.8GHz CMOS LC-VCO to fulfill GSM/DCS system.
Measured frequency tuning range is 1742~1923MHz . Measured phase noise performance is -106.4, -125.1dBc/Hz and -138.2dBc/Hz at100k, 600 kHz and 3 MHz offset, respectively. The result was published in Asia Pacific Microwave Conference 2003 in Seoul, Korea [2].
Jan. 2002 – Nov. 2003
Design IF variable gain amplifier (VGA), Tx mixer and RF VGA of transmitter for W-CDMA system in SiGe BiCMOS process.
Integrated W-CDMA RF transmitter was measured. The measured dynamic range is 80dB. Measured EVM is 1.86dB at maximum output power of 0dBm. The result was published in Radio Frequency Integrated Circuit Symposium. 2004 (RFIC 2004) [3].
Section Manager, Industrial Technology Research Institute. (Nov. 2003~Dec. 2006) Dec. 2003 – Dec. 2004
Lead designer of W-CDMA RF transceiver project. Finish two-step conversion
Lead designer of W-CDMA RF transceiver project. Finish two-step conversion