Int. J. Production Economics 85 (2003) 347–358
Heuristic PAC model for hybrid MTO and MTS
production environment
Sheng-Hung Chang
a,*, Ping-Feng Pai
b, Kuo-Jung Yuan
c,
Bo-Chang Wang
c, Rong-Kwei Li
caDepartment of Industrial Engineering and Management, Ming Hsin University of Science and Technology, 1 Hsin-Hsing Road, Hsin-Feng, Hsin-Chu County, Taiwan 304, ROC
bDepartment of Industrial Engineering, Da-Yeh University, 112 Shan-Jiau Rd., Da-Tsuen, Changhua, Taiwan 51505, ROC cDepartment of Industrial Engineering and Management, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu,
Taiwan 300, ROC
Abstract
Two distinct types of semiconductor plants in Taiwan are integrated device manufacturing (IDM) plants and foundry plants. Most IDM plants are make-to-stock (MTS) operations, focusing on throughput and machine utilization. However, foundry plants are make-to-order (MTO) operations, focusing on due date and cycle time. Besides the challenge of different process technology, the mode of hybrid operation (a combination of MTO and MTS operations) is also a formidable task for these plants. This study develops a heuristic production activity control model to achieve the two different criteria in a hybrid wafer production environment.
r2003 Elsevier B.V. All rights reserved.
Keywords: Wafer fabrication make-to-stock; Make-to-order; Production activity control; Theory of constraints
1. Introduction
Two distinct types of semiconductor plants in
Taiwan are integrated device manufacturing
(IDM) plants and foundry plants, bothwith different operation environments. Most IDM plants are make-to-stock (MTS) operations, focus-ing on throughput and machine utilization, while the foundry plants are make-to-order (MTO) operations, focusing on due date and cycle time. For strategic reasons, most IDM plants in Taiwan
are gradually switching their capacity to enter foundry business. Besides the challenge of different process technology, the mode of hybrid operation (combining MTO and MTS operations) is also a big challenge for these plants.
Numerous investigations, suchasSamadhi and
Hoang (1995), Sipper and Bulfin (1997), and
Vollman et al. (1997) have discussed operating
differences between MTO and MTS.Kogan et al.
(1998), Adan and van de Wal (1998), Williams (1984),Nguyen (1998)andNew and Szwejczewski (1995)all focused on issues of in combining MTO and MTS. These investigations agreed that plan-ning and controlling production in a hybrid production environment is challenging. However,
*Corresponding author. Tel.: +886-3-559-3142/3211; fax: +886-3-559-5142.
E-mail address:shchang@must.edu.tw (S.-H. Chang).
0925-5273/03/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0925-5273(03)00121-X
none of their research considered semiconductor plants, withtheir particularly complex manufac-turing processes.
Many studies have considered production plan-ning and control in semiconductor plants, which can be categorized into closed-loop and open-loop. Basically, closed-loop control is superior to open-loop control (Miller, 1990). The optimal WIP level is crucial in closed-loop systems, and the wafer is released according to the difference between actual
and projected WIP levels (Graves et al., 1995).
Starvation avoidance (SA) (Glassey and Resende,
1988a, b), workload regulating (WR) (Wein, 1988),
two-boundary (TB) (Lou, 1989; Lou and Kager,
1989;Yan et al., 1996), CONWIP (Spearman et al., 1989; Spearman and Zazanis, 1992), fixed-WIP
(Burman et al., 1986; Glassey and Resende,
1988a, b; Wein, 1988; Roderick et al., 1992), and
load-oriented order release (Bechte, 1988a, b,
1994; Wiendahl et al., 1992; Wiendahl, 1995; Chang et al., 2001;Huang et al., 2001) are several well-known closed-loop control policies. However, most of these focused on the problems of either MTS or MTO, and none considered a hybrid operation environment.
In a hybrid production environment, due date and minimizing cycle time are critical for MTO orders. Filling the finished product buffer size to the required level is the focus for MTS orders. The different requirements necessitate different pro-duction plan criteria. For MTO orders, the fact that due date and minimizing cycle time are key so a rigid order release plan and dispatching control are important. The release plan ensures that the order is not released too early or too late, while the dispatching control aims to expedite late orders to achieve on time delivery. For MTS orders, owing to the focus is filling the finished product buffer size to the requisite level so a rigid order release plan and dispatching control is not important. Instead, the key is to release the order to utilize remaining capacity (after planning for MTO orders) without disturbing the released MTO orders.
Since hybrid operation is a new operating mode in wafer production, a new method of production planning and control must be developed. This work aims to develop a heuristic production
activity control (PAC) model to achieve the different production criteria (for MTO and MTS) in the hybrid production environment. Fig. 1 illustrates the heuristic PAC model for hybrid wafer production. The model inputs are: workstation information, WIP information, pro-duction orders (MTO+MTS) to be processed and current shop floor information. The model itself consists of three sub-modules, the bottleneck identification sub-module, order release
sub-mod-ule and order dispatchsub-modsub-mod-ule, whichare
detailed herein. A simulation is created to test the feasibility of the model, and a comparison drawn with other PAC methods, with the comparative results revealing that the proposed heuristic model outperforms other methods.
2. Bottleneck identification sub-module
According to the theory of constraints (TOC) (Goldratt, 1991), the throughput, due date and WIP are dominated by the utilization of bottle-neck resources rather than the resources of the entire system, and thus controlling the bottleneck is crucial. First, the location of the bottleneck during the planning period must be identified. Eq. (1) is employed to calculate capacity utiliza-tion. The workstation with the highest predicted
utilization (Uw) is identified as the bottleneck
workstation, while workstations with 80% utiliza-tion or more are identified as capacity constrained resources (CCR). The remaining workstations are identified as non-bottleneck workstations.
Uw¼ P i P jXijRij 24PNðMTBFw=ðMTBFwþ MTTRwÞÞBw ; ð1Þ where 24 represents 24 h/day, Uw is utilization of
workstation w; P is the length of planning period,
N the number of machines in the workstation, Bw
the maximal quantity that workstation w can
process per unit time, MTBFw the mean time
between failure of workstation w; MTTRw the
mean time to repair of workstation w; Xij the
quantity of product i; jthtime in the same
product i; jthtime in the same workstation, i the type of product, j the number of times at same workstation, and w the number of workstation.
In Eq. (1), the denominator represents capacity available during the planning period and the numerator is the required capacity. Xij is difficult
to identify and control, and comprises two major elements: present WIP loading in the shop and loading for the planned releasing orders. Assume that MTO and MTS orders are distributed uniformly during the planning period. Finally, the standard cycle time is determined from historical data and is used to estimate the loading of eachworkstation.
3. Order releasing sub-module
As mentioned in Section 1, the release plan for MTO orders is aimed to ensure that the order is not released too early or too late. However, for MTS orders, owing to the focus on filling the finished product buffer size to the required level, a rigid order release plan is not required. Instead,
the central concern is releasing the order to utilize remaining capacity (after the planning of MTO orders) without disturbing the released MTO
orders.Fig. 2displays the flow of the sub-module.
The flow involves three major functions: determin-ing the order release sequences for MTO orders, determining the order release sequences for MTS orders, and determining the time of order release for MTO and MTS orders. Eachfunction is detailed below.
3.1. Determine the order release sequence for MTO orders
Critical ratio (CR) is applied herein as the criteria for determining the order release sequence of MTO orders. MTO orders are sequenced according the calculated CR value, with release priority increasing withdecreasing CR value. Because the order release sequence depends on the capacity loading of the shop floor, it is difficult
to estimate the CTi for the first period.
Conse-quently, the UNIFORM and FIFO are integrated and used as the rule for estimating the CTi during
The Order Dispatching Sub-Module
1.Due Date Monitoring of MTO Products
2.WIP Monitoring of MTS Products
The Order Releasing Sub-Module
1. Determining the sequence of MTO, MTS Products
2. Deciding the Timing of Order Releasing
3. Dynamic Real Time Order Releasing Sequence of MTS Products 4. Determination of Releasing Schedule Monitoring Processes
or Machines (defined by Manufacturing Departments)
WIP Quantity The Plan Period and Quantity of Releasing of MTO, MTS Workstation Information
(Machine Characteristics, Processing Time, Machine Number, Utilization)
Order Releasing, Shop Floor Control
Required Input Data Proposed Modules
Bottleneck Identification Sub-Module 1.Bottleneck Workstations
2.Capacity-Constrained Resources 3.Non-bottleneck Workstations
Determining the priority of releasing MTO Products
Distributing MTO products to each planning period according to the loading of
bottleneck workstations
Estimating the finished date of MTO products by the loading
of workstations
Releasing the wafers in advance Is the estimated finished
date later than due date?
Obtaining the daily release schedule for MTO products
Employing SA algorithm for wafer release
to the next releasing point W< S
Releasing the MTO products first, then filling up the remaining capacity by releasing the MTS products Not releasing
to the next releasing point
Is the planning period over?
Triggering the Bottleneck Identification Sub-Module and entering the next
period of shop floor control Determining the priority of
releasing MTS Products: Calculating the bi1 and Ri
bi1 < hbi1 and Ri< hRi
Calculating wpi* (hRi - Ri) to determine the release priority of the MTS products to the next releasing point Yes No Yes No Yes No Yes No
the first production period. The CR value is calculated as follows:
CRi;k¼ ðTdue i;k TnowÞ=CTi; ð2Þ
where CRi;kis the CR of ithproduct for kthbatch,
Tdue i;k the due date of ithproduct for kthbatch,
Tnowthe present time, CTithe predicted cycle time
of product i:
According to Park and Salegna (1995), th e
leveling of the bottleneck loading determines the cycle time and due date performance. Therefore, the bottleneck loading is leveled with the MTO orders for eachplanning period. Continuing this approach, the next step is to allocate the sequenced MTO orders to the planning horizon according to bottleneck loading. The slack capacity of the bottleneck after leveling will provide for insertion of the MTS orders. However, this leveling
approachis still unable to guarantee that all
MTO products will meet the due dates if the non-bottleneck becomes a temporary constraint, and this situation must still be identified before order release, and the delayed orders must be released again in advance of the original planned schedule. The sequenced MTO orders are allocated based on the average daily loading of the bottleneck of each planning horizon. The average daily loading ðDLMTOÞ is calculated using the following
expres-sions: TLMTO ¼ X iAMTO X j XiRij; ð3Þ DLMTO¼ TLMTO=P; ð4Þ
where Xi is the quantity of product i planning to
release during the planning horizon, Rij the
average processing time of product i; jthtime at bottleneck resources, P the length of planning period.
The accumulated daily loading of the bottleneck
cannot exceed DLMTO:
3.2. Determine the order release sequence for MTS orders
The release of MTS is planned so as to fill up the capacity remaining after the scheduling of MTO orders. Therefore, a dynamic real time order
release approachis specified here to deal with
problems related to the release of MTS orders. The release of an MTS order is planned only when the shop floor loading is below a certain level (S) Dbil
and DRi(Eq. 5) are used to determine which MTS
orders should be scheduled for release. Dbi1¼ hbi1 bi1> 0;
DRi¼ hRi Ri> 0;
ð5Þ
where i is the product type, bi1 the actual WIP
(visit the bottleneck first time) before the
bottle-neck, hbi1 the accumulated WIP before the
product i visit the bottleneck first time, Ri the
actual accumulated output, hRi the projected
accumulated output.
If both bi1 and Ri are below hbi1 and hRi; then
activate the MTS order. If more than two MTO
orders can be released, the value of ðwpiDRiÞ
where wpiis denoted as the MTS order weighting,
is used as release priority, withrelease priority increasing withthe value of ðwpiDRiÞ:
3.3. Release the planned MTO and MTS orders
The SA approach developed by Glassey and
Resende (1988a) is employed here to release
orders. The buffer time (S) before the bottleneck and the loading time of the bottleneck (W ) are obtained first using the following equation:
L ¼ maxðLiÞ; ð6Þ
S ¼ aL; ð7Þ
W ¼ TQþ TR; ð8Þ
where a is the number of bottleneck workstations (Chung et al., 1997), Li the total time of all
operations of product i from release to bottleneck
workstation, TQ the time that needed process all
wafer batches with the maximal total processing
time less or equal to L; TR the total workstation
repair time before bottleneck workstation. In the SA approach, the higher the value of a; the better for preventing starvation of bottleneck workstations. In this work, a represents the
number of bottleneck workstations (Chung et al.,
orders are released, and otherwise they are not released until the next evaluation period. If the orders are released, the MTO orders are released first according to the MTO order releasing sequence, after which the MTS products are released.
4. Order dispatching sub-module
The order dispatching sub-module attempts to dynamically prioritize orders at eachcontrol point. The bottleneck, capacity constraint resources and management assigned critical resources are defined as the control point in the dispatching sub-module. Table 1summarizes the proposed dispatching rules for MTO and MTS at different types of
work-stations. Meanwhile, Fig. 3illustrates the flow of
the order dispatching sub-module. The details of the flow are as follows.
4.1. Dispatching rules for MTO orders
Every MTO order, upon arrival at the control point, initiates computation of the SLACK time (Eq. 9):
Sike¼ ðDik TnowÞ Rike; ð9Þ
where Sike is the slack of product i; kthwafer
batch, ethprocess; Dik the due date of product i;
kthwafer batch; Tnow the present time; Rike the
total remaining standard processing time of product i; kthwafer batch, ethprocess.
If the SLACK is negative, then the order will be unavoidably delayed unless action is taken, and the order is placed in queue 1. Otherwise,
computation of operational SLACK continues. The equation is
OSike¼ ðODike TnowÞ Tie; ð10Þ
ODike¼ Dik ðDik rikÞ PEi l¼eþ1Til PEi l¼1Til ; ð11Þ
where OSikeis the slackness of product i; kthwafer
batch, ethprocess; ODikethe due date of product i;
kthwafer batch, ethprocess; Tie the processing
time of product i; kthwafer batch, ethprocess; rik
the releasing time of product i; kthwafer batch; Ei
the last process of product i; L the processing step. If the operational SLACK is negative, then the order is delayed at this operation only, and the order is placed in queue 2. Otherwise, the order has not delayed and is put into queue 3.
The dispatching priority is ranked according to the orders in queues 1, 2, and 3. The SRPT dispatching rule is used to prioritize orders in the same queue. Integrating the three queue control concepts with the SRPT policy can achieve due date, cycle time, and throughput simultaneously (Blackstone et al., 1982).
4.2. Dispatching rules for MTS orders
Since the MTS orders are scheduled to maximize throughput of the bottleneck, they are automati-cally placed in queue 4 upon arriving at the bottleneck. The SRPT rules are applied to schedule MTS orders in queue 4 after the scheduling of all orders in queues 1, 2 and 3. However, the problem with this approach is that too many MTS WIPs stay in front of the bottle-neck workstation or too few MTS WIPs remain in
Table 1
Releasing disciplines of MTO and MTS products on different workstation
Workstation MTO product MTS product
Bottleneck workstation Breaking into three pseudo-queueing lines to show the rush of order as well as adjust the production priority
Avoiding short of material for bottles and keeping producing products smoothly Capacity-limited workstation Breaking into three pseudo-queueing lines
to show the rush of order as well as adjust the production priority
Keeping the quantity of WIP under control to avoid temporary bottleneck and producing products smoothly
Waiting for the next part till all the parts on the bottleneck machines, capacity
constrained machines or predefined machines are finished.
Distinguishing lots waiting for process into MTO and MTS products.
MTO or
MTS products MTS product
Calculating the WIP in front of the machine Is the machine a bottleneck machine? NO Is there any WIP of MTS larger than threshold? Increasing the priority of these products to be priority #2
Searching for the process in front of
the capacity constrained machine
and decreasing the priority of the product Setting these MTS wafers to be priority #4 No Calculating the SLACK value of MTO wafers Is there any wafer lot with negative SLACK?
Is there any WIP of MTS lower
than threshold? Yes
No
Searching for the process in front of the
bottleneck machine and increasing the product to be priority #1
Yes MTO product
Setting wafers with negative SLACK to be priority #1 Yes Calculating the Operational SLACK of the remaining wafers No Is there any wafer lot with
negative Operational SLACK? Setting wafer with negative Operational SLACK to be priority #2 Yes Setting the remaining MTO wafer to be priority #3 No
Processing products with the sequence of priority
#1>#2>#3>#4
Yes
the processes before the bottleneck. The former compromises the smooth output of MTS orders, while the latter causes starvation of the bottleneck workstation. Should either one of these occur, the MTS priority needs to be adjusted. The upper and lower bounds of the WIP of the bottleneck are used as a guide to adjust the priority of the MTS orders.
If the WIP of MTS(bie) is less than the lower
bound of WIP(Lhbie), then WIP of the MTS order
is insufficient. An order is supposed to pass to the previous workstation to accelerate the throughput of MTS orders. The following rule is borrowed from JIT. The order dispatching priority for MTS
in the previous workstations is revised as wpi
ðLhbie bieÞ; with the priority increasing with the
value of this formula.
If the WIP of MTS(bie) exceeds the upper bound
of WIP (Uhbie), then the WIP of the MTS order is
too high. The priority of MTS products in front of the bottleneck workstation should be increased to ensure that the throughput of MTS products is smooth. In this case, the MTS orders with threshold values exceeding the set value are assigned to queue #2 to increase the priority of the MTS order.
A threshold (UhCCRie) is required to control the WIP of capacity constrained workstations. The processing priority is altered to #2 when WIP (CCRie) is larger than UhCCRie. To reduce the number of orders coming from upstream work-stations, the processing priority should be
de-creased. Another index (CCRieUhCCRie)/wpi
is employed here to determine the processing priority when some CCRie are larger than UhCCRie. The priority decreases with increasing
(CCRieUhCCRie)/wpi:
The FIFO dispatching rule is applied to non-bottleneck workstations because of their sufficient capacity. The FIFO discipline can reduce cycle
time and throughput variation (Wiendahl, 1995).
However, the previous rules should be adjusted when the WIP of downstream bottleneck work-stations is too high.
5. Simulation experiments
To confirm the usefulness of the proposed model, a virtual wafer fabrication shop was
designed with the SIMPLE++. The data were obtained from a Taiwan semi-conductor manu-facturing plant, and four different products were created (A, B, C, and D). Products A and B are MTS products, while products C and D are MTO products. The system contains a total of 24 workstations (from W1 to W24). Stations W1, W2, W3, and W4 are batchprocess stations, witha
batchsize of six. The ratio of MTS to MTO
products is assumed to be 5:5. From the viewpoint of long term, the product mix ratio of MTS and MTO is as follows: A:B:C:D=1:1:1:1. However, to verify the capability of the proposed model for dealing with the change of product mix, the proportion of MTS and MTO products of products A, B, C, D is generated as follows: A:B=2:1 and C:D=1:2 randomly. Due dates are based on the capacity of the MTO products. Finally, the due date for each MTO order is determined using
Dik ¼ aikþ PiRða; bÞ; ð12Þ
where Dik is the due date of product i; kthorder;
aik the arrival date of product i; kthorder; Pi the
total processing time of product i; Rða; bÞ the random distribution, the interval between a and b; i the MTO product.
To simplify the problem, we assume that only one kind of product of MTO orders exists. Owing to the due date of MTS products being more flexible than that of MTO products, the due dates of MTS products (A and B) are obtained by multiplying 1.5 from Eq. (12). The values of a and b in Eq. (12) depend on the system loading. Generally, the ratio of actual to theoretical cycle time is between 2.5 and 10 (Lu et al., 1994). The values of a and b are 3.5 and 5.5, respectively, in this study. The simulation period was 140 days, withthe first 70 days being for initial simulation, while data were collected after the 70th. Thirty iterations were conducted to test the hypothesis statistically.
Before running the system, the bottleneck resources, CCR, orders release time, and threshold values of MTS products releasing rule have to be identified. Eq. (1) identified workstation W14 as a bottleneck workstation with100% utilization, while workstation W7 was identified as a capacity
constrained workstation with94% utilization. The next step is to calculate the duration of the first time (Li) of arrival at the bottleneck workstation
(W14) of four kinds of products, A, B, C and D, and select the maximum value of four vales (L).
Here, L ¼ LC¼ 100;260 seconds. Since 14
work-stations are used, the value of buffer time (S) is 300,780 (3L) seconds. The fixed-WIP approach is employed to obtain threshold values for MTS products releasing and dispatching rules. Simula-tion is used to estimate the minimum WIP capable of maximizing utilization and throughput. The above calculation can be used to obtain hbi1; hRi
of MTS products.
System performance is evaluated from three perspectives: total performance, performance of MTO products, and performance of MTS pro-ducts. To demonstrate the advantages of the proposed approach, several PAC order releasing policies: Uniform-FIFO (first-in first-out), Uni-form-SRPT (shortest remaining processing time),
Uniform-EDD (earliest due date),
Uniform-SLACK, and FW-FIFO (fixed-wip–in first-out) are compared herein. Duncan’s Multiple Range Test is used to analyze all indices, and the indices are graded into five levels, namely A, B, C,
D, and E, ordered decreasingly.Table 2compares
overall performances. The proposed approach outperforms the alternative methods in terms of
WIP, cycle time, and throughput.Table 3lists the
performance of MTO products, revealing that the proposed approach outperforms other methods in terms of cycle time, average tardiness, and achievement of target due date. Meanwhile, Table 4lists the comparison of standard deviation
of cycle time and average tardiness withthe
Table 2
Overall performance analysis Performance
index
PAC methods Average Results of Duncan testing WIP (lots) Proposed
method 152.4 A Uniform-SRPT* 190.6 B FW-FIFO* 192.0 B Uniform-EDD* 233.7 C Uniform-FIFO 237.1 D Uniform-SLACK 275.3 E
Cycle time (h) Uniform-EDD 960.1 A Proposed method 1020.8 B Uniform-SRPT 1028.5 BC FW-FIFO 1050.2 C Uniform-SLACK 1270.3 D Uniform-FIFO 1325.1 E Throughput (lots) Proposed method 286.2 A FW-FIFO 279.8 B Uniform-SRPT 275.4 B Uniform-EDD 268.2 C Uniform-FIFO 262.6 C Uniform-SLACK 255.3 D Table 3
Statistic analysis of the average cycle time, average tardiness, and achievement percentage of due dates of MTO products Performance
index
PAC methods Average Results of Duncan testing Cycle time (h) Proposed method 726.5 A
Uniform-EDD 1016.4 B Uniform-SLACK 1039.5 BC Uniform-SRPT 1050.5 C
FW-FIFO 1100.9 D
Uniform-FIFO 1404.2 E Average Proposed method 2.2 A tardiness (h) Uniform-SLACK 112.4 B
FW-FIFO 162.0 C
Uniform-SRPT 171.2 C Uniform-EDD 172.7 C Uniform-FIFO 459.3 D Due date Proposed method 92.4 A achievement Uniform-EDD 51.1 B percentage Uniform-SLACK 47.5 C
(%) Uniform-SRPT 37.4 D
FW-FIFO 19.0 D
application of different order releasing rules. The proposed approachhas clear advantages in redu-cing the deviation of both cycle time and tardiness, bothof whichare extremely important in MTO products. Due dates are easier to estimate and thus control, while deviation of cycle time and tardiness
are small. Table 5 indicates that the proposed
approachfor MTS products only outperforms Uniform-SLACK discipline in average cycle time and throughput rate. The reason is that the order releasing rules of MTS products focus more on preventing the starvation of bottleneck worksta-tions rather than due date. However, the proposed approachdiffers little from Uniform-FIFO, Uni-form-EDD, and Uniform-SLACK in the results of
the Duncan test. Finally, Table 6 lists that the
performance of the proposed approach for MTS products is around the middle of all methods in terms of standard deviation of cycle time and throughput. Basically, the proposed approach outperforms other PAC approaches for MTO products, but displays no obvious advantage for MTS products.
6. Conclusion
This work developed a heuristic production activity control model to schedule and control wafer manufacturing in a hybrid wafer production environment (MTO and MTS). The proposed model considered due date and cycle time reduc-tion for MTO orders, and thus developed a rigid order release plan and dispatching control. The rigid release plan ensures that the order will not be released too early or late, while the dispatching control expedites late orders to allow timely delivery. However, for MTS orders, owing to the focus on filling the finished product buffer size to an appropriate level, a rigid order release plan and dispatching control is not important. Instead, the proposed model developed a method of releasing the orders so as to fill up remaining capacity (after the MTO orders have planned) without disturbing the released MTO orders. A comparison was drawn with other PAC methods, with the com-parative results showing that the proposed heur-istic model outperformed the other methods.
Table 4
Statistic analysis of standard deviation of cycle time and standard deviation of average tardiness of MTO products Performance
index
PAC methods Average Results of Duncan testing Standard deviation of Proposed method 72.4 A cycle time (h) FW-FIFO 103.1 B Uniform-FIFO 140.2 C Uniform-SRPT 284.4 D Uniform-SLACK 294.4 D Uniform-EDD 375.9 E Standard deviation of Proposed method 53.1 A average FW-FIFO 126.8 B tardiness (h) Uniform-FIFO 167.9 C Uniform-SRPT 231.9 D Uniform-SLACK 260.4 E Uniform-EDD 422.3 F Table 5
Analysis of average cycle time and through rate of MTS products
Performance index
PAC methods Average Results of Duncan testing Average cycle Uniform-EDD 913.4 A time (h) Uniform-SRPT 979.9 B FW-FIFO 1001.9 B Uniform-FIFO 1266.5 C Proposed method 1405.9 D Uniform-SLACK 1555.9 E
Through rate FW-FIFO 13.8 A (lots/week) Uniform-FIFO 13.5 AB Uniform-EDD 13.4 AB Uniform-SRPT 13.1 ABC Proposed method 12.9 BC Uniform-SLACK 12.5 C
Acknowledgements
The authors would like to thank the National Science Council of the Republic of China for financially supporting this research under Con-tract No. NSC 89-2213-E-159-020.
References
Adan, I.J.B.F., van de Wal, 1998. Combining make to order and make to stock. OR Spektrum 20, 73–81.
Bechte, W., 1988a. Theory and practice of load-oriented manufacturing control. International Journal of Production Research26 (3), 375–395.
Bechte, W., 1988b. Load-oriented manufacturing control. In: 23rd Annual APICS Conference Proceedings, Falls Church, VA, USA, pp. 148–152.
Bechte, W., 1994. Load-oriented manufacturing control just-in-time production for job shops. Production Planning & Control 5 (3), 292–307.
Blackstone, J.H., Phillips, D.T., Hogg, G.L., 1982. A state-of-the-art survey of dispatching rules for manufacturing job shop operations. International Journal of Production Research20 (1), 27–45.
Burman, D.Y., Gurrola-Gal, F.J., Nozari, A., Sathaye, S., Sitarik, J.P., 1986. Performance analysis techniques for IC manufacturing lines. AT&T Technical Journal 65 (4), 46–57.
Chang, S.-H., Chang, J., Li, R.-K., 2001. The integrated scheduling method for the wafer fabrication factories. Journal of the Chinese Institute of Industrial Engineering 18 (4), 59–72.
Chung, S.H., Yang, M.H., Cheng, C.M., 1997. The design of due date assignment model and the determination of flow time control parameters for the wafer fabrication factories. IEEE Transactions on Components, Packaging, and Man-ufacturing Technology 20 (4), 278–287.
Glassey, C.R., Resende, M.G.C., 1988a. Closed-loop job release control for VLSI circuit manufacturing. IEEE Transactions on Semiconductor Manufacturing 1 (1), 36–46.
Glassey, C.R., Resende, M.G.C., 1988b. A scheduling rule for job shop release in semiconductor fabrication. Operations ResearchLetters 7 (5), 213–217.
Goldratt, E.M., 1991. The Haystack Syndrome. North River Press Inc., Great Barrington, MA.
Graves, R.J., Konopka, J.M., Milne, R.J., 1995. Literature review of material flow control mechanisms. Production Planning & Control 6 (5), 395–403.
Huang, C.-L., Chang, S.-H., Li, R.-K., 2001. The literature review and analysis of the bottleneck shifting problems. Journal of the Chinese Institute of Industrial Engineering 18 (4), 73–81.
Kogan, K., Khmelnitsky, E., Maimon, O., 1998. Balancing facilities in aggregate production planning: Make-to-order and make-to-stock environments. International Journal of Production Research36, 2585–2596.
Lou, S.X.C., 1989. Optimal control rules for scheduling job shops. Annals of Operations Research 1 (17), 233–248. Lou, S.X.C., Kager, P.W., 1989. A robust production control
policy for VLSI wafer fabrication. IEEE Transactions on Semiconductor Manufacturing 2 (4), 159–164.
Lu, S.C.H., Ramaswamy, D., Kumar, P.R., 1994. Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants. IEEE Trans-actions on Semiconductor Manufacturing 7 (3), 374–388. Miller, D.J., 1990. Simulation of a semiconductor
manufactur-ing line. Communications of the ACM 33 (10), 99–108. New, C.C., Szwejczewski, M., 1995. Performance measurement
and the focused factory: Empirical evidence. International Journal of Operations & Production Management 15 (4), 63–79.
Nguyen, V., 1998. A multiclass hybrid production center in heavy traffic. Operations Research 46 (3), 13–25.
Park, P.S., Salegna, G.J., 1995. Load smoothing with feedback in a bottleneck job shop. International Journal of Produc-tion Research33 (6), 1549–1568.
Roderick, L.M., Philips, D.T., Hogg, G.L., 1992. A comparison of order release strategies in production control systems. International Journal of Production Research30 (3), 611–626.
Table 6
Statistic analysis of the standard deviation of cycle time and the standard deviation of throughput of MTS products
Performance index
PAC methods Average Results of Duncan testing Standard deviation of cycle time (h) FW-FIFO 105.2 A Uniform-FIFO 107.5 A Uniform-EDD 326.9 B Proposed method 329.8 B Uniform-SRPT 365.4 C Uniform-SLACK 425.4 D Standard deviation of throughput (lots) FW-FIFO 4.0 A Uniform-EDD 4.3 AB Uniform-FIFO 4.5 BC Proposed method 4.8 C Uniform-SRPT 5.5 D Uniform-SLACK 6.3 E
Samadhi, T.M.A., Hoang, K., 1995. Shared computer-inte-grated manufacturing for various types of production environment. International Journal of Operations & Pro-duction Management 15 (5), 95–108.
Sipper Jr., D., Bulfin, R.L., 1997. Production: Planning, Control, and Integration. McGraw-Hill, New York. Spearman, M.L., Zazanis, M.A., 1992. Pushand pull
produc-tion systems: Issues and comparisons. Operaproduc-tions Research 40 (3), 521–532.
Spearman, M.L., Woodruff, D.L., Hopp, W.J., 1989. CON-WIP: A pull alternative to kanban. International Journal of Production Research28 (5), 879–894.
Vollman, T.E., Berry, W.L., Whybark, D.C., 1997. Manufac-turing Planning and Control System. Irwin/McGraw-Hill, Homewood, IL/New York.
Wein, L.M., 1988. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing 1 (3), 115–130.
Wiendahl, H.P., 1995. Load-Oriented Manufacturing Control. Springer, Berlin.
Wiendahl, H.P., Glassner, J., Petermann, D., 1992. Applica-tions of load-oriented manufacturing control in industry. Production Planning & Control 3 (2), 118–129.
Williams, T.M., 1984. Special products and uncertainty in production/inventory systems. European Journal of Opera-tional Research15, 46–54.
Yan, H.S., Lou, S.S., Gardel, A., Deosthali, P., 1996. Testing the robustness of two-boundary control policies in semi-conductor manufacturing. IEEE Transactions on Semicon-ductor Manufacturing 19 (2), 285.
