Evaluation of thermal performance of all-GaN power module in
parallel operation
Po-Chien Chou, Stone Cheng
*, Szu-Hao Chen
Dept. of Mechanical Eng., National Chiao-Tung University, Hsinchu 300, Taiwan
h i g h l i g h t s
This work reveals the sorting process of GaN devices for parallel operation. The variations of ID max, RON, VP, and gmwith temperature are established.
The temperature-dependence parameters are crucial to prevent hot spots generation. Safe working operation prevents thermal runaway and hottest cell destruction.
a r t i c l e i n f o
Article history:
Received 2 December 2013 Accepted 24 May 2014 Available online 2 June 2014 Keywords:
GaN HEMTs
Power semiconductor devices Power module
Parallel operation Static parameters
a b s t r a c t
This work presents an extensive thermal characterization of a single discrete GaN high-electron-mobility transistor (HEMT) device when operated in parallel at temperatures of 25 Ce175C. The maximum
drain current (ID max), on-resistance (RON), pinch-off voltage (VP) and peak transconductance (gm) at various chamber temperatures are measured and correlations among these parameters studied. Un-derstanding the dependence of key transistor parameters on temperature is crucial to inhibiting the generation of hot spots and the equalization of currents in the parallel operation of HEMTs. A detailed analysis of the current imbalance between two parallel HEMT cells and its consequential effect on the junction temperature are also presented. The results from variations in the characteristics of the parallel-connected devices further verify that the thermal stability and switching behavior of these cells are balanced. Two parallel HEMT cells are operated at a safe working distance from thermal runaway to prevent destruction of the hottest cell.
© 2014 Elsevier Ltd. All rights reserved.
1. Introduction
Improvements in GaN-on-Si process technology in recent years have enabled large-area GaN HEMT power devices to be fabricated [1,2]. The availability of large-area devices does not ensure the economic viability of their mass production. As wide band-gap semiconductors, the die cost increases drastically with the size of the device because growth non-uniformity increases and process-ing yield declines[3,4]. This effect is the main reason for fabricating GaN power modules by bonding multiple lower-current cells in parallel to yield the desired high current rating. Previous studies have shown that the device power handling capabilities are dependent directly on maximum operating junction temperature [5,6]. We presented the methodology to raise the rating current of our GaN HEMT-based modules and our newly developed 200 V/
45 A GaN module with the same package size as the 600 V 50 A IGBT power module. Proper thermal management is critical because localized self-heating effects under high power operation significantly impact device's performance and reliability. The use of infrared microscopy and electrical measurements (RONand ID max) are employed to produce accurate channel to mounting tempera-ture differentials. Most applications require that the junction temperature be maintained below 175C to ensure reliability[7,8]. The failure rate increases very rapidly about this temperature[9]. The junction temperature substantially affects influences switching characteristics and, therefore, dynamic current sharing. Several SiC-based power modules have been developed[10e13]. However, the performance of individual GaN HEMTs that are operated in parallel in a module has not been examined. Analysis of parallel operation of HEMTs in a module is difficult because access to individual de-vices is impossible unless they are un-encapsulated using infrared thermal imaging [14,15]. Accordingly, this study investigates the thermal parameters that influence static and dynamic current * Corresponding author.
E-mail address:stonecheng@mail.nctu.edu.tw(S. Cheng).
Contents lists available atScienceDirect
Applied Thermal Engineering
j o u r n a l h o m e p a g e : w w w . e l s e v i e r . c o m/ l o ca t e / a p t h e r m e n g
http://dx.doi.org/10.1016/j.applthermaleng.2014.05.081 1359-4311/© 2014 Elsevier Ltd. All rights reserved.
sharing and, therefore, on junction temperature. The rest of this paper is organized as follows. The parameters that critically in flu-ence the feasibility of the parallel-connected HEMTs are
experi-mentally examined [16,17]. The variations of maximum drain
current (ID max), on-resistance (RON), pinch-off voltage (VP) and peak transconductance (gm) with temperature in the range 25Ce175C are obtained to elucidate the scaling of the device parameters [18,19]. The dependence of key transistor parameters on tempera-ture is determined to support reliable parallel operation over a wide range of temperatures. Finally, analyses of the switching behavior of two parallel devices reveal a positive temperature co-efficient of resistance tends to inhibit the generation of hot spots and to equalize the currents[20e22]. The results of the switching operation of devices further verify that these cells are thermally Fig. 1. Test module with four GaN HEMT chips mounted on a common source pad. A
parallel drain leads extended to the upper, and a gate leads extended to the lower. The circuit layout is designed for die-level sorting.
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 I tn err u C ecr uo S ot ni ar D D (A )Drain to Source Voltage VDS (V) 25 ºC
175 ºC Single HEMT cell
VGS= 0 V
(b)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 I tn err u C ecr uo S ot ni ar D D (A )Drain to Source Voltage VDS (V) 25 ºC
175 ºC Two paralleled HEMT cells
VGS= 0 V
balanced with parallel compensation during switching transitions Fig. 1.
2. Packaging design of a ceramics-based GaN power module Fig. 2shows that each direct bond copper (DBC) substrate of a GaN power module contains an array of 24 GaN HEMT cells that are arranged in two rows of four chips. The chips are bonded to a common AlN substrate using sintered silver nano-particles and then wire-bonded to the electrical interconnect board. The DBC substrate provides good coefficients of thermal expansion (CTE) matching and a path for efficient heat transfer that removes heat from GaN HEMTs. According to the developed thermal stability criterion, favorable heat sharing (using a ceramic heat sink and the minimization of thermal resistance between HEMTs) causes the hottest cell to heat its surrounding cells, increasing their share of HEMT's drain current, greatly reducing the tendency for thermal runaway[23]. Additionally, unequal cooling of parallel HEMT cells can result in further current imbalance in the module since the GaN
HEMT on-state and switching characteristics depend on
temperature.
3. Static and transient behavior of GaN HEMTs at various temperatures
Following the characterization of individual dies, two cells were in the module were selected for parallel operation based upon
matching output characteristics (IDeVDS) and transfer characteris-tics (IDeVGS). Current imbalance negatively affects the operation of parallel HEMTs. If the thermal resistance is constant and unaffected by temperature, then the junction temperatures of the parallel HEMTs may differ. To analyze current sharing, the effect of tem-perature must be analyzed in a steady state. The thermal perfor-mance of HEMTs was obtained for both single and parallel cells at various base-plate temperatures. The module was placed in a
thermostatic chamber at ambient temperatures (TA) of
25 Ce175C. For GaN HEMT, 175 C yields the highest channel
temperature. At each temperature, the DC IeV curves were
measured, and maximum drain current (ID max), on-resistance (RON), transconductance (gm), and pinch-off voltage (VP) were recorded. The experimental setup involved a Keithley 2601A, which operated the gate terminal and a Keithley 2651A, which operated the drain terminal, for electrical measurement. The current pulse widths were limited to minimize self-heating of the chips, which was less than 0.4C at the maximum current pulse. These electrical parameters were measured by simultaneously applying drain and gate biases at the sub-microsecond time-scale. Under this condi-tion, dissipated power was negligible, and the channel temperature equaled the ambient temperature based on the assumption that the thermal conductivities of both GaN and Si were linear in the tem-perature range of 25 Ce175C. In each case, the least-squares curve that isfitted to the experimental data is plotted. The static and dynamic characteristics were extracted to reveal how these parameters scale-up in parallel GaN HEMTs.
(a)
ID MAX(A) = -0.0042 TA+ 1.5042 ID MAX(A) = -0.0044 TA+ 1.4945 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 25 50 75 100 125 150 175 tn err uc ni ar d mu mi xa MI D m ax (A ) Temperature TA(ºC)(b)
1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 25 50 75 100 125 150 175 I tn err uc ni ar d mu mi xa M D m ax (A) Temperature TA (ºC)ID MAX(A) = - 0.0084 TA+ 2.9211 (Experiment )
ID MAX(A) = - 0.0085 TA+ 2.9815 (Calculation )
Fig. 3. Extracted ID maxof (a) single and (b) parallel HEMTs over a range of
tempera-tures, TA, from 25C to 175C. The maximum drain current ID max(drain current at
VDS¼ 5 V and VGS¼ 0 V) declined as the ambient temperature (TA) increased.
(a)
Ron(Ω) = 0.0175 TA+ 2.3703 Ron(Ω) = 0.0164 TA+ 2.5083 2.6 3 3.4 3.8 4.2 4.6 5 5.4 5.8 25 50 75 100 125 150 175 On re si st an ce RON (Ω ) Temperature TA(ºC)(b)
1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 25 50 75 100 125 150 175 Temperature TA (ºC) RON(Ω) = 0.0087 TA+ 1.2516 (Experiment ) RON(Ω) = 0.0085 TA+ 1.2165 (Calculation ) On re si st an ce (Ω )Fig. 4. Extracted RONof (a) single and (b) parallel HEMTs over a range of temperatures,
3.1. Measurements of maximum drain current (ID max) and on-resistance (RON)
Fig. 2plots the forward IDeVDScharacteristics of both single and parallel GaN HEMT cells at temperatures from 25C to 175C. The
IDeVDS plots were obtained by sweeping VDS from 0 V to VDS
(max¼ 5 V) with VGSset to 0 V. InFig. 2, ID maxis defined as IDat VDS¼ 5 V and VGS¼ 0 V, and RONis defined as the reciprocal of the slope of IDeVDSin the linear region at VGS¼ 0 V.Fig. 3plots ID maxfor a single HEMTcell and for two parallel HEMTcells at temperatures from 25C to 175C. The mean square slope of ID maxas a function of TA is0.42%/C and0.44%/C for the two HEMT cells.Fig. 3(b) com-pares the variation of ID maxwith temperature for two parallel HEMT cells with the calculated value for single devices. The experimental and calculated ID maxfor two HEMTs slightly differ.Fig. 4also plots the obtained on-resistances of both single and parallel cells at tempera-tures from 25C to 175C. As expected, the on-resistance, RON, versus TA, has a slope of 1.64%/C and 1.75%/C for the two devices, respec-tively. The temperature coefficient was positive, indicating that, as temperature increased, ID maxdeclined and RON increased. With a good thermal path between two parallel HEMTs, the positive tem-perature coefficient reduces the current in the hottest cell and forces more current toflow in the cooler cell, avoiding thermal runaway and destruction of the device. This process provides an essential thermal equilibrium that enables the two parallel cells to function reliably simplifying parallel operation. The on-resistance of two parallel HEMT cells was almost half of that of the single HEMT cell at the same ambient temperature. On-resistance RONincreased with TAat 0.87%/ C, andFig. 4(b) presents excellent agreement between the experi-mental and calculated results.
3.2. Measurement of pinch-off voltage (VP) and peak transconductance (gm)
Fig. 5 plots the IDeVGS characteristics of single and parallel
HEMTs. The IDeVGS plots were obtained by sweeping VGS
from10 V to VGS(max¼ 0 V) with VDSset to 5 V. These HEMTs have a positive temperature coefficient throughout their operating range of temperatures and the currents in the cells in parallel are therefore expected to be equalized. The power MOSFET has a small region with a negative temperature coefficient where there no current-equalization occurs [24]. Operation within this region generates potential hot spots within the module and limits its current-carrying capacity.Fig. 6shows that the pinch-off voltage shift increases with ambient temperature in both the single and parallel cells. VPwas calculated by extrapolating IDin the IDversus VGSgraph to ID¼ 1% of the room temperature ID max, at VDS¼ 10 V, and taking the corresponding VGSvalue as VP. VPwas obtained at 1% of ID maxrather than the typical 1 mA/mm leakage current because the leakage current depended strongly on temperature depen-dence because of the presence of defects. The changes in VPwith temperature for the two HEMT cells were 0.13%/C and 0.16%/C, respectively. The experimental results thus obtained during parallel operation depend on temperature in the same way.Fig. 6(b) reveals that the experimentally determined temperature increase of 0.14%/ C in the parallel HEMTs did not significantly differ from the calculated value.Fig. 7plots the measured peak transconductance (gm) as a function of temperature. Thefigure indicates that tem-perature was a significantly negatively related to gmin both single and parallel cells. The change in gmwith temperature was0.23%/
(a)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -10 -9.5 -9 -8.5 -8 -7.5 -7 -6.5 -6 -5.5 -5 It ner ru C ec ru o S ot ni ar D D (A )Gate to Source Voltage VGS (V)
Single HEMT cell
25 ºC 175 ºC VDS= 5 V
(b)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 -10 -9.5 -9 -8.5 -8 -7.5 -7 -6.5 -6 -5.5 -5 25 ºC 175 ºC VDS= 5 V It ner ru C ec ru o S ot ni ar D D (A )Gate to Source Voltage VGS (V)
Two paralleled HEMT cells
Fig. 5. Transfer characteristics (IDeVGS) of (a) single and (b) parallel HEMT cells.
(a)
-7.55 -7.5 -7.45 -7.4 -7.35 -7.3 25 50 75 100 125 150 175 Pi nc h-off vo lt ag e VP (V ) Temperature TA (ºC) ID= 1% ID MAX Single VP(V) = 0.0013 TA- 7.529 Single VP(V) = 0.0016 TA- 7.5868
(b)
-7.55 -7.5 -7.45 -7.4 -7.35 -7.3 -7.25 25 50 75 100 125 150 175 P in ch -o ff vo lt ag e VP (V ) Temperature TA (ºC) ID= 1% ID MAX VP(V) = 0.0014 TA- 7.5429 (Experiment ) VP(V) = 0.0014 TA- 7.5552 (Calculation )Fig. 6. VPof (a) single and (b) parallel HEMTs over a range of temperatures, TA, from
C for the single HEMT cell and 0.39%/C for the two parallel HEMT cells. Notably, the calculated and experimental gm values differed slightly owing to trapping at or near the surface. The par-allel HEMT cells have a larger gmthan the single HEMT cell. This increase in gmimpacts the switching speed of the HEMT cell when they are in parallel.
4. Dynamic characterization and analysis of two parallel HEMT cells
Fig. 8displays the switching performance when the circuit was tested using a gate pulse. The operating temperature was swept
from room temperature to 175 C in the same thermostatic
chamber that was used to perform the static IeV characterization. Switching is carried out at the frequencies up to 100 kHz and a 20% duty cycle. Since low current densities and high voltages can result in thermal runaway in parallel operation, VGS¼ 0 V is used for
(a) 0.2 0.4 0.6 0.8 25 50 75 100 125 150 175 g ec nat cu dn oc sn art ka e P m (S ) Temperature TA (ºC) Single gm(S) = - 0.0023 TA+ 0.7453 Single gm(S) = - 0.0023 TA+ 0.7301 (b) 0.4 0.6 0.8 1 1.2 1.4 1.6 25 50 75 100 125 150 175 g ec nat cu dn oc sn art ka e P m (S ) Temperature TA (ºC) gm(S) = - 0.0039 TA+ 1.2534 (Experiment ) gm(S) = - 0.0045 TA+ 1.4587 (Calculation )
Fig. 7. Dependence of transconductance on temperature. Transconductance decreases with as temperature increases for both (a) single and (b) parallel cells.
S G S D G D HEMT cell 1 HEMT cell 2 5 V RG CG CG RG -10 V~ 0 V + + Power supply Signal generator
Fig. 8. Drive circuit.
(a)
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 0 100 200 300 400 500 600 700 T urn o n c urre nt (A ) Time (ns)(b)
-0.1 0.1 0.3 0.5 0.7 0.9 3,650 3,675 3,700 3,725 3,750 3,775 3,800 Tu rn o ff c ur re nt (A ) Time (ns)Fig. 9. (a) Turn-on and (b) turn-off waveforms of two parallel HEMT cells at room temperature, 25C.
(a)
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 0 100 200 300 400 500 600 700 T urn o n c urre nt (A ) Time (ns)(b)
-0.1 0.1 0.3 0.5 0.7 0.9 3,650 3,675 3,700 3,725 3,750 3,775 3,800 T ur n o ff cu rr en t (A ) Time (ns)Fig. 10. (a) Turn-on and (b) turn-off waveforms of two parallel HEMT cells at an operating temperature of 175C.
on, and VGS¼ 10 V is used for turn-off with VDSheld at 5 V. Each cell has its own gate resistance of 22
U
and gate capacitance of 10 nF to stabilize the parallel operation during switching. The power test circuit must be symmetrical. The loop inductance in each test cir-cuit must be as small as possible to minimize voltage overshoot when the device is turned off. The current rating of the assembly must not exceed 70%e80% of the total maximum current of the cells to compensate for the inevitable parameter mismatch between the cells. Even with thermal de-rating, a thermocouple is required to ensure that the individual operating temperatures are always close to each other[25].Like SiC MOSFETs, GaN HEMT devices have a positive temper-ature coefficient in the on-resistance characteristics, which enables parallel operation.Figs. 9 and 10plot the dynamic switching be-haviors during the parallel operation of two HEMT cells. Based on the assumption that the base temperatures of the heat sink in the two packages are equal, and their thermal resistances are similar, the results of the switching operation may be regarded as effec-tively indicating temperature variation. Notably, the current is shared equally between the HEMT cells under initial transient conditions during turn-on and turn-off. Apparently, mismatching is minimal, and no oscillation is observed in current. Thefigure shows a very close waveform matching at turn-on. Equal current distri-bution of paralleled cells is essential to maintaining close matching of the junction temperatures of the individual cells and to prevent possible thermal runaway.Figs. 9(b) and 10(b)apparently reveal that current mismatching is minimal and remains essentially con-stant until each cell approaches the steady state. The test circuit must be symmetric with identical connection impedances of each cell.
Fig. 11presents the repetitive switching of two parallel HEMT cells at room temperature, 25C. Thefigure clearly demonstrates that favorable current sharing was achieved in the HEMT pair when the junction temperatures were stabilized. The current waveforms are super-imposed, and their similarity limits the current mismatch between the HEMTs to only 0.2%, mainly because of the difference between the temperature-dependent parameters affects the dy-namic behavior of the two parallel HEMT cells. The parasitic ele-ments that are connected into circuit also contribute to this effect. In spite of the mismatches between the parameters of the HEMTs, a favorable current distribution in the two parallel HEMT cells is obtained using series gate resistors. The current imbalance, which causes variations in the junction temperatures of the HEMTs, is acceptable, possibly because of the similar driving conditions, the careful design of the common package, and the special attention that was paid to improving heat sharing among the HEMT cells. The satisfactory experimental results verify the feasibility of the parallel operation of discrete GaN HEMTs in which current can be shared between two parallel HEMT cells.
5. Conclusions
To justify the use of GaN technology in high-power, high-tem-perature applications, device performance must be evaluated across a wide range of temperatures to support the development of multi-chip power modules. This study examined thermal effects on the IDeVDSand IDeVGS characteristics of both single and parallel GaN HEMTs at temperatures from 25C to 175C. The highly uni-form static current sharing between the cells prevents overloading of the device by an excessive current. The effects of temperature on maximum drain current (ID max), on-resistance (RON), pinch-off voltage (VP) and peak transconductance (gm) are measured. The variations of ID max, RON, VP, and gmwith temperature are estab-lished for both single and parallel operations. The analyses of transient behavior revealed that two parallel HEMTs effectively
(a)
0.00 1.00 2.00 3.00 4.00 5.00 6.00 0 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 5,000 V eg atl o V ec ru o S ot ni ar D DS (V ) Time (ns) -15.00 -10.00 -5.00 0.00 5.00 0 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 5,000 V eg atl o V ec ru o S ot et a G GS (V ) Time (ns) -0.10 0.10 0.30 0.50 0.70 0.90 1.10 0 1,000 2,000 3,000 4,000 5,000 It ner ru C ec ru o S ot ni ar D D (A ) Time (ns)(b)
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1,500 1,600 1,700 1,800 1,900 2,000 2,100 T ur n o n cu rr en t (A ) Time (ns)(c)
-0.1 0.1 0.3 0.5 0.7 0.9 3,620 3,660 3,700 3,740 3,780 T urn o ff c urre nt (A ) Time (ns)Fig. 11. Operating waveforms of two parallel HEMTs with a common gate drive. (a) Complete switching period. (b) Zoom-in during turn-on. (c) Zoom-in during turn-off.
share current during inductive switching and maintain this sharing up to a high temperature of 175C. In spite of the mismatch be-tween temperature-dependent parameters, the current sharing of the two parallel HEMT cells is satisfactory. The current imbalance, which is responsible for variations in the junction temperatures of the HEMTs, is acceptable when the parameters are appropriately sorted. Experimental results further verify the operation of parallel-connected HEMTs at a safe working distance from thermal runaway or destruction of the hotter cell.
Acknowledgements
This work was supported by the MOEA project 101-EC-17-A-05-S1-154, and MOST project 102-2221-E-009-074, Taiwan, R.O.C.. The authors would like to thank Prof. Edward Yi Chang of NCTU for supporting GaN devices, and Edward Kuo of Advanced Precision Testing Technology CO., Ltd for their very helpful suggestions and technical support.
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