Ambipolar Schottky-barrier TFTs

(1)

264 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002

Ambipolar Schottky-Barrier TFTs

Horng-Chih Lin, Senior Member, IEEE, Kuan-Lin Yeh, Tiao-Yuan Huang, Fellow,

Ruo-Gu Huang, Student Member, IEEE, and Simon M. Sze, Life Fellow, IEEE

Abstract—A novel Schottky-barrier metal-oxide-semiconductor thin-film transistor (SBTFT) was successfully demonstrated and characterized. The new SBTFT device features a field-induced-drain (FID) region, which is controlled by a metal field-plate lying on top of the passivation oxide. The FID region is sandwiched be-tween the silicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. The device is thus capable of ambipolar opera-tion. Excellent ambipolar performance with on/off current ratios over 106for both p- and n-channel operations was realized simulta-neously on the same device fabricated with polysilicon active layer. Moreover, the off-state leakage current shows very weak depen-dence on the gate-to-drain voltage difference with the FID struc-ture. Finally, the effects of FID length are explored.

Index Terms—Ambipolar, field-induced drain, Schottky barrier, TFT.

I. INTRODUCTION

S

CHOTTKY barrier (SB) MOS transistor, which employs metallic source and drain [1], eliminates the source/drain (S/D) implantation and subsequent annealing steps. It is there-fore simpler in processing and inherently suitable for low tem-perature processing. It is also excellent in short-channel effect control, due to the inherently shallow silicide junction [2], [3]. Moreover, it is also capable of bichannel operation [4]. With these advantages, it thus appears to be quite attractive for appli-cations to nanoscale devices as well as large-area electronics.

Conventionally, SB MOS devices employ a self-aligned sili-cidation (salicide) process to form the silicided S/D. Gate side-wall spacers are required to avoid bridging between the gate electrode and the silicided S/D [1]–[7]. However, the resultant SB MOS transistors generally suffer from severe leakage cur-rent and poor on/off curcur-rent ratio. This is due to the much larger junction leakage current inherent in Schottky diodes, compared to p-n junction diodes. Another shortcoming is that it is almost impossible to fabricate SB MOS transistors with acceptable n-and p-channel characteristics simultaneously for ambipolar op-eration [4]. This is due to the constraint imposed by the fixed barrier height of the Schottky contact of a given metallic layer.

Manuscript received August 15, 2001; revised October 15, 2001. This work was supported by the National Science Council, Taiwan, R.O.C., under Con-tract NSC90-2721-2317-200. The review of this paper was arranged by Editor C.-Y. Lu.

H.-C. Lin and S. M. Sze are with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).

K.-L. Yeh and R.-G. Huang are with the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.

T.-Y. Huang is with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. and also with National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(02)00819-5.

In this work, we have demonstrated a novel poly-Si Schottky barrier thin-film transistor (SBTFT) device that can effectively improve the on/off current [8]–[11]. The new device employs a field-plate (or subgate) to induce an electrical drain extension in the active poly-Si layer. The unique field-induced drain (FID) feature reduces the off-state leakage effectively while main-taining a reasonable on-current value, resulting in significant improvement in the device performance. Excellent ambipolar operations were demonstrated, for the first time, on the same SBTFT with FID structure.

II. DEVICEFABRICATION

Detailed fabrication steps have been previously described [8], [9]. Fig. 1(a) and (b) show key processing steps for devices with the conventional and FID structure, respectively. Briefly, Si wafers capped with a thermal oxide layer were used as the starting substrates. A 50-nm amorphous Si active device layer was deposited at 550 C by low-pressure chemical vapor depo-sition (LPCVD), and subsequently crystallized by a solid-phase re-crystallization (SPC) treatment at 600 C in N for 24 h. After patterning the active device region, a 20-nm CVD gate oxide layer and a n poly-Si (200 nm) layer were deposited. The n poly-Si gate layer was delineated to form the main gate. Next, a 200-nm CVD oxide layer was deposited, followed by lithographic step to define the offset regions for the new TFT device with FID [Fig. 1(b)] Self-aligned sidewall spacers were simultaneously formed for the conventional devices during the reactive-ion-etching step used to define the offset regions in the new devices [Fig. 1(a)] Next, silicided S/D was formed by a self-aligned silicidation (salicidation) treatment, by first de-positing a thin Co layer (15 nm, capped with 30 nm of TiN), followed by a rapid-thermal annealing step (550 C, 30 s) and a wet etching step in H SO :H O to remove the non-reacted metals. It should be noted that neither the channel nor the S/D region received any deliberate doping, so no post-im-plant annealing step was required. Wafers then followed a stan-dard back-end processing to completion. The metal subgate in the new structure was formed simultaneously with the regular metal patterning, so no extra processing steps were required. A plasma treatment at 250 C in NH for 1 h was performed be-fore measurements.

III. OPERATION OFSBTFT WITHFIELD-INDUCEDDRAIN

The new structure [Fig. 1(b)] features an undoped Si active channel, a top metal field-plate (i.e., the subgate), and Schottky S/D. For device operation, a fixed bias is applied to the subgate to form a FID extension under the subgate region. So depending on the subgate bias polarity, the device can function as either an

(2)

Fig. 1. Key fabrication steps for SBTFT devices with (a) conventional and (b) the new structure with field-induced drain (FID).X in (b) is the length of FID region in the channel.

n-channel transistor with positive subgate bias, or a p-channel transistor with negative subgate bias.

The new device is structurally similar to conventional SB MOSFETs [1]–[7], except that a FID extension is created between the channel and the Schottky drain. The FID extension serves to reduce the undesirable off-state leakage that has plagued all previous SB MOSFETs. Concomitantly, the new device can also be viewed as MOSFETs with FID [12], [13], with the exception that the heavily-doped S/D region is now replaced by Schottky S/D. The new structure thus retains all the advantages of FID such as low off-state leakage and low junction leakage. Finally, the use of Schottky S/D can greatly reduce processing steps (i.e., implant and subsequent annealing), and allows ambipolar operation, which further simplifies CMOS process integration.

IV. RESULTS ANDDISCUSSION

A. Characteristics of Ambipolar Operation

Fig. 2 depicts the ambipolar operation of the FID SBTFT [8]. Excellent on/off current ratios of over 10 are achieved for both n- and p-channel operations under proper bias conditions. It is interesting to note here that the turn-on behavior is somewhat retained for n-channel operation even when a zero sub-gate bias is applied. Meanwhile, the off-state leakage in p-channel oper-ation is higher for subgate bias of zero volt than that of 50 V. These phenomena will be addressed later.

Fig. 3 compares the ambipolar (i.e., both n- and p-channel) subthreshold characteristics of the conventional and FID SBTFTs. It can be seen that SBTFT with conventional structure exhibits very poor performance for both p- and n-channel modes of operation [Fig. 3(a)]. On/off current ratios are around

Fig. 2. Ambipolar subthreshold characteristics of a FID SBTFT.V is 5 and

05 V for n- and p-channel operations, respectively.

or less than 10 . Moreover, the strong gate-induced drain leakage (GIDL)-like leakage current results in the V-shaped current-voltage (I–V) curves. In contrast, superior p- and n-channel device performances are simultaneously realized on the SBTFT with FID structure under proper sub-gate biases. As shown in Fig. 3(b), on/off current ratio as high as is observed for both n- and p-channel modes of operation. In ad-dition, the GIDL-like leakage current is effectively suppressed. It should be emphasized that these characteristics are obtained on the same device by simply changing the polarity of the sub-gate bias.

(3)

Fig. 3. Typical p- (V = 05 V) and n-channel (V = 5 V) subthreshold characteristics of SBTFT with (a) conventional and (b) FID structure.L=W =

2=20 m/m. X in (b) is 1 m.

Output characteristics of the two types of devices are shown in Fig. 4. It is seen that the implementation of FID in the de-vice improves the on-state currents for both p- and n-channel operations. The improvements can be ascribed to the elimina-tion of the ungated channel regions existing under the sidewall spacers in the conventional devices. Since the bottom width of the sidewall spacers ( nm) is larger than the silicide thick-ness ( nm), the silicided S/D portion does not reach the channel region beneath the main-gate, leading to an increase in the parasitic resistance along the channel in the conventional device. This feature is quite different from that of SB MOS de-vices reported previously [4]–[7], in which the silicided S/D re-gion overlaps with the gate. Although a self-aligned sidewall spacer also exists at the source side of our new device, how-ever, the overlying metal subgate effectively covers the channel region underneath the spacer, so the parasitic resistance is re-duced when a high subgate bias is applied. This phenomenon will be addressed in more detail later.

B. Leakage Mechanisms

As mentioned earlier, the GILD-like leakage current is also effectively eliminated, further highlighting the effectiveness of FID. A more detailed study on the conduction mechanisms of the leakage current was reported elsewhere [11]. Here, we briefly present qualitative conduction mechanisms with the band diagrams shown in Fig. 5 to explain the effectiveness of FID in reducing the leakage. In the figure, we concentrate only on the n-channel operation. Similar results could also be deduced for p-channel operation. For the conventional device, a high electric field is developed in the channel region near the drain side [Fig. 5(a)]. Such a high field would enhance the field emission as well as thermionic emission of holes from the silicided drain. On the other hand, formation of the FID with the band diagram shown in Fig. 5(b) tends to suppress the emission of holes from the drain. As a result, GIDL-like leakage could be eliminated.

C. Effects of FID Length

The n- and p-channel subthreshold characteristics for devices with a fixed main-gate length (e.g., 3 m) but different ranging from 1 to 10 m are shown in Figs. 6 and 7, respec-tively. It can be seen that the leakage currents in the off-state and the subthreshold regions are essentially independent of the FID length. On the other hand, the on-state current increases as becomes shorter. This trend is reasonable, since the par-asitic resistance decreases with decreasing . Nevertheless, the dependence on is much stronger for the p-channel op-eration.

In Figs. 8 and 9, the drain currents for n- and p-channel oper-ations are shown as a function of the subgate voltage. Devices with different ranging from 1 to 6 m were characterized. Drain voltages were 3 and 3 V for n- and p-channel opera-tions, respectively. Two main-gate voltages were mea-sured for each operation mode, i.e., 10 and 0 V for the n-channel and 10 and 0 V for the p-channel, to represent the “on” and “off” states, respectively. When a large was applied, the I-V curves in Figs. 8 and 9 could be regarded as the opera-tion of FETs with the metal field-plate (or the subgate) serving as the transistor gate, while became the transistor channel length, since the channel region underneath the main-gate acted simply as a “pseudo source”.

extracted from the “on” I–V curves of Figs. 8 and 9 is shown in Fig. 10 as a function of . It is seen that the ab-solute value of in long-channel (i.e., large ) devices is larger for p-channel operation mode. In addition, the short-channel effects (i.e., roll-off shown in Fig. 10 and sub-threshold punchthrough shown in Figs. 8 and 9) are much more severe for n-channel operation.

The asymmetrical values for long-channel p- and n-channel operations can be ascribed to the existence of positive fixed charge normally observed at the oxide/Si channel interface [14]. However, this alone can not explain the asymmetrical short-channel effects shown in Fig. 10. Since n-channel operation shows much more severe short-channel effects, it strongly suggests that the background doping in our channel is n-type! After carefully reviewing the process history used in the device fabrication, we indeed found that the solid-phase crystallization (SPC) step was performed in a furnace previously used for n diffusion. This reasonably explains the n-type background doping found in the channel, and illustrates the importance of carefully controlling the process environment, as it could significantly influence the device operation.

The n-type background doping in the channel can also ex-plain the results shown in Figs. 6 and 7. As mentioned above, the on-state current for p-channel operation shows a much stronger dependence on the FID length, compared to the n-channel op-eration. This is because during the p-channel operation, con-duction of holes in the offset channel is confined in the narrow inversion layer near the channel/oxide interface. In contrast, cross-sectional width for conduction of electrons in the offset channel during n-channel operation is wider due to the n-type background doping. The former case thus shows a stronger de-pendence on the FID length.

(4)

Fig. 4. Typical p- and n-channel output characteristics of SBTFT with (a) and (b) conventional and (c) and (d) FID structure.L=W = 2=20 m/m. X in (c) and (d) is 1m.

Fig. 5. Band diagrams for n-channel operation of SBTFTs with (a) conven-tional structure and (b) FID at off-state (i.e.,V = 0; V = V , and

V 0).

Current ratios between the “on” and “off” states shown in Figs. 8 and 9 are depicted in Fig. 11. Owing to the severe short-channel effects and the n-type background short-channel doping men-tioned above, ratio much larger than unity is retained at zero sub-gate bias in n-channel operation. This is consistent with the results shown in Fig. 2.

For long-channel (i.e., large ) devices, the drain current becomes nonsensitive to the main-gate bias, and the ratio ap-proaches unity as the sub-gate bias becomes negative and pos-itive for - and p-channel operations, respectively. Band

dia-Fig. 6. Typical n-channel (V = 1 V) subthreshold characteristics of SBTFT devices with variousX (e.g., 1, 5, and 10 m). L=W = 5=20 m/m.

grams illustrated in Fig. 12 can be used to explain this phenom-enon. In the figure, we concentrate only on the p-channel opera-tion, although similar results can also be deduced for n-channel operation. When the subgate bias becomes positive, a strong electric field will be developed near the drain side. As a result, electron emission from the drain will be the dominant leakage mechanism, while the condition in the channel region

(5)

Fig. 7. Typical p-channel (V = 01 V) subthreshold characteristics of SBTFT devices with various X (e.g., 1, 5, and 10 m). L=W =

5=20 m/m.

Fig. 8. Effects of the subgate bias andX on the n-channel operation of FID SBTFTs (L=W = 5=20 m/m).

Fig. 9. Effects of the subgate bias andX on the p-channel operation of FID SBTFTs (L=W = 5=20 m/m).

Fig. 10. V extracted from the “on” state I–V curves of Figs. 8 and 9 as a function ofX .

Fig. 11. Ratio between the “on” and “off” state currents (Figs. 8 and 9) for (a) n- and (b) p-channel operations.

underneath the main-gate (or the “pseudo source”) has negli-gible effect. This could well explain why the off-state leakage is higher for p-channel operation with zero subgate bias than that with 50 V.

Finally, it should be pointed out that the drive performance of the proposed ambipolar device is not optimized in our experi-ment. This is because of the high barrier height ( 0.5 eV) for both p- and n-channel operations used in our devices. Improve-ment could be made specifically for either p- or n-channel op-erations by adopting silicide materials with low barrier-height. For examples, ErSi and PtSi can be used for n- and p-channel operations, respectively. However, such improvement in driv-ability is achieved by compromising the capdriv-ability of bi-channel operation.

(6)

(a)

(b)

Fig. 12. Band diagrams for p-channel operation (V = 03 V) of FID SBTFT with a high positive subgate bias.

V. CONCLUSION

In summary, a novel implantless SBTFT with silicided S/D and FID extension capable of ambipolar operation is successfully demonstrated and compared with conventional SBTFTs. We found that while the conventional SBTFTs depict large GIDL-like leakage current and low on/off current ratio of less than 10 , the new devices depict GIDL-free current characteristics with on/off current ratio as high as 10 . This is achieved for both n- and p-channel modes of operation on the same device.

The proposed structure and its fabrication possess many ad-vantages. First of all, all dopings (i.e., including the channel and S/D) and accompanying annealing steps are eliminated alto-gether, resulting in a much simplified overall process flow which is very suitable for low-temperature manufacturing. Second, the new structure is compatible with metal-gate processing, making feasible for the first time a fully implantless CMOS process, if metallic material such as TiN is adopted as the gate material. Third, no additional masking or processing steps is needed in the new structure. This is because the silcidation for forming the Schottky S/D can be performed simultaneously during the reg-ular salicidation step, while the metal subgate can be formed si-multaneously with metal interconnect. Fourth, the fully implant-less process coupled with the ambipolar operation can greatly simplify CMOS process integration, resulting in an extremely low mask-count CMOS flow that is previously impossible. Fi-nally, ambipolar modes of operation with superior characteris-tics are demonstrated for the first time, due to the unique device structure. The low current required for the subgate bias also al-lows the use of on-chip bias generator to simplify external power supply.

We also found that the channel region underneath the sub-gate has a lower value and depicts much more severe SCE for n-channel operation. These trends are ascribed to the

posi-tive fixed charges at the oxide/channel interface and the n-type background channel doping, the latter could be explained by the prior furnace history used in the SPC step of the device fabrica-tion.

ACKNOWLEDGMENT

The authors would like to thank their colleagues at National Nano Device Laboratories for their assistance in device fabrica-tion.

REFERENCES

[1] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-ef-fect transistor using Schottky barrier contacts for source and drain,”

Proc. IEEE, pp. 1400–1401, 1968.

[2] J. R. Tucker, C. Wang, and P. A. Carney, “Silicon field-effect transistor based on quantum tunneling,” Appl. Phys. Lett., vol. 65, pp. 618–620, 1994.

[3] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on SOI substrate and demonstration of sub-50 nmn-type de-vice with metal gate,” Jpn. J. Appl. Phys., vol. 38, pp. 6226–6231, 1999. [4] M. Nishisaka, Y. Ochiai, and T. Asano, “Pt-Si source and drain SOI-MOSFET operating in bi-channel mode,” in Proc. Device Res. Conf.

(DRC), 1998, pp. 74–75.

[5] C. Wang, J. P. Snyder, and J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistor,” Appl.

Phys. Lett., vol. 74, pp. 1174–1176, 1999.

[6] A. Itoh, M. Saitoh, and M. Asada, “A 25-nm-long channel metal-gate

p-type Schottky source/drain MOSFET on SOI substrate,” Jpn. J. Appl.

Phys., pt. I, vol. 39, pp. 4757–4578, 2000.

[7] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. J. King, and C. Hu, “Complementary silicided source/drain thin-body MOSFET’s for the 20 nm gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60. [8] H. C. Lin, C. Y. Lin, K. L. Yeh, R. G. Huang, M. F. Wang, C. M. Yu, T.

Y. Huang, and S. M. Sze, “A novel implantless MOS thin-film transistor with simple processing, excellent performance and ambipolar operation capability,” in IEDM Tech. Dig., 2000, pp. 857–859.

[9] H. C. Lin, K. L. Yeh, R. G. Huang, C. Y. Lin, and T. Y. Huang, “Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension,” IEEE Electron Device Lett., vol. 22, pp. 179–181, 2001.

[10] H. C. Lin, K. L. Yeh, R. G. Huang, and T. Y. Huang, “Impacts of field-induced drain (FID) on the ambipolar operation of poly-Si Schottky-barrier thin-film transistors (SBTFT’s),” in AMLCD Tech. Dig., 2001, pp. 247–250.

[11] K. L. Yeh, H. C. Lin, R. G. Huang, R. W. Tsai, and T. Y. Huang, “Con-duction mechanisms for off-state leakage current of Schottky barrier thin-film transistors,” Appl. Phys. Lett., vol. 79, pp. 635–637, 2001. [12] T. Y. Huang, I. W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, “A

simpler 100-V polysilicon TFT with improved turn-on characteristics,”

IEEE Electron Device Lett., vol. 11, pp. 244–246, 1990.

[13] , “Device sensitivity of field-plated polysilicon high-voltage TFT’s and their application to low-voltage operation,” IEEE Electron Device

Lett., vol. 11, pp. 541–543, 1990.

[14] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1982.

Horng-Chih Lin (S’91–M’95–SM’01) was born

in I-Lan, Taiwan, R.O.C. on August 1, 1967. He received the B.Sc. degree in physics from National Central University, Chung-Li, Taiwan, in 1989, and the Ph.D. degree from the Institute of Electronics from National Chiao-Tung University, Hsinchu, Taiwan, in 1994.

In 1994, he joined the National Nano Device Lab-oratories, Hsinchu, as an Associate Researcher, and became a Researcher in 1999. His current research interests include plasma etching technology, salicide technology, thin-film transistor (TFT) fabrication and characterization, and re-liability of CMOS devices.

(7)

Kuan-Lin Yeh was born in Hsinchu, Taiwan, R.O.C.,

on November 4, 1975. He received the B.S. degree in electrical engineering from Chang Chung University, Tao-Yuan, Taiwan, in 1998. He is currently pursing thePh.D. degree in the Institute of Electronics Engi-neering, National Chiao-Tung University, Hsinchu.

His research interests are focused on the study of Schottky Barrier TFTs and low-temperature TFT processes.

Tiao-Yuan Huang (S’78–M’81–F’95) was born in

Kaohsiung, Taiwan, R.O.C., on May 5, 1949. He re-ceived the B.S.E.E. and the M.S.E.E. degrees from National Cheng Kung University, Tainan, Taiwan, in 1971 and 1973, respectively, and the Ph.D. degree in electrical engineering from the University of New Mexico, Albuquerque, in 1981.

After serving two years in the Taiwanese Navy, he joined the Chung Shan Institute of Science and Technology, Lungtan, working on missile devel-opment. Following two years with Semiconductor Process and Design Center, Texas Instruments, he has worked with several companies, including Xerox Palo Alto Research Center, Integrated Device Technology, Inc., and VLSI Technology, Inc. He had worked in various VLSI areas including memories (DRAM, SRAM, and nonvolatile memories), CMOS process/device technologies and device modeling/simulation, ASIC technolo-gies, and thin-film transistors for LCD display. In 1995, he returned to Taiwan to become an Outstanding Scholar Chair Professor with National Chiao-Tung University and Vice President of National Nano Device Laboratories, National Science Council, Hsinchu, Taiwan. He has published over 150 technical papers in international journals and conferences, and holds over 40 patents.

Dr. Huang received the 1988 Semiconductor International R&D Technology Achievement Award for his invention of fully overlapped LDD transistors. He served on the technical committee of the IEEE International Electron Devices Meeting (IEDM) in 1991 and 1992. He also served on the program committee of the International Conference on Solid States Devices and Materials (SSDM) from 1996 to 1998.

Ruo-Gu Huang (S’00) was born in Taiwan, R.O.C.

in 1976. He received the B.S. degree in electrical engineering from National Tsing-Hua University, Taiwan, in 1999, and the M.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2001.

He is an Engineer with the Core SOC Division of Macronix International Corporation, Hsinchu. His re-search interests include microelectronic devices and VLSI circuit design.

Simon M. Sze (M’66–SM’74–F’77–LF’01) received

the B.S. degree from the National Taiwan Univer-sity, Taipei, Taiwan, R.O.C., the M.S. degree from the University of Washington, Seattle, and the Ph.D. de-gree from Stanford University, Stanford, CA, all in electrical engineering.

He was with Bell Laboratories from 1963 to 1989. He joined the faculty of Electronics Engineering Department, National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1990. At present, he is UMC Chair Professor of NCTU, and President of the National Nano Device Laboratories. He has made pioneering contributions to metal-semiconductor contacts, microwave and photonic devices, and submicron MOSFET technology. Of particular importance is his invention of the nonvolatile semiconductor memory such as EEPROM and flash memory. This memory is a key component for the cellular phone, notebook computer, smart IC card, digital camera, and a host of portable electronic system. He has authored or coauthored over 150 technical papers and written and contributed to 24 books. His book Physics of Semiconductor Devices (New York: Wiley, 1969, 2nd ed., 1981) is the most cited work in contemporary engineering and applied science publications (over 12000 citations from ISI Press).

Dr. Sze has received the IEEE Ebers Award, the Sun Yat-sen Award, the Na-tional Science and Technology Award, and the NaNa-tional Chair Professor Award. He is a member of the Academia Sinica, the Chinese Academy of Engineering, and the U.S. National Academy of Engineering.