Low-power VCO with phase-noise improvement in 0.18 mu m CMOS technology

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Low-power VCO with phase-noise

improvement in 0.18 mm CMOS technology

C.-P. Liang, T.-J. Huang, P.-Z. Rao and S.-J. Chung

A low-power 5.25 GHz voltage-controlled oscillator (VCO) with phase-noise improvement is designed in a 0.18 mm CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good ﬁgure of merit of 2190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a core power consumption of 1.9 mW and active chip area of 0.15 mm2_. The measured phase noise at 1 MHz offset is about 2119 dBc/Hz.

Introduction: Phase noise is one of the most critical parameters since it affects the overall performance of a communication system; therefore, there are numerous attempts in the design of VCOs to optimise phase-noise performance. The harmonic tuned LC tank is employed to attenu-ate the second-harmonic power while maintaining a superior fundamen-tal power, which is of beneﬁt in making the output voltage waveform steeper for reducing ﬂicker noise of the transistor[1]. Phase-noise sup-pression is achieved by maximising the slope of the output voltage at the zero crossing point. However, it inevitably results in high implemen-tation cost because additional on-chip inductors are required. On the other hand, inductively coupled plasma (ICP) deep-trench technology, which selectively removes the silicon underneath the inductors, also can be utilised to improve the phase noise of a VCO [2]. Nevertheless, the extra CMOS process steps will increase the compli-cation of the circuit implementation.

In this Letter, we adopt the design of a current-reused conﬁguration because of its excellent low-power characteristic [3], and focus on improvement of phase-noise performances without additional chip area and CMOS process steps. By a larger parallel capacitor, an extra harmonic-rejected capacitor, and an appropriate bulk bias voltage of transistor, a good ﬁgure of merit (FOM) of 2190 dBc/Hz will be attained. VDD Ro Ro Rb Rb Rg M1p Vbp V_g V_g Vbn CB CB R_g Vout+ core size : 0.33×0.45mm2 Vout– V– V+ Cvar Cvar M1n a b M2n M2n Cct CT L1 A C₁

Fig. 1 Complete schematic and die microphotograph of proposed VCO with phase-noise reduction techniques

a Complete schematic b Die microphotograph

Circuit design: The proposed VCO, shown inFig. 1, uses a cross-con-nected pair consisting of NMOS and PMOS transistors as a negative conductance generator. Power consumption and the use of inductors can be cut by half compared to the traditional VCO while providing the same negative conductance[3]. However, an unbalanced voltage swing at node V+will deteriorate the phase-noise performance when

V+changes between high and low statuses. To improve this drawback,

a larger value of the capacitor C1is required to maintain the similar

impedances in both operation statuses. It can be observed fromFig. 2

that a larger capacitor C1 effectively provides a balanced voltage

swing at node V+. On the other hand, the suppression of the

second-har-monic power with the series L-C sections has been utilised to improve the phase noise of a VCO [1]; however, the extra inductors will occupy additional chip area. In this study, we introduce an additional capacitor CTin the VCO circuit (Fig. 1) to attenuate the

second-harmo-nic signal. To begin with, it can be anticipated that node A is a virtual ground owing to the differential outputs of the fundamental signal, and this means that the existence of the capacitor CTwill have no

inﬂu-ence on the oscillation frequency. However, the in-phase second-har-monic signals can be suppressed by the use of a suitable capacitor CT

because a series resonance is produced. Consequently, the introduction of the suitably designed capacitor CTcan diminish the second-harmonic

signal without increasing chip area and inﬂuencing the oscillation frequency. 0 100 200 300 400 0 0.3 0.6 0.9 1.2 1.5 low status high status C₁=0.2 pF C₁=0.6 pF V+ voltage swing, V time, ps

Fig. 2 Simulated V+voltage swing for different values of C1

Moreover, the 1/f3corner in the phase noise spectrum can be given from[4] v1/f3≃v_1/f c0 c1 2 = K C0xWL g2 m ggd0 1 4kT c0 c1 2 (1) where v1/f is the corner of the transistor 1/f noise and c0 and c1

represent the ﬁrst and second Fourier series coefﬁcients of the impulse sensitivity function (ISF). From (1), the 1/f 3 corner of the phase noise spectrum can be reduced by selecting a larger channel width W; however, this will indirectly increase the value of the transconductance gm, which is proportional to the size of the transistor. To overcome this

drawback, here we introduce the additional bulk bias voltages Vbpand

Vbn of the transistors, as shown in Fig. 1, for further obtaining a

smaller gm. By providing an appropriate bulk bias voltage, the threshold

voltage can effectively be raised to diminish the current of the transistor since the threshold voltage is governed with the body effect. Fig. 3

shows the simulated results of the phase noise characteristics with and without improvement. It can be observed and demonstrated that a 15 dB decrease at 10 kHz offset frequency can be attained owing to the use of a larger capacitor C1, an extra capacitor CT, and the

appropri-ate bulk bias voltage Vb.

102 101 –100 –90 –80 –70 –60 without improvement with C_{1_larger} with C_{1_larger} & C_T with C_{1_larger} & C_T & V_b

phase noise, dBc/Hz

offset frequency, kHz

Fig. 3 Simulated phase noises with and without improvement

Results: The microphotograph of the low-power VCO fabricated by 0.18 mm TSMC CMOS process is shown in Fig. 1b. The core chip area is 0.33 × 0.45 mm2_{, and the core DC power dissipation is}

1.9 mW at a 1.3 V supply voltage. The value of Roin the proposed

VCO is set as 50 V to achieve the output match for testing purposes. The fabricated VCO is measured with an Agilent E5052A signal

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source analyser. The measured tuning range is from 5.12 to 5.36 GHz when the tuning voltage Vct is between 0 and 1.3 V. The measured

phase noise, as shown in Fig. 4, is about 2119 dBc/Hz at 1 MHz offset frequency with the centre frequency at 5.14 GHz and an output power of 22.4 dBm. The proposed VCO performance is compared with recently published CMOS VCOs and summarised in

Table 1[5 – 7]. 100 101 102 103 104 –140 –120 –100 –80 –60 –40 –20 phase noise, dBc/Hz offset frequency, kHz measurement simulation

Fig. 4 Measured and simulated phase noises of proposed VCO

Table 1: Comparison with previous works

Ref. Technique Frequency

(GHz) PN at 1Mz (dBc/Hz) Pdiss (mW) Area (mm2 ) FOM (dBc/Hz) [5] 0.18 mm CMOS 4.5 2122.5 6.75 0.55 2187 [6] 0.18 mm CMOS 5.1 2116.7 3.9 0.5 2185 [7] 0.18 mm CMOS 5.6 2110.8 8.3 0.5 2177

This work 0.18 mm CMOS 5.25 2119 1.9 0.15 2190

Conclusions: A low-power VCO with phase noise improvement has been designed and fabricated using 0.18 mm CMOS technology. Based on the current reused conﬁguration, a larger value of capacitor C1, an additional capacitor CT, and the appropriate bulk bias voltage

Vbof the transistor are adopted to achieve a better noise performance.

The measured results of the proposed VCO agree quite well with the simulated results.

Acknowledgment: The authors thank the Chip Implementation Center (CIC) for technical support.

#_{The Institution of Engineering and Technology 2010} 11 May 2010

doi: 10.1049/el.2010.1278

One or more of the Figures in this Letter are available in colour online. C.-P. Liang, T.-J. Huang, P.-Z. Rao and S.-J. Chung (Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan)

E-mail: sjchung@cm.nctu.edu.tw References

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