818 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 9, SEPTEMBER 2007
Measurement of Channel Stress Using Gate
Direct Tunneling Current in Uniaxially
Stressed nMOSFETs
Chen-Yu Hsieh, Student Member, IEEE, and Ming-Jer Chen, Senior Member, IEEE
Abstract—We measure the conduction-band electron direct
tun-neling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation po-tential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0,
−100, and −300 MPa for a gate-to-trench isolation spacing of 2.4,
0.495, and 0.21 µm, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measure-ments on the same device is conducted. The resulting piezoresis-tance coefficient and band offset are in good agreement with the literature values. The layout technique used is validated as well.
Index Terms—Mechanical stress, MOSFET, piezoresistance,
shallow trench isolation (STI), strain, tunneling.
I. INTRODUCTION
I
T IS WELL recognized that the mechanical stress in MOSFETs can significantly affect many electrical proper-ties such as mobility [1]–[3], hot carrier immunity [4], threshold voltage [5], and gate direct tunneling current [6]–[8]. Thus, the ability to quantitatively determine the magnitude of the underlying mechanical stress as well as its status (compressive or tensile) is essential. Three fundamentally different methods have been introduced in this direction: 1) wafer bending jig [9]; 2) sophisticated stress simulation [10]; and 3) Raman spec-troscopy [11]. Obviously, the electrical approach to mechanical stress was lacking to date. However, it is noteworthy that the gate direct tunneling current has been well studied under externally applied mechanical stress [6]–[8]. Particularly in [8], the deformation potential constants [12]–[14] have been exper-imentally determined and have been found to be consistent with theoretical works [15]. Therefore, with known deformation potential constants, it is plausible to measure mechanical stress by means of the gate direct tunneling current.In this letter, we show how to transform the gate direct tun-neling current in stressed devices into the value of stress achieved without adjusting any parameter. Confirmative evi-dence is presented in terms of piezoresistance coefficient and band offset, which are both electrically created on the same device.
Manuscript received April 26, 2007; revised June 7, 2007. This work was supported by the National Science Council of Taiwan under Contract NSC 95-2221-E-009-295-MY3. The review of this letter was arranged by K. De Meyer. The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: chenmj@ faculty.nctu.edu.tw).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2007.902985
Fig. 1. (a) Schematic cross section and (b) topside view of the device under study. The gate edge to STI sidewall, i.e., a, is highlighted. The stress condition is compressive due to the lower thermal expansion rate of STI oxide compared to silicon.
II. EXPERIMENT
The n+ poly-silicon gate nMOSFETs were fabricated in a state-of-the-art manufacturing process. Three key process parameters were obtained by capacitance–voltage (C–V ) fitting: n+poly-silicon doping concentration = 1× 1020cm−3,
gate oxide thickness = 1.27 nm, and substrate doping concentration = 4× 1017 cm−3. In this process, shallow trench isolation (STI)-induced compressive stress was applied. The gate length along the110 direction was 1 µm, whereas the gate width was 10 µm, which is large enough that the transverse strain is relatively insignificant. The layout technique was utilized in terms of gate edge to STI sidewall spacing, which is designated as a, with three values of 2.4, 0.495, and 0.21 µm. A decrease in a means increased magnitude of longitudinal stress. The schematic cross section and topside view of the test device are depicted in Fig. 1.
The gate direct tunneling current was measured in inversion conditions with the source, drain, and substrate all tied to ground. The simultaneously measured valence-band electron tunneling counterpart or equivalently the substrate hole current was found to be unchanged regardless of stress. This indicates that the gate oxide thickness under study remains constant. Also
HSIEH AND CHEN: MEASUREMENT OF CHANNEL STRESS USING GATE DIRECT TUNNELING CURRENT 819
Fig. 2. Relative change of the gate direct tunneling current at Vg= 1 V versus
gate-to-STI spacing. The inset shows the mobility variations and the threshold voltage shift both versus the gate-to-STI spacing.
characterized were the threshold voltage and mobility on the same device at Vd= 25 mV. The change of the
conduction-band electron direct tunneling current at Vg= 1 V, the mobility
at Vg= 0.5 V, and the threshold voltage shift, all with respect
to a = 2.4 µm, are plotted in Fig. 2 versus gate-to-STI spacing. It can be seen that a decrease in the gate-to-STI spacing can produce an increase in both gate current and threshold voltage while degrading mobility.
III. STRESSEXTRACTION
Existing direct tunneling models [16], [17] on the basis of the triangular potential approximation [18] in the channel, which takes into account the poly-silicon depletion, can be readily applied with some slight modifications such as incorporating stress dependencies of the subbands. The electrons in inver-sion primarily populate the two lowest subbands [8]: one of the twofold valley ∆2 and one of the fourfold valley ∆4. The corresponding stress dependencies are well defined in the literature [8], [12]–[14] E∆2(σ) = 9hqEeff,∆2 162m∗∆2 2 3 + Ξd+ Ξu 3 (S11+ 2S12)σ + Ξu 3 (S12− S11)σ (1) E∆4(σ) = 9hqEeff,∆4 162m∗∆4 2 3 + Ξd+ Ξu 3 (S11+ 2S12)σ − Ξu 6 (S12− S11)σ (2)
where the quantization effective masses are m∗∆2= 0.92 m0 and m∗∆4= 0.19 m0, and the elastic compliance constants are
S11= 7.68× 10−12 m2/N and S12=−2.14 × 10−12 m2/N. The hydrostatic and shear deformation potential constants Ξd= 1.13 eV and Ξu= 9.16 eV [5], which are close to those
in [8], were cited here. One of the expressions for the effective electric field Eeff can be found elsewhere [8]. With the afore-mentioned process parameters as input, the two lowest subband levels with respect to the Fermi level Ef can be determined.
The stress dependencies of the lowest subbands under different
Fig. 3. Relative change of the gate direct tunneling current versus extracted uniaxial compressive channel stress for Vg= 0.5, 0.75, and 1 V. The symbols
are experimental data. The fitting line is drawn only for accommodating the trend.
gate voltages were found to be consistent with those in earlier works [8]. The inversion-layer carrier density per unit area can further be calculated by Ni= (kBT /π2)gimdiln(1 +
exp((Ef− Ei)/kBT )) [16]–[18], where the subscript i
denotes ∆2 or ∆4, kBT is the thermal energy, gi is the
degeneracy of the valley, and mdi is the density of state effective mass. It is then a straightforward task to calculate the Wentzel–Kramers–Brillouin tunneling probability, taking into account the corrections for reflections from the potential discontinuities [19]. Here, the electron effective mass in the oxide for the parabolic-type dispersion relationship was used with mox∼ 0.50 m0, which is equivalent to
mox= 0.61 m0 for the tunneling electrons in the oxide using the Franz-type dispersion relationship [20]. The SiO2/Si interface barrier height in the absence of stress is 3.15 eV. Consequently, without adjusting any parameter, the conduction-band electron direct tunneling current density can be calculated as a function of stress σ [8] as Ig(σ) = qN∆2(σ) τ∆2(σ) +qN∆4(σ) τ∆4(σ) . (3)
The tunneling lifetime in (3) can be related to the transmission probability T as τ∆2(σ) = π/(T∆2(σ)E∆2(σ)) and
τ∆4(σ) = π/(T∆4(σ)E∆4(σ)).
With the above approach, we found that the uniaxial channel stress of around 0,−100, and −300 MPa for a gate-to-STI spac-ing of 2.4, 0.495, and 0.21 µm, respectively, can reproduce gate direct tunneling current versus gate voltage characteristics. The corresponding gate current change is plotted in Fig. 3 versus the extracted channel stress with gate voltage as a parameter. It can be seen that the magnitude of the gate current change increases linearly with the stress, which is consistent with those published elsewhere [8]. Again, in agreement with the citation [8], the slope of the straight line in Fig. 3 increases with decreasing gate voltage. This trend clearly points out that the accuracy of the proposed method can be enhanced by lowering gate voltages.
IV. CONFIRMATIVEEVIDENCE
The measured mobility change percentage versus extracted stress is shown in Fig. 4. The straight line through the data
820 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 9, SEPTEMBER 2007
Fig. 4. Measured mobility change and threshold voltage shift versus extracted stress. The inset shows the extracted stress divided by that of the minimum a versus the gate-to-STI spacing along with a fitting curve from (4).
points yields the slope or piezoresistance coefficient of 32.5× 10−12 dyn−1 cm2, which is close to that (31.5× 10−12 dyn−1 cm2) in the literature [21]. Also plotted is the threshold voltage shift ∆Vth, which produces a straight line of its own. This line can be related to the body-effect coefficient
m and the band offset ∆Eg[5]: q∆Vth(σ)≈ (m − 1)∆Eg(σ).
The band offset term can further be linked to the strain ε [5]: ∆Eg=−6.19ε = −3.66 × 10−11σ eV. The slope of the line in
Fig. 4 furnishes m = 1.35, which exactly falls within the cited range of 1.3–1.4 [5].
To testify to the layout technique mentioned above, we quote the existing relationship between the effective channel stress and the gate-to-STI spacing, which was derived from the stress simulation [10]
σ(a) = σ(amin) 1 + Vmσ a− amin a (4) where amin represents a minimum gate-to-STI spacing, and
Vmσis the maximum σ(a) variations (i.e., when a→ ∞) with
respect to σ(amin). The extracted stress can be adequately described by (4) with Vmσ=−1.05, as inserted in Fig. 4.
Indeed, the projected stress for a = 2.4 µm, i.e., the reference point mentioned above, approaches zero. Therefore, the layout technique holds true in this letter.
Finally, the electrical method accompanied with the layout technique was also applied to other devices (with a sample size of 10) on the same wafer. The corresponding stress-induced variations in gate direct tunneling current were found to be comparable with those in Fig. 3.
V. CONCLUSION
With known process parameters and published deformation potential constants as input, fitting of the gate direct tunneling current versus gate voltage data has led to the value of the un-derlying channel stress. A link with the mobility and threshold voltage measurements on the same device has been conducted. The resulting piezoresistance coefficient and band offset have been in good agreement with the literature values. The layout technique has also been validated.
REFERENCES
[1] J. Welser, J. L. Hoyt, and J. F. Gibbons, “nMOS and pMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures,” in
IEDM Tech. Dig., 1992, pp. 1000–1002.
[2] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790–1797, Nov. 2004.
[3] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM
Tech. Dig., 2003, pp. 73–76.
[4] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, “A new aspect of mechanical stress effects in scaled MOS devices,” IEEE Trans. Electron
Devices, vol. 38, no. 4, pp. 895–900, Apr. 1991.
[5] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed nMOSFETs,” IEEE
Electron Device Lett., vol. 25, no. 11, pp. 731–733, Nov. 2004.
[6] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, Jun. 2005.
[7] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, no. 5, p. 052 108, Jan. 2006.
[8] J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, “Measurement of conduction band deformation potential constants using gate direct tunnel-ing current in n-type metal oxide semiconductor field effect transistors under mechanical stress,” Appl. Phys. Lett., vol. 89, no. 7, p. 073 509, Aug. 2006.
[9] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally ap-plied stress,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1254–1261, Aug. 2004.
[10] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electri-cal performance,” in IEDM Tech. Dig., 2002, pp. 117–120.
[11] I. D. Wolf, “Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits,” Semicond. Sci. Technol., vol. 11, no. 2, pp. 139–154, Feb. 1996.
[12] C. Herring and E. Vogt, “Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering,” Phys. Rev., vol. 101, no. 3, pp. 944–961, Feb. 1956.
[13] I. Balslev, “Influence of uniaxial stress on the indirect absorption edge in silicon and germanium,” Phys. Rev., vol. 143, no. 2, pp. 636–647, Mar. 1966.
[14] C. G. Van de Walle and R. M. Martin, “Theoretical calculations of het-erojunction discontinuities in the Si/Ge system,” Phys. Rev. B, Condens.
Matter, vol. 34, no. 8, pp. 5621–5634, Oct. 1986.
[15] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, no. 4, pp. 2234–2252, Aug. 1996.
[16] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Mod-eling study of ultrathin gate oxides using direct tunn“Mod-eling current and capacitance–voltage measurements in MOS devices,” IEEE Trans.
Electron Devices, vol. 46, no. 7, pp. 1464–1471, Jul. 1999.
[17] K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+poly-gate pMOSFETs with
ultrathin gate oxides,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2161–2166, Nov. 2000.
[18] H. H. Mueller and M. J. Schulz, “Simplified method to calculate the band bending and the subband energies in MOS capacitors,” IEEE Trans.
Electron Devices, vol. 44, no. 9, pp. 1539–1543, Sep. 1997.
[19] L. F. Register, E. Rosenbaum, and K. Yang, “Analytic model for direct tun-neling current in polycrystalline silicon-gate metal–oxide–semiconductor devices,” Appl. Phys. Lett., vol. 74, no. 3, pp. 457–459, Jan. 1999. [20] Z. A. Weinberg, “On tunneling in metal–oxide–silicon structures,”
J. Appl. Phys., vol. 53, no. 7, pp. 5052–5056, Jul. 1982.
[21] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresis-tance coefficients of (100) silicon nMOSFETs measured at low and high (∼1.5 GPa) channel stress,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 58–61, Jan. 2007.
