Analysis and Design of a Single-Stage Parallel
AC-to-DC Converter
Heng-Yi Li, Hung-Chi Chen, Member, IEEE, and Lon-Kou Chang, Member, IEEE
Abstract—In this paper, a single-stage (S2) parallel ac-to-dc
con-verter based on single-switch two-output boost–flyback concon-verter is presented. The converter contains two semistages. One is the boost– flyback semistage, which transfers partial input power transferred to load directly through one power flow path and has excellent self-power factor correction property when operating in discontin-uous conduction mode even though the boost output is close to the peak value of the line voltage. The other one is the flyback dc-to-dc (dc/dc) semistage that provides the output regulation on another parallel power flow path. With this design, the power conversion efficiency is improved and the current stress of control switch is re-duced. Furthermore, the calculation process of power distribution and bulk capacitor voltage, design equations, and design procedure for key parameters are also presented. By following the procedure, an 80 W prototype converter has been built and tested. The exper-imental results show that the measured line harmonic current at the worst condition complies with the IEC61000-3-2 class D limits, the maximum bulk capacitor voltage is about 415.4 V, and the max-imum efficiency is about 85.8%. Hence, the proposed S2converter
is suitable for universal input usage.
Index Terms—AC/DC power conversion, fly back converter, power factor correction, single-stage, single-switch.
I. INTRODUCTION
T
HE POWER factor correction (PFC) has been widely em-ployed for improving the power quality of the power con-verters. In conventional converters design, a two-stage structure was usually employed for performing PFC and output regu-lation simultaneously, where the bulk capacitor CB is in the power transfer path between the PFC stage and dc-to-dc (dc/dc) stage. This structure can give high power factor and high regu-lation simultaneously by using two independent controllers and power stages, but the cost of switching devices and the control circuitry is not easy to cut down especially in low-power appli-cation. Although unity power factor is the ideal objective, it is no longer an essential requirement. According to the regulation IEC61000-3-2 [1], the power supplies of low-power productsManuscript received October 27, 2008; revised March 20, 2009. Current ver-sion published December 28, 2009. This paper was presented in part at the IEEE Power Electronics Specialists Conference (PESC), Jeju, Korea, June 18th–22nd, 2006. Recommended for publication by Associate Editor P.-T. Cheng.
H.-Y. Li is with the Department of Electrical and Control Engineering (ECE), National Chiao Tung University (NCTU), Hsinchu 300, Taiwan. He is also with the Institute of Nuclear Energy Research, Taoyuan 325, Taiwan (e-mail: [email protected]).
H.-C. Chen is with the Department of Electrical and Control Engineering (ECE), National Chiao Tung University (NCTU), Hsinchu 300, Taiwan (e-mail: [email protected]).
L.-K. Chang is with Macroblock, Inc., Hsinchu 300, Taiwan (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2023550
such as computers, PC monitors, and television sets have to comply with class D limits. This fact promotes the development of the S2 ac-to-dc converter, such as boost integrated/flyback
rectifier/energy storage/dc-to-dc converter (BIFRED) [2] and boost input current shaper (ICS) [3]–[8], which comply with the regulations without achieving unity power factor. In those designs, two power stages were integrated into one stage by using only one controller and sharing the control switch so that the component count and cost could be reduced. However, these converters have the problems of high bulk capacitor voltage at high line and light load when PFC semistage is operated in discontinuous conduction mode (DCM) and dc/dc semistage in continuous conduction mode (CCM). Some alternative de-signs [5]–[8] using additional coupled feedback windings could reduce the bulk capacitor voltage, but they also result in dead angle in the input current so that the input current distortion is increasing. Furthermore, it can be seen that part of the power is repeatedly processed or recycled in both the conventional two-stage and S2ac-to-dc converters.
To improve the power processing, the concept of parallel PFC (PPFC) has been proposed in [9] and [10]. In those schemes, two parallel power flow paths are used and part of the input power is processed only once. Therefore, the converters could transfer power with higher efficiency. Since each path only transmits part of the whole conversion power, the components can be replaced with smaller ones. However, the PPFC design has complex cir-cuit with special control scheme as mentioned in [11]. Another scheme of parallel power processing approach was presented on the base of two-output preregulator cascaded with two-input postregulator [12]. Although the output capacitor is smaller and the power conversion efficiency is high, some extra implementa-tion prices exist, such as multiple switching devices and floating MOSFET driver. In addition, the output range of the postreg-ulator is limited so as not suitable for universal input, and it is a two-stage structure by nature. The universal boost/forward converter presented in [14], [15] makes use of an auxiliary trans-former to reduce link voltage stress without inducing the dead angle of the line current. Hence, it inspires the parallel idea for the universal S2converter in this paper.
For an ideal PFC converter, the input power (pin) is a sine
square function biased by constant output power (Pout). As
mentioned in [9] and [10], there is 68% of line average in-put power that can be transferred to outin-put directly through PFC stage, which is called the direct power (DP). Only the remaining 32% of line average input power needs to be stored in the bulk capacitor temporarily through PFC stage and taken off from the bulk capacitor through dc/dc stage. Since the processed powers are not directly transferred from ac input to dc output, they are
TABLE I
RECENTLYPUBLISHEDS2APPROACHES
called indirect powers (IDPs). Hence, based on the aforemen-tioned concept, a new family of S2ac-to-dc (ac/dc) converter is proposed in this article to increase the DP content percentage on the input power. In the circuits, the front semistage is of single-switch two-output (SSTO) boost–flyback configuration that works as a power factor corrector. Part of input power is processed with the front flyback cell, and the remainder of input power is processed through the path along boost cell-CB-dc/dc semistage.
To illustrate the circuit and control of the proposed con-verter, several recently published low-power S2 approaches are
tabulated in Table I. Only the proposed converter and those in [20], [21] are implemented with single-switch and single-loop controller. However, the efficiency of [20] is significantly lower than the proposed one and the component count of [21] is more than the proposed one. From Table I, the circuits in [20], [21], and [13] have relatively small capacitor voltages. However, the
circuit of [20] has the shortcoming of low efficiency. The circuit of [21] employs two bulk capacitors and multiwinding trans-former to get low voltage. The circuit in [13] puts bulk capacitor on the secondary side of flyback transformer, which results in the low capacitor voltage. However, it also has the shortcomings of extra control switch and that the efficiency would decrease when universal voltage is applied. Though the bulk capacitor voltage in proposed converter is higher than those in [13], [20], and [21], it is not higher than 450 V, the voltage limitation of commercial capacitors. Additionally, the use of single switch with small current stress, two parallel power streams with small components, and single-loop controller is a competitive advan-tage in the low-power universal applications.
Besides the S2parallel topologies, the detailed operation
prin-ciple and design procedure for universal application is also presented in this article. With the procedure, an 80 W proto-type is constructed, which is a specific demonstration case used
Fig. 1. Proposed S2PPFC scheme.
for clear demonstration. Its experimental results have shown that input current has no dead angle and its harmonics satisfies IEC61000 class D at low line with full load and the maximum bulk capacitor voltage is under 450 V at high line with light load. It is suggested that the proposed S2 converter could be
used for 50–150 W with universal input voltage range and up to 200 W with European voltage range. Therefore, the potential applications could be PC monitors, ac/dc adapters, and small television sets.
II. OPERATIONPRINCIPLES
A. S2 Parallel Boost–Flyback Converter
The new design power flow scheme of a S2 PPFC is shown
in Fig. 1. In Fig. 1, the line power pin is fed to SSTO boost–
flyback semistage and split to two power flow streams p1 and p2. The power flow stream p1is processed only by flyback cell
and transferred to output directly, and hence it is DP. Since the instantaneous pin is always different from output power Pout,
the remaining input power, p2, is buffered to bulk capacitor CB
through the boost function of boost cell to regulate power flow. To fulfill a better output power regulation, a dc/dc semistage is employed to transfer the power, denoted by p3, from CB to the output when pinis low, especially smaller than Pout. The power
series p2and p3are processed twice from ac input to dc output,
and hence they are IDPs. Furthermore, to obtain high power factor, the boost and flyback cells both had to better operate in DCM, whereas the dc/dc semistage can be implemented with forward or flyback configuration and operate either in CCM or DCM. A S2implemented circuit of Fig. 1 is shown in Fig. 2(a).
The circuit has been simplified so as to use only one com-mon power control switch for SSTO boost–flyback and dc/dc semistages as shown in Fig. 2(b). In Fig. 2(b), PFC and out-put regulation are performed with one feedback controller as shown in Fig. 2(c). More topologies variations had been shown in [15]. The practical realization circuit in Fig. 2(b) is com-posed of a SSTO boost–flyback semistage, which is constructed by LB, DB, T1, DO 1, DI 1, S, Db, and a bulk capacitor CB, and a dc/dc semistage, which is implemented by a flyback circuit and constructed by T2, DO 2, DI 2, S, and Db. In Fig. 2(a) and (b), the two transformers T1 and T2 share the load current, so
their size could be small. Furthermore, the boost inductor LB Fig. 2.
S2Implementation circuit of parallel boost–flyback–flyback converter.
Fig. 3. SSTO boost–flyback converter. (a) Circuit. (b) Main waveforms.
and transformers T1 distribute the input power together when
switch S isON, so the size of LBcould be of smaller one. There-fore, the sizes of LB, T1, and T2 can be chosen as smaller ones
in this design.
B. SSTO Boost–Flyback Circuit
In order to clearly build the primary operation concepts and theories of the proposed S2parallel ac-to-dc converter depicted in Figs. 1 and 2, the operation of a SSTO boost–flyback converter depicted in Fig. 3(a) will be introduced in advance. In SSTO boost–flyback converter, T1− DO 1− DI 1− CO− RO− S is the flyback cell and LB− DB− CB− RB− S is the boost cell. This converter has PFC function that will be demonstrated later. In the converter, the boost inductance LB and the flyback transformer T1 both operate in DCM. When control switch S is
turned on, T1and LBare charged serially. When S is turned off, T1and LB are discharged to RO− CO and RB− CB, respec-tively. The main current waveforms of SSTO boost–flyback con-verter operating in one switching period are shown in Fig. 3(b). To demonstrate the operation theory of the converter, the moving average notationx (t) of a waveform x (t) over a switching period TS is employed and defined as follows [16]:
x (t) ≡ x (t)TS = 1 TS t+ TS t x (τ ) dτ . (1) To focus on the primary analyses, some assumptions are made as follows.
1) All components are ideal.
2) Since switching frequency fS is far greater than line
frequency fL= 1/TL, where TL is line period. The
in-put voltage vin(t), regarded as the rectified line voltage Vinpk|sin (ωL· t)|, is approximated to a constant over one
switching period, where Vinpk is the ac voltage amplitude
and ωL= 2· π/TL.
3) Since bulk capacitor CB and output capacitor CO are sufficiently large, flyback output voltage VO and boost output voltage VC B are regarded as constants within one half line cycle.
From Fig. 3(a), it can be seen that the average input cur-rent iin(t) is equal to the sum of average flyback input
diode current iD I 1(t) and average boost output diode cur-rentiD B(t). Therefore, by summing the current waveforms ofiD I 1(t) and iD B(t) shown in Fig. 3(b), iin(t) can be
obtained as
iin(t) = iD I 1(t) + iD B(t) =
ipk1× (d + d2)
2 (2a)
where d is the duty ratio of S, d2 is the boost cell diode
con-duction time ratio, and the current peak value can be obtained from ipk1= d· vin(t) fS(LB + LM 1) =d2· (VC B − vin(t)) fSLB =d1· n1· VO fSLM 1 (2b) where LM 1 is the primary magnetizing inductance of T1, n1is
the primary turns ratio of T1, and d1 is the flyback cell output
diode conduction time ratio. From (2b), d2 can be obtained as d2= d· vin(t) (VC B − vin(t)) LB LB+ LM 1 . (2c)
With substituting (2b) and (2c) into (2a),iin(t)can be found
as iin(t) = d2v in(t) 2fS(LB + LM 1) × 1 + vin(t) (VC B − vin(t)) LB LB+ LM 1 . (2d) Since the average current of COover a half line cycle is zero at steady state, the half line average current of iD O 1 is equal to the average output current. Thus
2 TL π ωL 0 iD O 1(t) dt = VO RO . (3a)
From Fig. 3(b), average current over one switching period iD O 1(t) in (3a) can be obtained as follows:
iD O 1(t) =
n1· ipk1· d1
2 (3b)
where the magnetism discharging time ratio of T1transformer, d1, can be found from (2b) as
d1 = d· vin(t) n1· VO LM 1 LB + LM 1 . (3c)
With substituting (2b) and (3c) into (3b),iD O 1(t)can be obtained as
iD O 1(t) =
LM 1d2v2in(t)
2fS(LB+ LM 1)2VO
. (3d)
Substituting (3d) into (3a), the voltage gain of flyback cell MO can be obtained as MO = VO Vinpk = d· LM 1· RO 4fS(LB + LM 1)2 (3e) where RO is the load resistance of flyback cell.
TABLE II
VARIOUSOPERATIONMODES IN THEPROPOSEDCIRCUIT
Similarly, since CB has zero average current over a half line cycle in steady state, the average current relation can be obtained as 2 TL π ωL 0 iD B(t) dt = VC B RB (4a) whereiD B(t)can be obtained from Fig. 3(b) as
iD B(t) = ipk1· d2 2 = LBd2vin2 (t) 2fS(LB + LM 1)2(VC B − vin(t)) . (4b) The voltage gain of boost cell MC B is defined and obtained with substituting (4b) into (4a) as
MC B= VC B Vinpk = d 2· R B· LB 2π· fS(LB + LM 1)2 π 0 sin2θ MC B − |sin θ| dθ (4c) where RB is the load resistance of boost semistage.
It can be seen from (2d) that while d and fS are regarded as constants, the arrangement of smaller ratio of LB/(LB+ LM 1) can result in higher linear relation betweeniin(t) and vin(t),
in other words, lower input harmonic distortion. Furthermore, (3e) and (4c) show that voltage gain rises as load resistance increases. In particular, VC Bin (4c) can be very high at light load and high line. Therefore, the method to keep it under commonly accepted limit would be presented in Section III.
C. S4 Parallel Boost–Flyback–Flyback Converter
The proposed S2 boost–flyback–flyback PPFC that has two
semistages is shown in Figs. 1 and 2. The boost–flyback semistage has PFC function and simultaneously gives two energy-processing paths. Being the remaining semistage, the flyback dc/dc converter circuit has fast output regulation ability. The proposed circuit has three magnetic elements, and each el-ement has two operation modes (i.e., CCM and DCM). Hence, there are eight modes that may happen in the circuit as shown Table II. In order to obtain good power factor, the boost and flyback cells are designed to operate in DCM, whereas the fly-back dc/dc semistage operates in either CCM or DCM in a line cycle. Thus, the converter has two operating modes. The operation mode while the flyback dc/dc semistage operates in CCM is defined as the M1mode. Contrarily, the operation mode
while the flyback dc/dc semistage operates in DCM is defined as the M2 mode. As mentioned latter in Section III-C, it is not
easy to make LB operate in DCM throughout universal range, and CCM offers higher efficiency and lower current stress than DCM. M3and M4modes are allowed under harmonic limitation
Fig. 4. Main waveforms of flyback dc/dc semistage in a switching period. (a) M1mode. (b) M2mode.
of IEC61000-3-2 class D and not discussed in this paper. With properly selected n1, it is easy to control T1in DCM, so M5–M8
modes would not happen. The main current waveforms of the boost–flyback semistage in a switching period are the same as Fig. 3(b), and the waveforms of flyback dc/dc semistage in both modes are shown in Fig. 4. The circuit operations of the single-switch implemented circuit shown in Fig. 2(b) are demonstrated as follows:
In t0 ≤ t ≤ t1control switch S is switched on, flyback input
diode DI 1conducts, and DB, DO 1, and DO 2are cutoff. Because the boost inductor LB and the flyback transformer primary in-ductance LM 1 both are connected in series, they are charged by the input power at the same time. The current iL B, which is equal to iD I 1 and also the magnetizing current of T1, iL M 1, in-creases linearly from zero. Meanwhile, the currents iD I 2, which is equal to the magnetizing current of T2, iL M 2, also increases
linearly from its initial value while in M1 mode and from zero
while in M2mode. At the moment t1, S is turned off. The
cur-rents iL B, iD I 1, and iL M 1 reach the same peak value ipk1 and
the currents iD I 2 and iL M 2 reach another peak value ipk2.
In t1 ≤ t ≤ t3, the main switch S isOFF, the diode DI 1 and DI 2 are OFF, and DB, DO 1 and DO 2 are ON. The magnetic energy of inductor LB is transferred to CB and the magnetic energies of the transformers T1 and T2 are transferred to the
same output load RLsimultaneously. Consequently, the energy discharging in T1 produces the result that iL M 1 and iD O 1 (= n1· iL M 1) both decrease linearly to zero at t2a and keep zero
until t3, and iL B and iD B decrease linearly to zero at t2b. The
energy discharging in T2 gives the result that both iL M 2 and iD O 2(= n2· iL M 2) decrease linearly to nonzero final values at t3for M1mode and to zero at t2c for M2mode.
TABLE III
VARIOUSCASES IN THEPROPOSEDCIRCUIT
Since M1 and M2 modes are to be discussed, three kinds of
the combination of operation modes may be yielded within a half line cycle as shown in Table III. The major current waveforms and the corresponding duty ratio waveforms are depicted and shown in Fig. 5. Case I normally happens in low input voltage and high output power condition, whereas case III normally happens at high input voltage and low output power.
For transient current balance of CO, the transient load current can be expressed as
iO(t) = iD O 1(t) + iD O 2(t)− iC O(t) (5a) where iD O 1(t), iD O 2(t), and iC O(t) represent the transient current of DO 1, DO 2, and CO. By an ideal output voltage feedback control, the duty-cycle of control switch is varied in order to set output voltage on reference value. As shown in Figs. 3(b) and 4, the input current (iD O 1(t) + iD O 2(t)) of CO is regulated to balance with output current (iO) in TS so thatiO(t) = IO,iC O(t) = 0,vO(t) = VO, and (5a) can be expressed as IO = VO RL = Pout VO =iD O 1(t) + iD O 2(t) (5b) where VO is the average output voltage, RL is the load resis-tance, iD O 1(t) represents the averaging current of DO 1 as expressed in (3d), andiD O 2(t) represents the averaging cur-rent of DO 2. Although the input voltage varies in a half line cycle, the output power will be kept constant through the output feedback control. To make (5b) come true, the ideal output volt-age feedback controller should have superior transient response and robust stability. The structure of controller is implemented with current-mode controller with optically isolated feedback as shown in Fig. 2(c). In the circuit of Fig. 2(c), output voltage signal VO is transferred to UC3844 via TL431 and optcoupler, the switch current iS is sensed and fed back to comparator, and then the duty ratio d of control switch S is well controlled.
For the M1mode, consider the bulk capacitance is a large one.
Then the duty ratio d in M1 mode will be kept nearly constant Dm 1and yield a high regulation output, which is given by
VO = VC B · d n2(1− d) d= Dm 1 (6) where n2 is the turns ratio of T2. From (6), Dm 1 can be found
as
d = Dm 1 =
n2VO n2VO+ VC B
. (7)
From (5b),iD O 2(t) can be obtained as
iD O 2(t) = IO− iD O 1(t)|d= Dm 1. (8)
Fig. 5. Main waveforms of parallel boost–flyback–flyback converter in a line cycle. (a) Case I (M1 mode only). (b) Case II (both M1 and M2 modes).
TABLE IV
THECORRESPONDINGPARAMETERS OFCASESI–III ILLUSTRATIONEXAMPLE
While in M2mode, T2 operates in DCM. From Fig. 4(b) by
following the similar deriving procedure of (3d),iD O 2(t) can be obtained as iD O 2(t) = n2· ipk2· d3 2 = d2· VC B2 2fSLM 2VO d= dm 2 (9) where dm 2 is the instant duty ratio in M2 mode. Substituting
(3d) and (9) into (5b), it can be obtained as d = dm 2(θ) = 2fSPout LM 1Vi n p k2 sin2θ (LB+ LM 1)2 + V2 C B LM 2 (10)
where θ = ωL· t is the phase of sinusoidal line voltage, and Poutis the output power. In order to generate the complex duty dm 2, the compensator in the current-mode control had been op-timized to possess superior transient responses such as small rising time, low overshoot, and zero steady-state error. Addi-tionally, the compensator also can generate the correct duty dm 2 with different operation modes due to its superior performances. From (3d) and (5b), iD O 1(t) reaches maximum and iD O 2(t) reaches minimum at ωL· t = π/2. For case I, the
converter operates only in M1 mode (T2 operates in CCM), IO must be greater than the boundary valueID O 1P K+ ID O 2B
IO ≥ ID O 1P K + ID O 2B (11) where ID O 1P K is the peak value ofiD O 1(t) and ID O 2B is the boundary value of iD O 2 between CCM and DCM. The former can be obtained by replacing d with Dm 1 and vin(t)
with Vinpksin (π/2) in (3d), and expressed as ID O 1P K =
LM 1D2m 1Vinpk2
2fS(LB + LM 1)2VO
(12) and the latter can be obtained by replacing d with Dm 1 in (9) and expressed as ID O 2B = D2 m 1· VC B2 2fSLM 2VO . (13)
Furthermore, as IOis smaller than the boundary value in (11), M2 mode shows in the operation of the proposed converter as
plotted in Fig. 5(b). From the equality ID O 2= ID O 2B and (5b), the transition angle θT from M1to M2 mode can be expressed
as θT = ωL· tT = sin−1 2fS(LB + LM 1)2VO LM 1D2m 1Vinpk2 (IO− ID O 2B) . (14)
As IOgets smaller, the interval of M2becomes wider and M1
becomes narrower. It can also be seen from (3d) thatiD O 1(t) reaches zero at line voltage phase being 0 and π and from (5b) thatiD O 2(t) reaches maximum at the same time. Thus, as IO gets smaller than the boundary value of (13), the converter would work in M2 mode only during a half line cycle. Consequently,
for case II operation that the converter works in both M1 and M2modes in a half line cycle, IO will be in the range of
ID O 1B + ID O 2B ≥ IO ≥ ID O 2B. (15) Besides, for case III operation that the converter works only in M2 mode in a half of a line cycle, IO is smaller than the
boundary value
ID O 2B ≥ IO. (16)
Based on the earlier discussion, the theoretical currents and voltage waveforms for the cases I–III examples are illustrated in Fig. 5(a)–(c), and the corresponding parameters used are shown in Table IV. For the case I operation, the value of LM 2 in (13) intentionally selected a large one so that (11) can be satisfied and case I operation can present. For the other param-eters, LB, LM 1, n1, and n2, they are selected according to the
equations described in Section III so that cases II and III can be activated.
From Figs. 2 and 5(a)–(c), it can be seen that the average input currentiin(t) is divided into iD I 1(t) and iD B(t) through the operation of boost–flyback semistage. Among these two currents,iD O 1(t) is transformed to iD O 1(t) by the flyback cell, and then transferred to RLdirectly. Alternatively,iD B(t) is mainly buffered in CB during vin peak, then transformed to iD O 2(t) by the flyback dc/dc semistage, and then transferred to RLfor output regulation. The output current IO is primarily supplied byiD O 2(t) in low line voltage duration.
The switch current of conventional cascade S4 converter
like [3] mainly composed of inductor current of the boost-ICS semistage and the transformer primary current of the flyback semistage. Both semistages have to handle the whole input power. Hence, the peak switch current is doubled and reaches peak value when input power is the maximum and occurs at θ = π/2. In Fig. 2, the average switch current iS(t) of the
proposed converter is the sum of iD I 1(t) and iD I 2(t) and can be expressed as
iS(t) = iD I 1(t) + iD I 2(t) . (17a) BothiD I 1(t) and iD I 2(t) represent the charged current of the first semistage from line input and the transformer primary current of second semistage from bulk capacitor and can be
Fig. 6. Average switch current for case I.
obtained from Fig. 3(b) as
iD I 1(t) = iL B(t) − iD B(t) (17b) and iD I 2(t) = VO VC B iD O 2 (t) = VO VC B (IO − iD O 1(t)) . (17c) It can be seen from (17a) and (17c) that if iD O 1(t) in-creases, more output current will be provided by flyback cell, andiS(t) will be reduced. Contrarily, if flyback cell is absent
(i.e.,iD O 1(t) = 0), the circuit in Fig. 2(b) will be reduced to a conventional S2 converter [3]. Furthermore, from Fig. 3(b), iD I 1(t) can be further obtained as
iD I 1(t) = ipk1· d 2 = d2V inpksin (ωL· t) 2fS(LB+ LM 1) . (17d)
Substituting (3d) into (8) and the result is substituted into (17c),iD I 2(t) for M1 mode can be further expressed as
iD I 2(t) = VO VC B IO− LM 1D2m 1Vinpk2 sin2(ωL· t) 2fS(LB+ LM 1)2VO . (17e) Substituting (9) into (17c), iD I 2(t) for M2 mode can be
further obtained as iD I 2(t) = d2· V C B 2fSLM 2 d= dm 2 (17f) where dm 2 can be obtained from (10). It can be seen from (17d)–(17f) and Fig. 6 thatiD I 1(t) reaches local maximum at θ = π/2 whileiD I 2(t) is minimum, and iD I 2(t) reaches local maximum at θ = π/2 or π whileiD I 1(t) is zero. There-fore, the power processed by flyback cell is transferred to load directly and would not be processed by the switch again, the lo-cal maximum current stresses due to DP and IDP do not appear at the same time during half line cycle, so the overall current stress of main switch was small compared with that of conven-tional S4 converter.
III. ANALYSIS ANDDESIGN
A. Power Distribution and Bulk Capacitor Voltage
In the proposed S2PPFC scheme shown in Fig. 1, the power
distribution between the DP (p1) and IDP (p2 or p3)
process-ing paths is one of the important design considerations since it affects not only the converter efficiency but also the power rat-ings required to the components in each processing power path. Besides, in the IDP path, the energy balance between the power flow into (p2) and out (p3) of bulk capacitor determines the
bulk capacitor voltage, which can be very high if not properly designed. Based on the earlier design considerations, the power distribution will be analyzed according to the implementation circuit shown in Fig. 2(b), and hence the formula related to power distribution and bulk capacitance voltage can be derived. They are formulated as follows.
The input power pin is composed of p1and p2
pin(θ) = vin(t)iL B(t) = p1(θ) + p2(θ) . (18)
The DP processed by flyback semistage is given by p1(θ) = vin(t)
LM 1 LB+ LM 1
iD I 1(t) = VOiD O 1(t) . (19a) Substitution ofiD O 1(t) given by (3d) into (19a) gives
p1(θ) = 2kpPoutsin2θ (19b)
where kP is defined as the DP ratio and can be obtained as kp ≡ P1,pk(d) Pout = LM 1d 2V2 inpk 4fS(LB + LM 1)2Pout (20) and P1,pkis given by P1,pk(d) = LM 1d2Vinpk2 4fS(LB + LM 1)2 . (21)
In M1 mode, kp is a constant and can be found by
kp = kp|d= Dm 1 = KP 1. (22)
In M2 mode, kp is a function of θ and obtained by kp = kp|d= dm 2(θ )= kp2(θ) = LM 1· V 2 inpk 2 LM 1Vinpk2 sin2θ + V 2 C B LM 2 (LB + LM 1) 2. (23)
It can be seen from (23) that kp2 is independent of Pout. The
values of Dm 1and dm 2can be obtained from (7) and (10). The IDP processed by boost semistage from LB to CB is given by
p2(θ) = VC BiD B(t) . (24a) Substitution ofiD B(t) given by (4b) into (24a) gives
p2(θ) = MC Bsin2θ MC B − |sin θ| 2kpPout KM 1 (24b) where KM 1is called inductance ratio and expressed as
KM 1 = LM 1
LB
TABLE V
KID P INDIRECTPOWERRATIO
The dimensionless variable MC B in (4c) and (24b) can be re-garded as the normalized VC B with respect to Vinpk. In practice,
the true value of VC B is lower than the theoretical value because of presence of the equivalent series resistance (ESR) of induc-tance and capacitor. Thus, in order to avoid the bulk capacitor voltage VC Bfrom exceeding the limitation voltage, 450 V, of the commercial capacitor, it is suggested that MC B had better been controlled below or just equal to 1.2 for vac= 265Vrm s.
Fur-thermore, the IDP processed by flyback dc/dc semistage from CB can be expressed as p3(θ) = VOiD O 2(t) = Pout− p1(θ) = Pout 1− 2kpsin2θ . (26a)
Substituting (9) into (26a), p3for M2 mode can be expressed
as p3(θ) = d2· V2 C B 2fSLM 2 d= dm 2 = d 2· (M C B · Vinpk)2 2fSLM 2 d= dm 2 . (26b) Since p1and p2(or p3) vary with θ, they would be expressed
as Px,ave|x= 1,2,3 = 1 π π 0 px(θ) dθ x= 1,2,3 . (27)
Therefore, DP ratio KD Pis defined as KD P =
P1,ave Pout
. (28)
In this equation, high KD P implies high efficiency and large
utilization performance of T1. Because the average power sent
to and out from CB are equal for a half line cycle, the IDP ratio KID Pcan be defined as KID P = P2,ave Pout =P3,ave Pout = 1− KD P. (29)
The more detailed IDP ratio expressions defined in (29) for three cases can be derived as shown in Table V by substituting (24b) and (26a) into (27) and normalizing with Pout. By using
iterative approaching methodology for obtaining accurate MC B, the detailed expressions in Table V are calculated repeatedly until (29) is satisfied, and KD P, KID P, and MC B can be solved consequently. Following the iterative calculation process, the curves of DP ratio KD P versus output power Poutfor different
line input voltage vac and operation cases are obtained and
shown in Fig. 7, and the curves are obtained by taking the
Fig. 7. KD P versus output power for different va cand cases at the condition
of Table IV-case I.
converter parameters in Table IV–case I as an example. It can be seen from Fig. 7 that the relation between KD P and case is
(KD P)III> (KD P)II > (KD P)I. KD P increases as Pout is low
or vacis high.
The curves of KD P and MC B versus Pout for different KM 1 and LM 2 at the assigned conditions of the converter, LM 1= 150 µH, n2 = 1.7, Vac= 265 Vrm s, and VO = 54 V,
are shown in Fig. 8. Substituting (23) into case III of Table V, MC B obtained from (29) is independent of Pout. Hence, each MC B curve in Fig. 8(b) is horizontal when converter operates in case III. From Fig. 8(a), it can be seen that KD P is greater
at low output power. That is to say, KID P rises as output power
increases. This implies that the DP is the main portion provid-ing the load and the IDP is regarded as energy reservoir used for regulating the power flow to load. Besides, it can be seen from Fig. 8(b) that MC B increases as Pout decreases and
ap-proaches and holds to the maximum value at lighter load. This phenomenon shows that high bulk capacitor voltage will be re-sulted at high line and case III. However, from Fig. 8, it also can be seen that KD P goes up and MC B slides down as KM 1
increases. This is because more input power goes through fly-back cell without being buffered by CB. Hence, for the purpose of obtaining high efficiency and low VC B it is better to select KM 1 as large as possible. Furthermore, the decrease of LM 2 can lower both KD P and MC B since it can be seen from (9) that low LM 2 will result in large current iD O 2 for M2 mode
or equivalently to say that the output power ratio provided by CB will be increased. In other words, more output power comes from buffered energy and less input power passes through
Fig. 8. (a) KD P. (b) MC Bversus output power for different KM 1and LM 2, at LM 1= 150 µH, n2 = 1.7, Va c= 265 Vrm s, VO = 54 V.
flyback cell, so this will result in lower efficiency. However, it is good for reducing the maximum value of MC B since more power is continuously sent out from CB. Therefore, MC Bhas to be lower to achieve half line cycle average IDP balance in (29) as can be seen from (24b) and (26b). Besides, decreasing LM 2 would cause flyback dc/dc semistage closer to DCM but make worse output voltage regulation. A compromise is suggested for selecting proper value of LM 2 in considering of the proper values of VC B, KD P, and output voltage regulation. It can be
seen from Fig. 8 that curves (1) and (2) have high KD Pand the
maximum values of MC B are below or close to 1.2 among all curves. Thus, with the consideration of obtaining high efficiency and low VC B, curves (1) and (2) are better choices.
B. Design Equations
The design equations are going to be derived for the objectives of obtaining proper PFC and output voltage regulation. The DCM operation design of boost–flyback semistage is essential for obtaining good PFC. It can be seen from iL M 1waveform in Fig. 3(b) that to guarantee T1operating in DCM, d1TS should
be smaller than (1 − d)TS. Thus, n1 should be designed to
satisfy the following equation derived from (3c) n1 ≥ KM 1 (KM 1+ 1) Vinpk VO dpk (1− dpk) (30a) where dpkis the duty ratio occurring at θ =π2as shown in Fig. 5.
From (30a), the minimum turns ratio for T1to operate in DCM
is obtained as n1 ≥ n1,m in= KM 1 (KM 1+ 1) Vinpk,m in VO dpk,m ax (1− dpk,m ax) (30b) where dpk,m axis the maximum of dpkand occurs at the lowest
rectified line input voltage vin(t) = Vinpk,m in|sin(π/2)| and the
largest output power. With conservative design, dpk,m axcan be
replaced with the acceptable maximum value.
Similarly, to guarantee LBoperating in DCM, d2TSshould be
smaller than (1− d)TS. Thus, LB and LM 1should be designed
to satisfy the following equation derived from (2c): (1− dpk)≥ LB (LB + LM 1) dpk (MC B− 1) (31a) where MC Bcan be solved from (29) and Table V. From previous section, it can be known that MC B will slide down and dpk
thus rises as output power is increasing. Thus, the worst DCM condition occurs at the low input voltage and the large output power for universal application. From (31a), the minimum time ratio needed for iL B to decay to zero before the end of switch
OFFtime duration can be obtained as Ddz = LB (LB+ LM 1) dpk,m ax (MC B ,m in − 1) (31b) where MC B ,m in = VC B ,m in/Vinpk,m in, and VC B ,m inis the
min-imum bulk capacitor voltage occurring at the lowest recti-fied line input voltage and the largest output power. However, the converter needs sufficient secondary open voltage of dc/dc semistage transformer T2, VC B/n2, to guarantee the output
reg-ulation operation all the time even at vin(t) = 0. Hence, for
flyblack dc/dc semistage, the following relation must be satis-fied VC B n2 dz c (1− dz c) = VO (32a)
where dz c is the duty ratio at vin(t) = 0 as denoted in Fig. 5.
It can be seen from (32a) that VO is decreasing as n2 increases.
Thus, after rearranging (32a), the turns ratio limitation of T2is
obtained as n2 < VC B ,m in VO dz c,m ax (1− dz c,m ax) = n2,m ax (32b)
where dz c,m ax is the maximum dz cwhile occurring at the low-est rectified line input voltage and the larglow-est output power, and n2,m ax is the upper bound of n2 to satisfy output voltage
requirement shown in (32a). C. Example and Design Procedure
To verify the proposed boost–flyback–flyback converter, a prototype converter with the following specifications was de-signed:
1) ac input voltage (vac): 85–265 Vrm s;
2) output voltage (VO): 54 V;
3) maximum output power (Pout,m ax): 80 W;
4) switching frequency (fS): 100 kHz;
5) maximum duty ratio (Dm ax) at vac = 85 Vrm s: 0.44.
As the suggested criterion [17] for universal input voltage S2 converter, the main design objective is to comply with the line current harmonic standards such as IEC61000-3-2 class D, to keep bulk capacitor voltage below 450 V, and to filter output ripple as small as possible.
From the previous section, it can be known that LB tends to operate in CCM as input voltage decreases and load increases, thus at this condition the harmonic current will get large. Fur-thermore, the bulk capacitor voltage will be high and may in-crease over 450 V at high line and light load. While considering the object of input current, the DCM operation gives a better
Fig. 9. Dd z and (1− dp k , m a x) versus LM 1 for different LB, LM 2=
1.5 mH, at Dm a x= 0.42, va c= 85 Vrm s, VO = 54 V, and Po u t= 60 W.
Fig. 10. MC B , m in and n2 , m a x versus LM 1 for different LB, LM 2=
1.5 mH, at Dm a x = 0.42, va c = 85 Vrm s, VO = 54 V, and Po u t= 60 W.
TABLE VI
PARAMETERS OFCRITICALCOMPONENTS
PF in comparing with that given by the CCM operation. How-ever, the CCM operation offers higher conversion efficiency and lower switch current stress than those given by the DCM op-eration. For the regular design, it is not easy to be realized in practice that LBoperates in DCM under the lowest line and the fullest load condition. Hence, it is not necessary for LB to op-erate in DCM during the whole half cycle, and the worst DCM condition for LB in this example is set at vac = 85 Vrm s, and Pout = 60 W. It is permissible that LBoperates in CCM during
Fig. 11. Measured line voltage, bulk capacitor voltage, line current, output voltage. (a) va c = 85 Vrm s, Po u t= 60 W. (b) va c= 265 Vrm s, Po u t=
60 W. (c) va c= 265 Vrm s, Po u t= 20 W.
a small interval within a half line cycle, that is also called semi-continuous conduction mode (SCM) [17] while vac = 85 Vrm s
and Pout> 60 W, as long as the IEC regulation can be satisfied.
With the substitution of the earlier specifications to (30b), DCM condition for T1could be reached as long as n1and KM1 were
properly selected. However, LM 1and LB cannot be determined by (31b) directly since LM 2must be assigned in advance, and further, MC B, m i n and dpk,m axhave to be calculated. For the
ob-ject of low bulk capacitor voltage, MC B had better no more than 1.2 at high line and light load condition in order to guarantee VC B below 450 V by properly selecting KM 1 and LM 2. The critical parameters LB, LM 1, n1, LM 2, and n2 are interrelated
and designed from the following procedure.
1) Assign LM 2 at first, and calculate MC B ,m in and
Fig. 12. Measured switching waveforms. (a) M1 mode. (b) M2 mode at va c = 130 Vrm s, RL = 60.24 Ω.
Section III-A at the preset worst DCM condition of LB, vac = 85 Vrm s, and Pout = 60 W.
2) Generate the curves of (1 − dpk,m ax) and Ddz versus LM 1 for different LB by using equation (31b) with the calculated MC B ,m in and dpk,m axin step 1.
3) Generate the curves of n2,m ax versus LM 1 for different LB with substituting MC B ,m in and dz c,m ax in (32b), and
set dz c,m ax to 0.42 while Pout = 60 W to prevent from
over 0.44 when Pout = 80 W.
4) Select LM 1 and LB from the curves of (1 − dpk,m ax)
and Ddz provided from step 2 such that LB can operate in DCM at the preset worst DCM condition, and hence KM 1 = LM 1/LB is determined.
5) Select n2with selected LM 1and LB from n2,m axcurves
given by step 3 such that flyback dc/dc semistage can correctly fulfill output regulation.
6) Select n1 with the selected KM 1from step 4 substituted
to (30b) such that T1 can operate in DCM.
7) Calculate MC Bat high line and light load with the selected LB, LM 1, n1, LM 2, and n2 by following the iterative
calculating process in Section III-A.
8) Check MC B whether it is below 1.2 at high line and light load or not. If not, reduce LM 2and repeat steps 1–7 until MC B is equal to or smaller than 1.2 at high line and light load.
Following these procedures, the final curves of (1− dpk,m ax)
and Ddz are shown in Fig. 9, the curves of n2,m ax are shown
in Fig. 10, and the designed parameters of key components are obtained as LB = 30 µH, LM 1 = 150 µH, n1 = 1.6, LM 2 = 1.5 mH, n2 = 1.7.
Fig. 13. (a) Line voltage and line current measured at worst condition. (b) Harmonic content and class D limits.
IV. EXPERIMENTALRESULTS
For presenting the performance of the prototype based on the proposed topology, the circuit of Fig. 2(b) and (c) has been built and tested in the specifications described in Section III-C. The parameters of the critical components are given in Table VI. Because the input current iin = iL B of the proposed converter is pulsating when LB operates in DCM, the electromagnetic
interference (EMI) level would be above the limits of standard such as Federal Communications Commission (FCC) or In-ternational Special Committee on Radio Interference (CISPR). Hence, an input filter with low input displacement angle be-tween input voltage and current, minimum interaction with the converter and system stability are designed to attenuate EMI to meet regulatory specifications and get smooth waveform of line input current iacin Figs. 11 and 13(a). The detailed design and
analysis about input filter could be referred to [18] and [19]. The key waveforms at vac = 85 Vrm s/Pout = 60 W, vac =
265 Vrm s/Pout = 60 W, and vac = 265 Vrm s/Pout = 20 W are
presented in Fig. 11, and the switching waveforms for M1mode
and M2 mode at vac = 130 Vrm s/RL = 60.24 Ω are presented
in Fig. 12. As can be seen, the shapes of line input current iacare
Fig. 14. Measured bulk capacitor voltage under line and load variations.
Fig. 15. Measured power factor under line and load variations.
Fig. 16. Measured efficiency under line and load variations.
measured key waveforms at the worst condition (vac = 85 Vrm s
and Pout = 80 W) are shown in Fig. 13(a). Although the line
input current is distorted due to the SCM operation of LB, its harmonic contents still comply with the class D limits as shown in Fig. 13(b). Fig. 14 shows the measured bulk capacitor volt-age under line and load variations. The maximum bulk capacitor voltage is 415.4 V, which is below the commercial size 450 V and occurs at vac = 265 Vrm swith Pout = 20 W. Fig. 15 shows
measured power factor under line and load variations. It can be seen that the lowest power factor is 0.91 and occurs at the worst
condition. The power factors at most conditions are above 0.95 and some even reach 0.99. As described in Sections III-B and III-C, LB tends to operate in CCM as input voltage decreases and load increases, and the worst DCM condition for LBis set at vac = 85 Vrm sand Pout = 60 W. Hence, LB begins to operate in SCM when Poutis greater or equal to 60 W. Consequently, iacis distorted and PF degrades as can be seen vac = 85 Vrm s
curve in Fig. 15. Fig. 16 shows efficiency under line and load variations. The efficiency is greater than 80% in most operating range, and the maximum value is 85.8% at vac = 130 Vrm swith Pout = 60 W.
V. CONCLUSION
The SSTO boost–flyback converter and corresponding S2 par-allel converter were introduced in this paper. The SSTO boost– flyback converter has appreciable self-PFC property when op-erates in DCM. By cascading dc/dc semistage to the boost cell output of boost–flyback converter, the S2 parallel converter can
achieve input line current shaping and tight output voltage reg-ulation with single-loop feedback control. Since partial of input power is processed only once by flyback cell, so the conversion efficiency is improved and the switch current stress is small compared with the conventional S2 converter. The proposed
circuit has two parallel power streams so that the components could be small. Furthermore, the analysis of the implemented circuit and the design procedure for universal application are also presented. With this procedure, an 80 W prototype was built and tested. The experimental results show that the volt-age across bulk capacitor is kept under 415.4 V for full range operation (85–265 Vrm s) and load (20–80 W). The maximum
power factor is 0.99 and the measured line current harmonic contents at the worst condition comply with the IEC61000-3-2 class D limits. The maximum efficiency is 85.8%. This new circuit structure also can be extended to more alternative par-allel combinations. Therefore, the proposed parpar-allel converter presents an overall good performance in the main aspects of universal S2PFC converters.
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Heng-Yi Li was born in Taipei, Taiwan, in August
1963. He received the B.S. degree from the National Taiwan University of Science and Technology, Taipei, and the M.S. degree from the National Taiwan Uni-versity, Taipei, in 1990, both in mechanical engi-neering. Currently he is working toward the Ph.D. degree at the Institute of Electrical and Control En-gineering, National Chiao Tung University, Hsinchu, Taiwan.
He is currently a Staff Member at the Insti-tute of Nuclear Energy Research, Taoyuan, Taiwan. His main responsibilities include plasma power development and computer-controlled system design. His recent research interests include ac-to-dc power factor correction circuit, high-frequency inverter, and system modeling and control.
Hung-Chi Chen was born in Taichung, Taiwan,
in June 1974. He received the B.S. and Ph.D. de-grees from the Department of Electrical Engineering, National Tsing-Hua University (NTHU), Hsinchu, Taiwan, in June 1996 and June 2001, respectively.
From October 2001, he was a Researcher at the Energy and Resources Laboratory (ERL), Industrial Technology Research Institute (ITRI), Hsinchu. In August 2006, he joined the Department of Electrical and Control (ECE), National Chiao Tung University (NCTU), Hsinchu, where he is currently an Assistant Professor. His research interests include power electronics, power factor correc-tion, motor and inverter-fed control, DSP/MCU/FPGA-based implementation of digital control.
Lon-Kou Chang (M’87) received the B.S. degree
from the Chung Yuan Christian University, Chung-Li, Taiwan, in 1975, the M.S. degree from the Na-tional Chiao Tung University, Hsinchu, Taiwan, in 1977, both in electronics engineering, and the Ph.D. degree in electrical engineering from the University of Maryland, College Park, in 1995.
From 1983 to 2008, he was an Associate Professor of electrical and control engineering at the National Chiao Tung University. During 1982–1985, he was a part-time Electrical Supervisor for the Tri-Service General Hospital, Taipei, Taiwan. He was also an R&D Consultant of Sun-pentown Int. Co., Taiwan, from 1996 to 1998. He is currently a Consultant at Macroblock Incorporation, Hsinchu. His recent research interests include power converter topology design, LED lighting, and ESD and latch up protection de-sign for power ICs.
