904 IEEE TRANSACTIONS ON ELECTRON DEVTCES, VOL. 43, NO. 6, JUNE 1996
Back-Gate Forward Bias Method for
Low-Voltage
CMOS Digital Circuits
Ming-Jer Chen, Member, IEEE,
Jih-ShinHo,
Tzuen-HsiHuang, Member, IEEE,
Chuang-Hen Yang,
Yeh-Ning Jou,
andTerry Wu
Abstruct- The hack-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter em- ploying the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc volt-
age transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4
V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current. Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS ana- log/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
1. INTRODUCTION
N CMOS digital circuits the power dissipated in the dy- namic active mode is proportional to the square of power supply voltage and thus lowering the supply voltage can help achieve the objective of low power consumption for the battery-operated portable applications. Simultaneously, the threshold voltage of MOSFET’s must be reduced in order to maintain the operating speed as high as possible. However, a reduction in threshold voltage can increase exponentially the stand-by subthreshold current. This problem can be overcome in the circuit level by using high threshold voltage MOS- FET’s from multi-threshold
CMOS
process [ 11 or inserting the switched impedance into the source[2],
[ 3 ] . Very recently, a novel back-gate reverse or forward bias scheme [4]-[6] has been introduced as an efficient trade-off between switching speed and subthreshold power. In [4], a near-zero threshold voltage was obtained by modifying the threshold implant mask, which was then electrically increased by reverse biasing the back gate to the level suitable for operation in the active mode, and optionally in the stand-by mode can further be increased to another higher level such as to maintain a very low subthreshold current. In [5] and [6], the back-gate forward bias method was achieved by tying together the gate and body of MOSFET’s, creating a three-terminal gated lateral bipolar transistor and thus constituting the so called dynamic Manuscript received November 6, 1995. The review of this paper was arranged by Editor K. Tada. This work was supported by the National Science Council under Contract NSC 84-2215-E-009-043.M.-J. Chen, J . S . Ho, T.-H. Huang, C.-H. Yang, and Y.-N. Jou are with the Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
T. Wu is with the Electronics Research and Service OrganizationiITRI, Mixed-Mode Integrated Circuits Department, Hsinchu 300, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9383(96)04027-0.
threshold voltage characteristics; however, only SO1 (Silicon- On-Insulator) or oxide isolation process is possible to realize since a common p- or n-type substrate is inhibited in this scheme. On the other hand, the back-gate forward bias method in terms of a four-terminal gated lateral bipolar transistor in a MOSFET structure as cited in [7] and [SI possesses two competitive abilities as compared with [4]-[6]: it is fully compatible with present low-cost, high-yield standard bulk CMOS processes; and the threshold voltage in the active mode can be electrically reduced, without any mask or process modification.
In this paper we promote the back-gate forward bias method suitable for present standard bulk CMOS processes to the circuit level for low-voltage digital application. Transient switching waveforms and dc transfer characteristics measured from a CMOS inverter employing the method at reduced supply voltages will be given. Guidelines for ensuring proper implementation of the method in a bulk CMOS process will be set up. A new low-voltage, low-power, high-density mixed- mode CMOS analog/digital integrated circuits chip will further be projected to highlight the potential of the method.
11. METHOD AND RESULTS
The method of forward biasing the back gate or bulk with respect to the source in the dynamic active mode is schematically shown in Fig. 1 for a bulk CMOS inverter. The CMOS inverter was fabricated by one of existing standard bulk CMOS processes. The gate width to length ratio W/L of p- and n-MOSFET’s were 20 pm/0.8 pm and 20 pm/0.9 pm, respectively. The gate oxide thickness was about 163
A.
The corresponding drain current versus gate voltage characteristics measured with the back-gate forward bias as parameter are plotted in Fig. 2. From Fig. 2 we can observe that at high gate voltages a small back-gate forward bias produces a small increase in the drain current while this current increase is magnified with reducing the gate voltage. Here we define the threshold voltage Vth as the gate voltage delivering a fixeddrain current of 1 x l o p 5 A. The threshold voltage extracted from Fig. 2 as function of the back-gate forward bias for n- and p-NlOSFET’s is plotted in Fig. 3. From Fig. 3, it can be clearly seen that for each MOSFET an increase in the back-gate forward bias from 0 V to 0.4 V can lower the threshold voltage magnitude from 0.52 V down to 0.31 V for
n-MOSFET and from 0.55 V down to 0.40 V for p-MOSFET.
The measured dependencies on the back-gate forward bias in 0018-9383/96$05.00 0 1996 IEEE
CHEN et al.: BACK-GATE FORWARD BIAS METHOD 905
In
the Active Mode
Fig. 1 . inverter.
The back-gate forward bias method employed for a bulk CMOS
Fig. 3 can be reasonably reproduced by [7], [8]
&h = a1
+
a z z / a 3 - V B s
(1)where VBS = VB, or V,,;V,, = and lVthp/ for
n- and p-MOSFET's, respectively; and a l , az, and a3 are
three process-dependent parameters to be fitted. The fitting parameter values of a1 = 0.027 V , a z = 0.635 VI/', and
a3 = 0.603 V for n-MOSFET as well as al = 0.220 V, a2 =
0.446 V1/'. and a3 = 0.558 V for p-MOSFET both lead to good agreement as demonstrated in Fig. 3.
-4 10 -10
I , ,
I I I , , , I I I # , , , , , , , I I,I t,, I I, I
10 0.0 0.5 1.0 1.5VG
(v) (a) F ' ' ' ' ' ' ' ' ' I ' ' ' ' ' ' ' ' ' I ' ' ' ' ' ' ' ' ' 3 -4 10 -10L a ,
, , , , , , I , , , ,,(, ,, I , , , , , , , ,, j
10A. DC Voltage Transfer Characteristics
The measured dc inverter characteristics for two different 0.0 -0.5 -1.0 -1.5
power supply voltages in terms of both the output voltage VG
m>
versus input voltage curves and the power supply current versus input voltage curves are plotted in Fig. 4 each with a decrease in the & h n causes a decrease in the critical input voltage needed to tum on the n-MOSFET and pull down
(b)
different combinations of back-gate forward biases. Intuitively, Fig. 2. The measured drain current versus gate voltage characteristics with the back-gate forward bias as parameter for both MOSFET's in a CMOS inverter,
the output to the ground. On the other hand, a decrease in
the magnitude of produces an increase in the critical that the direct current power dissipation in the active mode is
input voltage needed to turn on the p-MOSFET and pull up as 'Ompared with the dynamic One'
the output to the supply voltage VDD. This tendency agrees with Fig. 4(a): applying the back-gate forward bias VB, in p- MOSFET shifts the transition region along the input voltage axis toward the high voltage level while the back-gate forward bias V,, in n-MOSFET pushes the transition region to the low voltage level. Traditionally, the transition region adjustment to the midway between high and low levels was performed primarily through the channel width ratio. Thus, the back-gate forward bias method can provide an efficient alternative to adjust the transition region to around the midway between high and low levels. Further observation of the measured direct current characteristics in Fig. 4(b) reveals that: 1) the peak current occurring at the transition region decreases with decreasing the power supply voltage; and 2) application of a back-gate forward bias can raise significantly the current. Note
B. Transient Switching
Transient experiment was performed by means of the pulse generator HP 8 110A and the storage digitizing oscilloscope Tektronix 11 402A. The measurement conditions were: the input voltage waveform with high-level VH = V,, and low- level V, = 0 V as well as with the rise and fall times both fixed at 15 ns; and the power supply voltage Voo ranging from 1.5 V down to 0.6 V. The reason for the minimum
VDD value of 0.6 V in our work is that for gate voltage less than this value, the amount of the drain current, as seen in Fig. 2, is comparable with the leakage current ( % l o p 7 A) through the oscilloscope probe in the transient experiment. Fig. 5 demonstrates the measured voltage waveforms at the input and output with and without the back-gate forward bias
906 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996 Y
4
-
0.60 0.55 0.50 0.45 0.40 0.35 0.30 " " 1 " " " " " " 1 " " " ' 1 " ' ' 1 ' ' " 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40Back -Gate Forward Bias V,, or VBp (v)
Fig. 3 .
forward bias for both MOSFET's.
The measured and calculated threshold voltage versus the back-gate
method for three different power supply voltages of 0.6, 0.8,
and 1.0 V. From Fig. 5 we can observe that not only the
fall time in the output pull-down waveform but also the rise time in the output pull-up waveform are decreased with the method applied. Evaluation of improvement in the switching speed due to back-gate forward bias can further be obtained by plotting the measured delay time t d versus the power supply
voltage V ~ D in Fig. 6. From Fig. 6 it can be seen that: 1) from
Voo
= 1.5 V to about 1.0 V the change in the delayE
U3
n
n
U 1o-2
1o - ~
l(r6 10-10 0.0 0.5 1.0 1.5 'in0
time is gradually slow while further reduction of VDD can dramatically increase the delay time; and 2) the delay time can be substantially decreased by the back-gate forward bias time
i S reduced by a large factor of about 3.0 at
voo
= 0.6v.
Also plotted in Fig. 6 are the calculated results by a simple
delay time formula [9]
(b)
at low power the Fig. 4. (a) The measured voltage transfer characteristics for two different
power supply voltages each with three different combinations of back-gate forward biases in a CMOS inverter; and (b) the corresponding measured power supply current versus the input voltage.
where C:L is the output capacitance; and I d n and Id, are the drain saturation currents of n- and p-MOSFET's, respectively. With the measured I-V characteristics of both MOSFET's in Fig. 2 as input parameters for the currents I d n and Idp in
( 2 ) , the equivalent value of the output capacitance CL in the measurement has been extracted to be 6 2 pF by fitting the eight data points in Fig. 6. The calculated delay times versus the power supply voltage are plotted in Fig. 6 . From Fig. 6 we can observe that excellent agreements with the measured ones with and without the back-gate forward bias method are simultaneously achieved. Further calculation has been performed using (2) with the same I-V characteristics in Fig. 2 for a small C L = 100 fF typically encountered in the internal circuitry, as plotted in Fig. 7. From Fig. 7 we can clearly observe that: 1) without the proposed method the delay time dramatically changes over the low power supply voltage range between 0.5 V and 1 .0 V; and 2) a relatively slow change in the delay time less than 800 ps is obtained with back-gate
forward bias. Note that the supply voltage range in Fig. 7 is free from latch-up and impact ionization as explained later.
111. THE GUIDELINES
Since the implementation of the method requires the bulk or substrate forward biased, guidelines must be carefully established in order to avoid malfunction or permanent damage caused by parasitic bipolar, impact ionization, latch-up, and stand-by current. This is achieved by constraining quantita- tively the range of the supply voltage and forward bias as demonstrated below.
First, the range of 0
5
V,,5
0.4 V and 05
VB,5
0.4 V can guarantee the action of the gated lateral bipolar transistors in low-level injection; that is, the parasitic bipolar far away from the surface is essentially inactive. We have measured a considerable amount of the current disturbing the nearby circuitry only for V,,>
0.5 V or VB,>
0.5 V. Further, the power supply voltage VDD is limited to below about 2 V for elimination of impact ionization at the drain. This can make the hot carrier effect due to impact ionization less ofCHEN et al.: BACK-GATE FORWARD BIAS METHOD
output
Pull-up:
Output
P u l l - D o ~ :
Fig. 5.
back-gate forward bias.
The measured input and output voltage waveforms in a CMOS inverter for three different power supply voltages each with and without the
the problem. Under this situation, the base current reversal
[lo],
as
an indicator of impact ionization, disappears. Thelatch-up test experiment has been performed on the long- stripe standard latch-up structure with the back-gate forward bias as parameter. Fig. 8 depicts the measured latch-up I-V characteristics for an n-p spacing of 6 ,um with V,, = VB, =
0.2 V and VB, = V& = 0.4 V. From Fig. 8, we can observe
that the holding voltage for sustaining the latch-up is about 1 V and thus a maximum supply voltage of 1 V can guarantee
latch-up free operation. Therefore to ensure proper utilization of the back-gate forward bias method, in this work the supply voltage is limited to less than 1 V, which in turn automatically eliminates the impact ionization.
To overcome the increased subthreshold current due to the method, the source impedance switch as described in detail in [1]-[3] is suggested as a design guideline in the circuit level. By combining the back-gate forward bias method and the source impedance switch, we have measured a great reduction
908 16 12 0.8 - 0.6 - 0.4 - 0.2 - - - i n 3 4 -0 Experiment 0 v,, -v,,-ov 0 VB, = VB,
-
0.4V ; p-sub(
n-well . - , . _ . . . _ . . _ . . . . - ~ . - ~ . - . - ~ ~ - ~ VBn-
v,,-
0.2v VB,,-
VB,-
0 . 4 V _ _ _ - _ ' ~ " ~ " " ~ " ~ ~ ' " " " " ' ' ' 'I
~ (2) with C,-
62pF t -"B1 0 0 0 " " " " " ' " " " " ~ 0.5 0.7 0.9 1.1 1.3 1.5Power Supply Voltage VDD (V)
The comparison of measured and calculated delay times versus power Fig. 6.
supply voltage with and without the back-gate forward bias.
-
e t
} 0.4V
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996
20 , , / , , 1 , / , , 1 , , , , / , / / , , , 1 , , , , 1 , , , , , S = G b m VDD Pulse Scheme ~ 0.0 t ' " ' I ' " ' I , " ' I ' " I ' "
' 1
0.5 0.6 0.7 0.8 0.9 1.0Power Supply Voltage VDD (V)
Fig, 7.
without the back-gate forward bias for C L = 100 fF.
The calculated delay times versus power supply voltage with and
in the subthreshold current by about three orders of magnitude, comparable with those reported in [ 11-[3]. Another alternative choice is also suggested as schematically shown in Fig. 9. The back-gate bias pulse waveforms in Fig. 9 can be separated into two distinct components: the active mode and the stand- by mode. In the active mode the aforementioned back-gate forward bias method is employed while the back gate or substrate is reverse biased in the stand-by mode in order to maintain a very low subthreshold current. The back-gate bias pulse waveforms in Fig. 9 can be provided extemally or generated on chip.
IV. THE IMPACTS
Following the above guidelines, the method based on a four- terminal gated lateral bipolar transistor in low-level injection can produce several important features for low-voltage digital circuit application: 1 ) the transition region of the dc voltage
VDD
Fig. 9. Inverter.
The back-gate bias pulse scheme suggested for the bulk CMOS
transfer characteristics can be electrically adjusted to around the midway between high and low levels; and 2) the switching speed can be substantially improved. Further combining the source impedance switch [1]-[3] or the pulse waveforms in Fig. 9, low power demand can be achieved. It is noticeable that under the suggested range for
VB,
and V&, the base or bulk current is negligible (i.e., an amount of about lo-'' A was measured in the bulk atVB,
= 0.4 V orV&
= 0.4 V),CHEN et al.: BACK-GATE FORWARD BIAS METHOD
implying an inherent high-gain feature. This thereby signifi- cantly lowers the power consumed externally for provision of the back-gate forward bias or by on-chip back-gate forward bias generator circuitry (i.e., the band gap voltage references plus the comparators). Therefore, the present standard bulk
CMOS processes can be readily utilized for realization of
low-voltage, low-power digital circuits without any process or mask modification. Moreover, the original merit of low cost and high yield can be maintained along with the resultant comparable performances. For example, Fig. 3 shows a low- threshold voltage of 0.31 V at V B ~ = 0.4 V, which is comparable to that (= 0.3 V) obtained by multi-threshold CMOS process [ l ] ; and Fig. 7 shows a three times reduction in delay time for Voo = 0.6 V. which is also comparable to those obtained by using SO1 process as cited in
[ 5 ] .
On the other hand, the same method has recently found new application in low-voltage, low-current, high-density CMOS analog integrated circuits [ 1 11: a substantial improvement in match between the identically drawn small-size devices has been characterized over the weak inversion and moderate inversion region between weak and strong inversion. This is achieved by operating MOSFET’s as four-terminal gated lateral bipolar transistors in low-level injection. The created better precision over the conventional MOSFET’s is due to forward back-gate bias effect and has been successfully reproduced by a new mismatch model [ll]. Apparently, by following the same guidelines, both reasonable digital speed and improved analog precision can be readily combined on the same chip. To highlight the potential of the back-gate forward bias method, a cost-effective mixed-mode low-voltage, low- power, high-density CMOS analog/digital integrated circuits chip is thus projected for the first time.
V. CONCLUSION
The back-gate forward bias method has been examined experimentally in the present standard bulk CMOS processes, exhibiting the abilities for low-voltage digital applications: electrically adjusting the transition region of the dc voltage transfer characteristics as well as substantially improving the switching speed. Guidelines for proper implementation of the method have been established. A new low-voltage, low-power, high-density mixed-mode
CMOS
analog/digital integrated circuits chip has been projected to highlight the potential of the method.ACKNOWLEDGMENT
The comments and suggestions of the reviewers for substan- tial improvement of the manuscript are very much appreciated.
REFERENCES
[ 1 I S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1 V high- speed digital circuit technology with 0.5 u m multi-threshold CMOS,” in Proc. IEEE Int. ASIC Con$ and Exhibit, Sept. 1993, pp. 186-189. [21 M. Horiguchi, T. Sakata, and K. Itoh, “Switched-source-impedance
CMOS circuit for low standby subthreshold current giga-scale LSI’s,” IEEE J. Solid-state Circuits, vol. 28, pp. 1131-1135, Nov. 1993. [3] T. Kawahara, M. Horiguchi, Y. Kawajiri, G. Kitsukawa, T. Kure, and
M. Aoki, “Subthreshold current reduction for decoded-driver by self-
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reverse biasing,” IEEE J. Solid-State Circuits, vol. 28, pp. 1136-1 144, Nov. 1993.
J. B. Burr and J. Shott, “A 200 mV self-testing encoderldecoder using Stanford ultra-low-power CMOS,” in IEEEInt. Solid-State Circuit Con$, Dig. Tech. Papers, Feb. 1994, pp. 84-85.
F. Assaderaghi, D. Sinitsky, S . Parke, J. Bokor, P. K. KO, and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” in IEEE Int. Electron Devices Mtg., Tech. Dig., Dec. 1994, T. Andoh, A. Furukawa, and T. Kunio, “Design methodology for low- voltage MOSFET’s,” in IEEE Int. Electron Devices Mtg., Tech. Dig., Dec. 1994, pp. 79-84.
T. H. Huang and M. J. Chen, “Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET struc- ture,’’ Solid-State Electronics, vol. 38, pp. 115-1 19, Jan. 1995. J. S. Ho, T. H. Huang, and M. J. Chen, “High gain p-n-p gated lateral bipolar action in a fully depleted counter-type channel p-MOSFET structure,” Solid-Stute Electron., vol. 39, pp. 261-267, Feb. 1996. C. Hu, “Low-voltage CMOS device scaling,” in IEEE Int. Solid-State Circuit Con$, Dig. Tech. Pupers, Feb 1994, pp. 86-87.
r.
H. Huang and M. J. Chen, “Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar transistor,” lEEE Trans. Electron Devices, vol. 42, pp. 321-327, Feb. 1995. M. J. Chen, J. S. Ha, and T. H. Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling,” I E E E J . Solid-State Circuits, vol. 31, pp. 259-262, Feb. 1996. pp. 809-812.Ming-Jer Chen (S’77-M’86) was born in Tai-
wan, R.O.C., on April l, 1954. He received the B.S. degree with highest honors from the National Cheng-Kung University, Tainan, Taiwan, in 1977, and the M.S. and Ph.D. degrees from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1979 and 1985, respectively, all in electrical en- gineering. His doctoral work involved the modeling and prediction of CMOS latch-up.
From 1979 to 1980, he worked at Telecommu- nication Laboratories. establishing a multiurocessor distributed system. From 1985 to 1986, he conducted post-doctoral research on CMOS latch-up at NCTU. From 1986 to 1992, he was an Associate Professor, and in 1993 became a Professor in the Department of Electronics Engineering at NCTU. From 1987 to 1992, he set up a series of design rules for the Taiwan Semiconductor Manufacturing Company. His current research interests include deep submicron reliability, low power integrated circuits, and subthreshold CMOS and BiCMOS technologies for new applications. He holds four patents in the above fields.
Dr. Chen has served as a reviewer for international journals such as IEEE ELECTRON DEVICE LETTERS, IEEE TRANSACTIONS ON ELECTRON DEVICES, Solid- State Electronics, and the Journal of the Chinese Institute of Engineers. He is a member of Phi Tau Phi.
Jih-Shin Ho was born in Taiwan, R.O.C., on July 13, 1966. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1988. He is currently working toward the Ph.D. degree at the Institute of Electron- ics, National Chiao-Tung University. His research interests include the CMOS device modeling and mismatch analysis in subthreshold region, and low power, low voltage mixed-mode integrated circuits design.
910 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996
circuit integration.
Tzuen-Hsi Huang (S’88-M’95) was born in
Taiwan, R.O.C., on April 14, 1966. He received the B.S. degree in electrical engineering from National Cheng-Kung University. Tainan, Taiwan, and the Ph.D. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1988 and 1995, respectively.
Recently, he joined the Department of High- Frequency Device Development in ERSOIITRI, Hsinchu, Taiwan. His research fields include the silicon bipolar device modeling and BiCMOS
Chuang-Hen Yang was born in Taiwan, R.O.C.,
on November 8, 1968. He received the B.S. degree in electrical engineering from Chung Yuan Christian University, Chung-Li, Taiwan, in 1993, and the M.S. degree in electronics engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 1995. His interests include low-power, low-voltage CMOS technology and alpha particle induced effect.
Yeh-Ning Jou was born in Taiwan on December 28, 1968. He received the B.S. degree in applied physics from Tamkang University, Tamsui, Taiwan, in 1992 and the M.S. degree in electronics engineering from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan in 1995.
From 1995 to 1996, he was involved in the processing o f 0.35 p m CMOS Reliability at MoselNitelic Inc., Hsinchu. He has been interested in the reliability study o f deep submicron CMOS devices.
Terry Wu received the M.S. degree in communica-
tion engineering from National Chiao-Tung Univer- sity, Hsinchu, Taiwan, in 1987.
Since joining ERSOflTRI, Hsinchu, in 1982, he has been engaged in the design of bipolar and CMOS analog integrated circuits. Since 1990, he has been the design manager of the Mixed-Signal IC De- partment of ERSOIITRI, responsible for the design of high-speed and high-resolution data converter IC, PLL IC, and high-frequency continuous-time filter IC with auto-tuning function.
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