计算机专业英语（第二版） - 万水书苑-出版资源网

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(1)Chapter 2 Basic Organization of Computers. 学习指导计算机主要由中央处理器、存储设备以及输入、输出设备等组成。通过本章的学习，读者应掌握以下内容：  计算机结构与硬件的主要术语  计算机的组成与各部分的功能，并能用英语表述  专业词汇的构成规律，特别是常用词缀及复合词的构成. 2.1. Introduction. In this chapter, we examine the organization of basic computer systems. A simple computer has three primary subsystems. The central processing unit, or CPU, performs many operations and controls the computer. A microprocessor usually serves as the computer’s CPU. The memory subsystem is used to store programs being executed by the CPU, along with the program’s data. The input/output, or I/O, subsystem allows the CPU to interact with input and output devices, such as the keyboard and monitor of a personal computer, or the keypad and digital display of a microwave oven. Most computer systems, from the embedded controllers found in automobiles and consumer appliances to personal computers and mainframes, have the same basic organization. This organization has three main components: the CPU, the memory subsystem, and the I/O subsystem. The generic organization of these components is shown in Figure 2-1. Address Bus CPU. Data Bus. Memory Subsystem. Control Bus. I/O Device. …. I/O Device. I/O Subsystem. Figure 2-1 Generic computer organization.

(2) 计算机专业英语（第二版）. 12. In this chapter, we first describe the system buses used to connect the components in the computer system. Then we examine the instruction cycle, the sequence of operations that occurs within the computer as it fetches, decodes, and executes an instruction. New Words & Expressions subsystem n. 子系统. operation. microprocessor. system buses 系统总线. sequence decode. n. [计]微处理器. n. 时序，序列. n. [计]操作，运算，执行命令. fetch vt. 取数，取指令. vt. 解码，译解. instruction. n. 指令. Abbreviations CPU(Central Processing Unit) 中央处理器. 2.2. I/O(Input/Output) 输入输出（设备）. System Buses. Physically, a bus is a set of wires. The components of the computer are connected to the buses. To send information from one component to another, the source component outputs data onto the bus. The destination component then inputs this data from the bus. As the complexity of a computer system increases, it becomes more efficient (in terms of minimizing connections) at using buses rather than direct connections between every pair of devices. Buses use less space on a circuit board and require less power than a large number of direct connections. They also require fewer pins on the chip or chips that comprise the CPU. The system shown in Figure 2-1 has three buses. The uppermost bus in this figure is the address bus. When the CPU reads data or instructions from or writes data to memory, it must specify the address of the memory location it wishes to access. It outputs this address to the address bus; memory inputs this address from the address bus and uses it to access the proper memory location. Each I/O devices, such as a keyboard, monitor, or disk drive, has a unique address as well. When accessing an I/O device, the CPU places the address of the device on the address bus. Each device can read the address of the bus and determine whether it is the device being accessed by the CPU. Unlike the other buses, the address bus always receives data from the CPU; the CPU never reads the address bus. Data is transferred via the data bus. When the CPU fetches data from memory, it first outputs the memory address on its address bus. Then memory outputs the data onto the data bus; the CPU can then read the data from the data bus. When writing data to memory, the CPU first outputs the address onto the address bus, then outputs the data onto the data bus. Memory then reads and stores the data at the proper location. The processes for reading data from and writing data to the I/O devices are similar. The control bus is different from the other two buses. The address bus consists of n lines, which combine to transmit one n-bit address value. Similarly, the lines of the data bus work together to.

(3) Chapter 2 Basic Organization of Computers. 13. transmit a single multibit value. In contrast, the control bus is a collection of individual control signals. These signals indicate whether data is to be read into or written out of the CPU, whether the CPU is accessing memory or an I/O device, and whether the I/O device or memory is ready to transfer data. Although this bus is shown as bidirectional in Figure 2-1, it is really a collection of (mostly) unidirectional signals. Most of these signals are output from the CPU to the memory and I/O subsystems, although a few are output by these subsystems to the CPU. We examine these signals in more detail when we look at the instruction cycle and the subsystem interface. A system may have a hierarchy of buses. For example, it may use its address, data, and control buses to access memory, and an I/O controller. The I/O controller, in turn, may access all I/O devices using a second bus, often called an I/O bus or a local bus. New Words & Expressions pins n. 插脚，管脚. address bus 地址总线. uppermost adj. 最高的；adv. 在最上. control bus 控制总线. data bus 数据总线. via. multibit 多位. bidirectional 双向的. unidirectional 单向的. hierarchy n. 层次，层级. I/O bus 输入/输出总线. local bus. 2.3. prep. 经，通过，经由. n. 局域总线. Instruction Cycle. The instruction cycle is the procedure a microprocessor goes through to process an instruction. First the microprocessor fetches, or reads, the instruction from memory. Then it decodes the instruction, determining which instruction it has fetched. Finally, it performs the operations necessary to execute the instruction. (Some people also include an additional element in the instruction cycle to store results. Here, we include that operation as part of the execute function.) Each of these functions—fetch, decode, and execute—consists of a sequence of one or more operations. Let’s start where the computer starts, with the microprocessor fetching the instruction from memory. First, the microprocessor places the address of the instruction on to the address bus. The memory subsystem inputs this address and decodes it to access the desired memory location. (We look at how this decoding occurs when we examine the memory subsystem in more detail later in this chapter.) After the microprocessor allows sufficient time for memory to decode the address and access the requested memory location, the microprocessor asserts a READ control signal. The READ signal is a signal on the control bus which the microprocessor asserts when it is ready to read data from memory or an I/O device. (Some processors have a different name for this signal, but all microprocessors have a signal to perform this function.) Depending on the microprocessor, the READ signal may be active high (asserted - 1) or active low (asserted - 0)..

(4) 14. 计算机专业英语（第二版）. When the READ signal is asserted, the memory subsystem places the instruction code to be fetched onto the computer system’s data bus, The microprocessor then inputs this data from the bus and stores it in one of its internal registers. At this point, the microprocessor has fetched the instruction. Next, the microprocessor decodes the instruction. Each instruction may require a different sequence of operations to execute the instruction. When the microprocessor decodes the instruction, it determines which instruction it is in order to select the correct sequence of operations to perform. This is done entirely within the microprocessor; it does not use the system buses. Finally, the microprocessor executes the instruction. The sequence of operations to execute the instruction varies from instruction to instruction. The execute routine may read data from memory, write data to memory, read data from or write data to an I/O device, perform only operations within the CPU, or perform some combination of these operations. We now look at how the computer performs these operations from a system perspective. To read data from memory, the microprocessor performs the same sequence of operations it uses to fetch an instruction from memory. After all, fetching an instruction is simply reading it from memory. Figure 2-2(a) shows the timing of the operations to read data from memory. In Figure 2-2, notice the top symbol, CLK. This is the computer system clock; the microprocessor uses the system clock to synchronize its operations. The microprocessor places the address onto the bus at the beginning of a clock cycle, a 0/1 sequence of the system clock. One clock cycle later, to allow time for memory to decode the address and access its data, the microprocessor asserts the READ Signal. This causes memory to place its data onto the system data bus. During this clock cycle, the microprocessor reads the data off the system bus and stores it in one of its registers. At the end of the clock cycle it removes the address from the address bus and deasserts the READ signal. Memory then removes the data from the data bus, completing the memory read operation. The timing of the memory write operation is shown in Figure 2-2(b). The processor places the address and data onto the system buses during the first clock cycle. The microprocessor then asserts a WRITE control signal (or its equivalent) at the start of the second clock cycle. Just as the READ signal causes memory to read data, the WRITE signal triggers memory to store data. Some time during this cycle, memory writes the data on the data bus to the memory location whose address is on the address bus. At the end of this cycle, the processor completes the memory write operation by removing the address and data from the system buses and deasserting the WRITE signal. The I/O read and write operations are similar to the memory read and write operations. A processor may use either memory mapped I/O or isolated I/O. If the processor supports memory mapped I/O, it follows the same sequences of operations to input or output data as to read data from or write data to memory, the sequences shown in Figure 2-2. (Remember, in memory mapped I/O, the processor treats an I/O port as a memory location, so it is reasonable to treat an I/O data access the same as a memory access.) Processors that use isolated I/O follow the same process but have a second control signal to distinguish between I/O and memory accesses. (CPUs that use isolated I/O can have a memory location and an I/O port with the same address, which makes this extra signal.

(5) Chapter 2 Basic Organization of Computers. 15. necessary.). Clock Cycle 1. Clock Cycle 1. Clock Cycle 2. CLK. Clock Cycle 2. CLK. Address Bus. Address Data. Data Bus READ. Address Bus. Address. Data Bus. Data. WRITE. (a). (b). Figure 2-2 Timing diagram for (a) memory read and (b) memory write. Finally, consider instructions that are executed entirely within the microprocessor. The INAC instruction of the Relatively Simple CPU, and the MOV r1, r2 instruction of the 8085 microprocessor, can be executed without accessing memory or I/O devices. As with instruction decoding, the execution of these instructions does not make use of the system buses. New Words & Expressions instruction cycle register. 指令周期. memory map n. [计]内存. n. 寄存器. port. timing n. 定时；时序；时间选择 assert trigger. vt. 主张，发出. n. 端口. synchronize. vt. 使……同步. deassert vt. 撤销. vt. 引发，引起，触发. map v. 映射. 2.4. CPU Organization. The CPU controls the computer. It fetches instructions from memory, supplying the address and control signals needed by memory to access its data. The CPU decodes the instruction and controls the execution procedure. It performs some operations internally, and supplies the address, data, and control signals needed by memory and I/O devices to execute the instruction. Nothing happens in the computer unless the CPU causes it to happen. Internally, the CPU has three sections, as shown in Figure 2-3. The register sections, as its name implies, includes a set of registers and a bus or other communication mechanism. The registers in a processor’s instruction set architecture are found in this section of the CPU. The system address and data buses interact with this section of the CPU. The register section also contains other registers that are not directly accessible by the programmer. The relatively simple CPU includes registers to latch the address being accessed in memory and a temporary storage register, as well as other registers that.

(6) 计算机专业英语（第二版）. 16. are not a part of its instruction set architecture. Control bus signals. Address bus. Data bus. Control signals Control Unit Data values Control signals. Register. Data values(Operands) ALU Data values (Results). Figure 2-3 CPU Internal Organization. During the fetch portion of the instruction cycle, the processor first outputs the address of the instruction onto the address bus. The processor has a register called the program counter; the CPU keeps the address of the next instruction to be fetched in this register. Before the CPU outputs the address onto the system’s address bus, it retrieves the address from the program counter register. At the end of the instruction fetch, the CPU reads the instruction code from the system data bus. It stores this value in an internal register, usually called the instruction register or something similar. The arithmetic logic unit or ALU performs most arithmetic and logical operations, such as adding or ANDing values. It receives its operands from the register section of the CPU and stores its results back in the register section. Since the ALU must complete its operations within a single clock cycle, it is constructed using only combinatorial logic. The ADD instructions in the relatively simple CPU and the 8085 microprocessor use the ALU during their executions. Just as the CPU controls the computer (in addition to its other functions), the control unit controls the CPU. This unit generates the internal control signals that cause registers to load data, increment or clear their contents, and output their contents, as well as cause the ALU to perform the correct function. These signals are shown as control signals in Figure 2-3. The control unit receives some data values from the register unit, which it uses to generate the control signals. This data includes the instruction code and the values of some flag registers. The control unit also generates the signals for the system control bus, such as the READ, WRITE, and IO / M signals. A microprocessor typically performs a sequence of operations to fetch, decode, and execute an instruction. By asserting these internal and external control signals in the proper sequence, the control unit causes the CPU and the rest of the computer to perform the operations needed to correctly process instructions. This description of the CPU is incomplete. Current processors have more complex features that improve their performance. One such mechanism, the instruction pipeline, allows the CPU to fetch one instruction while simultaneously executing another instruction..

(7) Chapter 2 Basic Organization of Computers. 17. New Words & Expressions latch v. 闭锁，锁存. program counter 程序计数器. instruction register 指令寄存器. operand. increment. n. 增量，加一. pipeline n. 流水线. n. 操作数. flag register 标志寄存器 microsequenced 微层序的. Abbreviations ALU (Arithmetic Logic Unit) 算术逻辑单元. Reading Material: On 64-Bit Processing http://www.baselinemag.com/article2/0,1397,1261882,00.asp This isn’t new. No, it’s not. Digital Equipment Corp. came out with the first 64-bit processor, the Alpha, in 1992, and Hewlett-Packard, IBM and Sun Microsystems soon followed. What’s new is the idea that “industry standard” computers, not just Unix boxes, may process information in 64-bit chunks, as well. What changed? In 2001, Intel released its Itanium 64-bit processor, prompting Microsoft to get serious about producing a 64-bit version of Windows. Other significant new 64-bit processors include AMD’s Opteron and IBM’s Power4. How does it compare with 32-bit? By definition, a 64-bit processor can process twice as many bits (1s and 0s) of data as a 32-bit chip can in the same number of compute cycles. Because it’s the number of combinations of bits that really matters, this translates to much more than twice the processing power. Thirty-two bits factors out to 4,294,967,296 possible combinations, or 4GB of data, that can be addressed. Sixty-four, on the other hand, raises the roof to 18,446,744,073,709,551,616. That’s 16 exabytes—two orders of magnitude beyond a terabyte. Why would my company need it? As businesses grow more dependent on complex data analysis for standard operations, fast processors become increasingly necessary. Take a supply-chain-optimization application. Such a program might require sorting through all combinations of inventory item and location. When thousands of items and locations are involved, memory requirements can make data impossibly slow to analyze. And while 64-bit is overkill for most desktop users, it may be necessary for graphic artists and animators—something Apple probably had in mind with the G5 processor, a Power4 variant. What are the issues? Having a 64-bit chip doesn’t automatically make a computer faster. The theoretical limit may be enormous, but the ability of subsystems such as the bus to move data into and out of memory can produce a practical limit. For example, Apple says the 64-bit G5 should eventually support 4 TB of data, but can only handle 8 GB today. The faster chip also requires that the operating system and applications that run on top of it be recompiled for 64-bit processing. The Itanium does allow 32-bit applications to run unchanged, but.

(8) 计算机专业英语（第二版）. 18. with a hit on performance. In fact, 32-bit applications may actually run slower on Itanium than they would on a 32-bit Intel Xeon. AMD took a more evolutionary approach with its Opteron processor which extends a 32-bit design to handle 64-bit operations. This means that unmodified 32-bit applications don’t suffer the same performance penalty as the Itanium. How much 64-bit software is available? Unix operating systems like Sun Solaris, HP-UX and IBM AIX have been running on 64-bit processors for years, so Unix software vendors supply these products as a matter of course. Windows Server 2003 is the first Microsoft operating system to fully support 64-bit computing (on Itanium).Linux implementations for Itanium also are beginning to appear. Commercial software applications are following slowly. For example, i2 Technologies’ Supply Chain Planner for 64-bit Windows on Itanium 2 is currently supported for pilot projects only. How does Itanium compare with the Xeon? The 32-bit Xeon will almost certainly remain the default Windows server processor for years to come because of its support for existing applications and the fact that many applications don’t really need 64-bit power. However, Itanium allows Windows to break into territory that used to be exclusive to Unix servers, such as large-scale graphics or simulation applications that require each processor to work with more than 4 GB of memory at a time. Most Xeon-based servers are limited to eight processors; Itanium can support up to 32.. 计算机英语专业词汇的构成英语的词汇构成有很多种，英语真正的基本词汇是不多的，很大部分词汇属于构成型词汇。这里，仅介绍在专业英语中遇到的专业词汇及其构成。目前，各行各业都有一些自己领域的专业词汇，有的是随着本专业发展应运而生的，有的是借用公共英语中的词汇，有的是借用外来语言词汇，有的则是人为构造成的词汇。一、派生词（derivation）这类词汇非常多，它是根据已有的词加上某种前后缀，或以词根生成、或以构词成分形成新的词。科技英语词汇中有很大一部分来源于拉丁语、希腊语等外来语，有的是直接借用，有的是在它们之上不断创造出新的词汇。这些词汇的构词成分（前缀、后缀、词根等）较固定，构成新词以后便于读者揣度词义，易于记忆。 1．前缀采用前缀构成的单词在计算机专业英语中占了很大比例，通过下面的实例可以了解这些常用的前缀构成的单词。 multi- 多 hyper- 超级 super- 超级 multiprogram 多道程序 hypercube 超立方 superhighway 超级公路 multimedia 多媒体 hypercard 超级卡片 superpipline 超流水线 multiprocessor 多处理器 hypermedia 超媒体 superscalar 超标量 multiplex 多路复用 hypertext 超文本 superset 超集.

(9) Chapter 2 Basic Organization of Computers. 19. multiprotocol 多协议 hyperswitch 超级交换机 superclass 超类 inter- 相互、在……间 micro- 微型 tele- 远程的 interface 接口、界面 microprocessor 微处理器 telephone 电话 interlace 隔行扫描 microkernel 微内核 teletext 图文电视 interlock 联锁 microcode 微代码 telemarketing 电话购物 internet 互联网络（因特网） microkid 微机迷 telecommuting 家庭办公 interconnection 互联 microchannel 微通道 teleconference 远程会议单词前缀还有很多，其构成可以同义而不同源（如拉丁、希腊），可以互换，例如： multi, poly 相当于 many 如：multimedia 多媒体，polytechnic 各种工艺的 uni, mono 相当于 single 如：unicode 统一的字符编码标准，monochrome 单色 bi, di 相当于 twice 如：bichloride 双角的，dichloride 二氯化物 equi,iso 相当于 equal 如：equality 等同性，isoline 等值线 simili, homo 相当于 same 如：similarity 类似，homogeneous 同类的 semi,hemi 相当于 half 如：semiconductor 半导体，hemicycle 半圆形 hyper, super 相当于 over 如：hypertext 超文本，superscalar 超标量体系结构 2．后缀后缀是在单词后部加上构词结构，形成新的单词。如： -scope 探测仪器 -meter 计量仪器 -graph 记录仪器 baroscope 验压器 barometer 气压表 barograph 气压记录仪 telescope 望远镜 telemeter 测距仪 telegraph 电报 spectroscope 分光镜 spectrometer 分光仪 spectrograph 分光摄像仪 -able 可能的 -ware 件（部件） -ity 性质 enable 允许、使能 hardware 硬件 reliability 可靠性 disable 禁止、不能 software 软件 availability 可用性 programmable 可编程的 firmware 固件 accountability 可核查性 portable 便携的 groupware 组件 integrity 完整性 scalable 可缩放的 freeware 赠件 confidentiality 保密性二、复合词（compounding）复合词是科技英语中另一大类词汇，其组成面广，通常分为复合名词、复合形容词、复合动词等。复合词通常以小横杠“-”连接单词构成，或者采用短语构成。有的复合词进一步发展，去掉了小横杠，并经过缩略成为另一类词类，即混成词。复合词的实例有： -based 基于，以……为基础 -centric 以……为中心的 rate-based 基于速率的 client-centric 以客户为中心的 credit-based 基于信誉的 user-centric 以用户为中心的 file-based 基于文件的 host-centered 以主机为中心的 Windows-based 以 Windows 为基础的 -oriented 面向……的 -free 自由的，无关的 object-oriented 面向对象的 lead-free 无线的.

(10) 计算机专业英语（第二版）. 20. market-oriented 市场导向 jumper-free 无跳线的 process-oriented 面向进程的 paper-free 无纸的 thread-oriented 面向线程的 charge-free 免费的 info- 信息，与信息有关的 info-channel 信息通道 info-tree 信息、树 info-world 信息世界 info-sec 信息安全其他 point-to-point 点到点 point-and-click 点击 plug-and-play 即插即用 drag-and-drop 拖放 easy-to-use 易用的 line-by-line 逐行 off-the-shelf 现成的 store-and-forward 存储转发 peer-to-peer 对等的 operator-controllable 操作员可控制的 leading-edge 领先的 over-hyped 过度宣扬的 end-user 最终用户 front-user 前端用户 sign-on 登录 sign-of 取消 pull-down 下拉 pull-up 上拉 pop-up 弹出此外，以名词 + 动词-ing 构成的复合形容词形成了一种典型的替换关系，即可以根据需要在结构中代入同一词类而构成新词，它们多为动宾关系。如: man-carrying aircraft 载人飞船 earth-moving machine 推土机 time-consuming operation 耗时操作 ocean-going freighter 远洋货舱然而，必须注意，复合词并非可以随意构造，否则会形成一种非正常的英语句子结构。虽然上述例子给出了多个连接单词组成的复合词，但不提倡这种冗长的复合方式。对于多个单词的非连线形式，要注意其顺序和主要针对对象。此外还应当注意，有时加连字符的复合词与不加连字符的词汇词意是不同的，必须通过文章的上下文推断。如： force-feed 强迫接受（vt.），而 force feed 则为“加压润滑”。随着词汇的专用化，复合词中间的连接符被省略掉，形成了一个单词，例如： videotape 录像带 fanin 扇入 fanout 扇出 online 在线 onboard 在板 login 登录 logout 撤销 pushup 拉高 popup 弹出三、混成词（blending）混成词不论在公共英语还是科技英语中也大量出现，也有人将它们称为缩合词（与缩略词区别）、融会词，它们多是名词，也有地方将其作为动词用，对这类词汇可以通过其构词规律和词素进行理解。这类词汇将两个单词的前部拼接、前后拼接或者将一个单词前部与另一词拼接构成新的词汇，实例有： brunch (breakfast + lunch) 早中饭 smog (smoke +fog) 烟雾 codec (coder+decoder) 编码译码器 compuser (computer+user) 计算机用户 transeiver (transmitter+receiver) 收发机 syscall (system+call) 系统调用.

(11) Chapter 2 Basic Organization of Computers. 21. mechatronics (mechanical+electronic) 机械电子学 calputer (calculator+computer) 计算器式电脑四、缩略词（shortening）缩略词是将较长的英语单词取其首部或者主干构成与原词同义的短单词，或者将组成词汇短语的各个单词的首字母拼接为一个大写字母的字符串。随着科技发展，缩略词在文章索引、前序、摘要、文摘、电报、说明书、商标等科技文章中频繁采用。对计算机专业来说，在程序语句、程序注释、软件文档、文件描述中也采用了大量的缩略词作为标识符、名称等。缩略词的出现方便了印刷、书写、速记、以及口语交流等，但也同时增加了阅读和理解的困难。缩略词开始出现时，通常采用破折号、引号或者括号将它们的原形单词和组合词一并列出，久而久之，人们对缩略词逐渐接受和认可，作为注释性的后者也就消失了。在通常情况下，缩略词多取自各个组合字（虚词除外）的首部第一、二字母。缩略词也可能有形同而义异的情况。如果遇到这种情况，翻译时应当根据上下文确定词意，并在括号内给出其原形组合词汇。缩略词可以分为如下几种。 1．压缩和省略将某些太长、难拼、难记、使用频繁的单词压缩成一个短小的单词，或取其头部、或取其关键音节。如： flu=influenza 流感 lab=laboratory 实验室 math=mathematics 数学 iff=if only if 当且仅当 rhino=rhinoceros 犀牛 ad=advertisement 广告 2．缩写（acronym）将某些词组和单词集合中每个实意单词的第一或者首部几个字母重新组合，组成为一个新的词汇，作为专用词汇使用。在应用中它形成三种类型，即：（1）通常以小写字母出现，并作为常规单词 radar (radio detecting and ranging) 雷达 laser (light amplification by stimulated emission of radiation) 激光 sonar (sound navigation and ranging ) 声纳 spool (simultaneous peripheral operation on line) 假脱机（2）以大写字母出现，具有主体发音音节 BASIC (Beginner’s All-purpose Symbolic Instruction Code) 初学者通用符号指令代码 FORTRAN (Formula Translation) 公式翻译 COBOL (Common Business Oriented Language) 面向商务的通用语言（3）以大写字母出现，没有读音音节，仅为字母头缩写 ADE (Application Development Environment) 应用开发环境 PCB (Process Control Block) 进程控制块 CGA (Color Graphics Adapter) 彩色图形适配器 DBMS (Data Base Management System) 数据库管理系统 FDD (Floppy Disk Device) 软盘驱动器 MBps (Mega Byte Per Second) 每秒兆字节 Mbps(Mega Bits Per Second) 每秒兆字位.

(12) 计算机专业英语（第二版）. 22. RISC (Reduced Instruction Set Computer) 精简指令集计算机 CISC (Complex Instruction Set Computer) 复杂指令集计算机五、借用词借用词一般来自厂商名、商标名、产品代号名、发明者名、地名等，它通过将普通公共英语词汇演变成专业词意而实现。有的则是将原来已经有的词汇赋予新的含义。例如： woofer 低音喇叭 tweeter 高音喇叭 flag 标志、状态 cache 高速缓存 semaphore 信号量 firewall 防火墙 mailbomb 邮件炸弹 scratch pad 高速缓存 fitfall 专用程序入口在现代科技英语中借用了大量的公共英语词汇、日常生活中的常用词汇，而且，以西方特有的幽默和结构讲述科技内容。这时，读者必须在努力扩大自己专业词汇的同时，也要掌握和丰富自己的生活词汇，并在阅读和翻译时正确采用适当的含义。. Exercises I. Answer the following questions: 1. 2. 3.. Describe the organization of basic computer systems. How does a processor process an instruction? How many sections are there in a CPU, and what are their functions? II. Write a review on the 64-bit processors..

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