External Stresses on Tensile and Compressive
Contact Etching Stop Layer SOI MOSFETs
Wen-Teng Chang, Member, IEEE, Chih-Chung Wang, Jian-An Lin, and Wen-Kuan Yeh, Member, IEEE
Abstract—A n-/p-SOI MOSFET capped with a standard 380 Å
tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were mea-sured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-induced threshold voltage shifts and input-referred voltage noise showed bigger depletion zones and higher noise in the device with compressive CESL. The measurement suggests that both SOI thickness and CESL type are critical for mobility enhancement or degradation of devices. The capped compressive CESL for n-/p-SOI MOSFETs demonstrated higher piezoresis-tive coefficient compared with tensile CESL under external uni-axial compressive stresses for both longitudinal and transverse configurations.
Index Terms—Contact etch stop layer, induced defect,
piezore-sistive, silicon-on-insulator (SOI) technology, strain engineering.
I. INTRODUCTION
S
TRAINED-CHANNEL transistors, which can enhance carrier mobility, are studied intensively in the integrated circuit (IC) industry [1]–[11]. Combined with silicon-on-insulator (SOI) technology, the strained SOI further enhances carrier mobility in order to realize integrated circuits with high speed and low noise for deep submicrometer devices. The strain on a surface can either be uniaxial or biaxial. Biaxial stress can be broken into parallel and perpendicular parts relating to the channel. A variety of strained approaches have been developed through fabrication process, lattice mismatch, or package in order to obtain a strained-channel transistor [1]–[9]. The uniaxial process such as contact etching stop layer (CESL) is a particularly key technology that further improves mobility performance because uniaxial stress can significantly change hole and electron mobility resulting from its effective mass transformation compared with biaxial stress. A previous report demonstrated that uniaxial tension via CESL can either enhance or degrade nMOSFET and pMOSFET [5]–[8]. CESL com-monly uses a layer of capped silicon nitride (SiN), which can be adjusted to a tensile or compressive stress deposited by plasma-enhanced chemical vapor deposition on the channel for bothManuscript received October 9, 2009; revised April 9, 2010; accepted May 18, 2010. Date of publication June 28, 2010; date of current version July 23, 2010. This work was supported by National Science Council under Grant 98-2221-E-390-025-MY2. The review of this paper was arranged by Editor J. Woo.
The authors are with the Department of Electrical Engineering, National Uni-versity of Kaohsiung, Kaohsiung 811, Taiwan (e-mail: wtchang@nuk.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2051362
Fig. 1. (a) TEM of a 900 Å SOI MOSFET. The stressed contact etch stop layer (CESL) is denoted as tensile layer (T.L.) and compressive layer (C.L.). (b) The wafers were cut into longitudinal and transverse configurations to110 channel.
n-/p- MOSFETs via gates [10]. However, the strained-channel technique for enhancing the performance of MOSFETs also results in interface traps. Charge accumulations are attributed to many parameters, including doping density, SOI thickness, flatband voltage, capacitance between front gate, back gate oxide, and depletion. These accumulations were measured by gate voltage shifts or noise level [11], [12]. However, the impact of both CESL type and SOI thickness have yet to be addressed in tandem. This paper first characterizes extensively the re-sults affected by the induced defect via tensile and compres-sive CESL on MOSFETs and for those with SOI thicknesses of 500/700/900 Å. Additionally, external compressive forces were exerted on n-/p- SOI MOSFETs longitudinally and trans-versely in order to quantify mobility enhancement or degra-dation by measuring the shift level of their drain currents and transconductances.
II. EXPERIMENTS
The SOI wafers in this work were obtained by smart-cut technology using 200-nm-thick buried oxide (BOX). The 1.6 nm nitride gate oxide was grown. Arsenic/boron ion im-plantations were used for source/drain junctions. The 120-nm-thick poly-Si gate was followed by spike anneal. A 50-nm-120-nm-thick Ni was deposited due to lower thermal budget. Fig. 1(a) shows the TEM cross-section of the 900 Å SOI MOSFET. The chan-nels of the n-/p-MOSFETs in this work have width/length = 10 μm/90 nm. For the 90-nm technology with tensile CESL (T.L.) stress, one set of the samples were capped by silicon nitride with a standard thickness of 380 Å. The other sam-ple sets of MOSFETs were capped with 700 Å compressive CESL (C.L.) stresses. The Nichol fully silicided (FUSI) metal gate approach was used because its work function is ad-justable through implantation doping, and the process is highly compatible with the CMOS process [13], [14]. Additionally,
different thicknesses of SOI (tSOI) were measured throughout this work, combining SOI thicknesses of 500/700/900 Å for the devices capped with tensile and compressive CESL.
The contact pads of the gate, source, drain, and body were connected by manipulating probes. They were measured by HP4156 semiconductor parameters. To understand the interface trap caused by the electron injection degradation, which re-sulted in threshold voltage shift and transconductance degrada-tion, the experiment set gate voltage was placed approximately equal to the drain voltage in order to extract hot carrier degrada-tion to its maximum level [15], [16]. BTA 9812 noise analyzers were used to inspect the low-frequency noise spectrum. Since the generation-recombination noise was mostly caused by dop-ing or defects and by the major low-frequency noise, flicker noise was one of the methods used to quantify the interface traps [17]–[20].
To measure the piezoresistive change of the devices with tensile and compressive CESL under external uniaxial stresses, both n- and p-channel 110 SOI MOSFETs on (100)-orientated substrates were cut at a size of about 1 cm by 4 cm, in parallel (longitudinal; 0◦) and in perpendicular (transverse; 90◦), according to channel directions [Fig. 1(b)]. The external stress measurement setup was comprised of a customized ap-paratus that could clamp a cut silicon bar on one side. Loading force was then applied on the other free end (i.e., a cantilever design for measurement). The lift distance was counted by the turns of a delicate screw via a hole underneath. With the constant distance from the measured device to the clamping end, the stress at the device was calculated by Young’s modulus of a single crystal silicon (150 GPa) multiplied by the strain of the silicon bar. The strain was estimated as
strain =l2+ (Δd)2− l l (1) where l is the distance from the clamping end to the location of the screw fixed at 24 mm, while Δd is the distance of the screw lift. The interval between the screw threads is 0.79 mm.
III. RESULTS ANDDISCUSSION A. Characterization of Capped Tensile and Compressive CESL
This work measured the variation of depletion zone depth. Using the temperature coefficient of the threshold voltage (Vth), this ratio was expressed as [21]
dVth dT = dφF dT 1 + q COX εSiNd kT ln(Nd/ni) (2)
where kT is the thermal energy, q is the elementary charge, Nd
is the doping concentration, ni is the silicon intrinsic
concen-tration, and Coxis the gate oxide capacitance. Since the ratio of work function (φF) on temperature is negatively related with
temperature, the increasing temperature results in a decreas-ing depletion region. The thinner SOI has lower temperature coefficients (dVth/dT ) in (2), compared with those having thicker SOI [22], [23]. In the measurement using pMOSFET
Fig. 2. Threshold voltage shifts versus temperature. Temperature coefficients for PMOS tensile and compressive CESL are−0.91 and −0.70 mV/K, respec-tively, from room temperature to 200◦C.
Fig. 3. Transconductance (Gm) shift versus temperature from tensile and compressive CESL of pMOSFET with SOI 900 Å. Compressive CESL en-hances while tensile CESL degrades Gm. The degradation ratios are 37.54% and 33.75% for PMOSFET with compressive and tensile CESL, respectively.
with tensile and compressive CESL (Fig. 2), the temperature coefficients were−0.91 and −0.70 mV/K, respectively, which implies that the device with compressive CESL has lower effective depletion width.
In Fig. 3, pMOSFET transconductance with tensile and com-pressive CESL demonstrates that the device with comcom-pressive CESL has an intrinsically high transconductance compared with that of tensile CESL. From the definition of transconduc-tance in Gm= ∂iD ∂vGS VDS = μCOX W L(VGS− Vth)(1 + λVDS) (3)
where μ is the carrier mobility; W and L are the gate width and length, respectively; VGS, VDS, and Vthare gate-to-source voltage, drain-to-source voltage, and threshold voltage, re-spectively; and λ is the channel-length modulation parameter. Transconductance is only mobility-dependent under fixed tem-perature. However, under rising temperatures, phonon scatter-ing degrades their mobility, resultscatter-ing in roughly the inverse of the temperature by a degree from 1 to 1.3 (Fig. 3) for rising temperatures from room temperature to 200 ◦C and a degree of 1.5 for ultra thin SOI (T−1.5) [24]. The input-referred
Fig. 4. Larger input-referred voltage noise on compressive CESL capped pMOSFET than that on tensile CESL.
TABLE I
PIEZORESISTIVECOEFFICIENTS OF110BULKSILICON FOR n-/p-MOSFETs WITH THECHANNEL OFLONGITUDINAL AND
TRANSVERSECONFIGURATIONS[30]
Fig. 5. IDmeasurement for the pMOSFETs capped with tensile CESL (T.L.) and compressive CESL (C.L.) and those with SOI thicknessess of 500 Å, 700 Å, 900 Å, respectively.
voltage noise (SVG) was measured from 10 Hz to 100 kHz. The noise was mainly determined by the interface defect of oxide [25], [26]. Under this context, the interface state of the device with capped C.L. obviously demonstrated more induced defects compared with the device capped with T.L. (Fig. 4).
B. Impact of SOI Thickness of MOSFETs
SOI thickness has been reported to correlate with induced interface defect. This phenomenon has been estimated by transconductance, threshold voltage shift, or noise level [26]– [29]. However, the interaction for capped T.L. and C.L. stresses are seldom discussed, although they were known to enhance or degrade MOSFETs using capped T.L. and C.L. stresses (Table I) [30], [31]. Fig. 5 shows the saturation current of the devices with SOI thicknesses of 500/700/900 Å capped with
T.L. and C.L. SOI thickness of 900 Å-capped C.L. has the highest ID, which was only correlated to its carrier mobility
because the mobility was limited by phonon scattering in the thinner SOI thickness [32]. However, this measurement demon-strates that the impact of SOI thickness and capped CESL were both important in determining the mobility. It has been known that uniaxial compressive stress can enhance pMOSFET
110 silicon while tensile stress degrades pMOSFET [1],
[33], [34]; however, the thick SOI in this work has played an equally important role relative to the capped films. For example, pMOSFET with SOI thickness of 900 Å with capped T.L. was significantly higher than that which was capped with 500 and 700 Å C.L. By Matthiessen’s rule, mobility was determined by lattice vibration and impurities, implying that the induced defect from SOI is as important as the well-capped layer, which mainly resulted from the interface state of oxide.
C. External Compressive Stresses on the MOSFETs Capped With Tensile and Compressive CESL
This measurement manipulated testing probes on the devices sitting on the upper side suffering from compressive stresses, whereas external force was applied underneath the cut silicon bar. Fig. 6(a) and (b) show the Gm plot under external
lon-gitudinal stresses on nMOSFET and pMOSFET, respectively, with SOI 900 Å at VG= 1.2 V. Each plot contained the samples
with capped T.L. and C.L. Fig. 6(c) and (d) show the Gmplot
under the same conditions but with different transverse stresses. The applied stresses were on the clamped end while the loading forces were on the free end. The devices on the clamped end were estimated to be approximately 5.1, 20.3, and 45.7 MPa for the interval of the screw lift of 1/4, 2/4, and 3/4 turns by (1), respectively. Fig. 7(a) and (b) show the measured normalized saturation current changes of the nMOSFETs and pMOSFETs capped with T.L. and C.L., respectively, with SOI thickness of 900 Å under longitudinal and transverse configurations with external stresses from 0 to 45.7 MPa. These measurements extracted the saturation current (IDsat) value when VD was
at 1.2 V.
The results in Figs. 6(a)–(d) and 7(a) and (b) indicate that the normalized saturation carrier mobility decreased for both longitudinal and transverse configurations of all measured de-vices, except for the pMOSFET longitudinal configuration. For the 110 silicon channel direction, the normalized saturation current or transconductance change was calculated as stress multiplied by their piezoresistive coefficients in longitudinal configuration (0◦) and transverse configuration (90◦):
ΔID ID 0◦ = ΔGm Gm 0◦ = Δμ μ 0◦ = π11+ π12+ π44 2 Δσ (4) ΔID ID 90◦ = ΔGm Gm 90◦ = Δμ μ 90◦ = π11+ π12− π44 2 Δσ (5)
where π11, π12, and π44 are three independent piezoresis-tive coefficients and Δσ is the normal stress change when shear stress is ignored. The reported coefficients, longitudinal coefficients (π11+ π12+ π44)/2, and transverse coefficients
Fig. 6. Transconductance (Gm) shift of n-/p-MOSFET capped with T.L. and C.L. with SOI 900 Å under external stresses from 0 to 45.7 MPa. The applied stresses are longitudinal (a) and (b) and transverse (c) and (d) related to channel direction. The insets enlarge the local Gmaround the peaks.
(π11+ π12− π44)/2 for bulk n- and p-type silicon, as well as the different sizes of SOI MOSFETs, were reported [30]. The ratios for ((ΔID/ID)/Δσ) in (4) and (5) are in fact the
piezoresistive coefficients of the measured devices, as well as the slopes in Fig. 7(a) and (b). The figures show that the
Fig. 7. Normalized drain current measurement for (a) tensile and compressive CESL nMOSFET and (b) pMOSFET under external compressive stresses. Compressive CESL capped MOSFETs have higher piezoresistive coefficients than those of tensile CESL.
capped C.L. on both n- and p-MOSFET has significantly higher piezoresistive coefficients than those with T.L. stress. In other words, additional compressive stress (i.e., external stress in this case) on those devices capped with C.L. and T.L. can show different levels of mobility change.
IV. CONCLUSION
This paper measured n-/p-SOI MOSFETs capped with 380 Å tensile CESL and 700 Å compressive CESL. The higher strained MOSFETs (i.e., compressive CESL) clearly showed higher input-referred voltage noise but with a full depletion zone. Both SOI thickness (500/700/900 Å) and CESL type are important in determining the enhancement and/or degradation of the mobility of devices. The capped T.L. and C.L. for n-/p-SOI MOSFETs demonstrated that compressive CESL has higher piezoresistive coefficient compared with tensile CESL under external uniaxial compressive stresses of up to 45.7 MPa for both longitudinal and transverse configurations. The mea-surements were verified by normalized saturation current change and transconductance measurement. The results suggest that thinner SOI MOSFETs, capped tensile CESL, and external stress such as CESL may have higher-induced interface trap, al-though the strained-channel has also been proven as an effective approach for enhancing carrier mobility in this work.
ACKNOWLEDGMENT
The authors would like to thank the staff at United Micro-electronics Corporation for their informative discussions.
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Wen-Teng Chang (M’07) was born in Kaohsiung,
Taiwan, in 1971. He received the B.S.degree in elec-trical engineering from the National Tsing Hua Uni-versity, Hsinchu, Taiwan, in 1994 and the M.S. and Ph.D. degrees from Case Western Reserve Univer-sity, Cleveland, OH, in 2004 and 2006, respectively. He joined Applied Materials, Taiwan and Chi Mei Optoelectronics, in 1997 and 1999, respectively, where he worked in thin film technology develop-ment. Since 2006, he has been an Assistant Pro-fessor in the Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung, Taiwan. His research interests include microsystems, electronic materials, and SOI MOSFETs.
Chih-Chung Wang received the M.S. degree in
electrical engineering from the National University of Kaohsiung, Kaohsiung, Taiwan, in 2009.
Since 2007, he has been investigating the impact of SOI thickness on device characteristic and reli-ability for FUSI gate CMOSFET with CESL strain technology.
Jian-An Lin was born in 1984. He received the
M.S. degree in electrical engineering from the Na-tional University of Kaohsiung, Kaohsiung, Taiwan, in 2009.
Since 2007, he has been investigating the influence of piezoresistive field-effect transistors and MEMS resonators used for filter and oscillator.
Wen-Kuan Yeh (M’00) was born in Hsin-Chu,
Taiwan, in 1964. He received the B.S. degree in electronic engineering from Chung-Yuan Christian University, Chung-Li, Taiwan, in 1988, the M.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1990, and the Ph.D. degree in electronics engineering from the National Chiao-Tung University, Hsin-Chu, Taiwan, in 1996. From 1996 to 2000, he was a Member of the Research Staff of the
Unite Microelectronic Corporation Technology & Process Development Division. He helped in the research and development of Logic, Embedded DRAM, SOI, and 90-nm transistor tech-applications. He is currently a Full Professor with the Electrical Engineering Department of the National University of Kaohsiung, Kaohsiung, Taiwan. His recent work is in the field of low-power and high-performance MOSFETs.
