RGMII Interface電磁干擾解決方案分析

RGMII Interface

Analysis of Electromagnetic Interference Solutions

for RGMII Interface

RGMII Interface

Analysis of Electromagnetic Interference Solutions

for RGMII Interface

Student Chia-Lung Wang Advisor Dr. Lin-Kun Wu

A Thesis

Submitted to Institute of Communication Engineering College of Electrical and Computer Engineering

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master of Science

in

Communication Engineering December 2013

RGMII Interface

MAC PHY RGMII Interface

EMI clock FFT

125MHz clock 250MHz 375MHz••• EMI

125MHz Clock slew rate EMI

clock trace 10pF slew

rate 125MHz EMI

Analysis of Electromagnetic Interference Solutions for RGMII

Interface

Student Chia-Lung Wang Advisor Dr. Lin-Kun Wu

Degree Program of Electrical and Computer Engineering National Chiao Tung University

Abstract

This thesis investigates the effectiveness of two techniques commonly used to improve EMI performance of networking products RGMII Interface. By measuring clock waveform and obtaining its spectral power characteristics via FFT, the EMI suppressing effectiveness of the two techniques are compared.

Spread-spectrum clocking (SSC) and slew rate control techniques are employed to suppress the EMI associated with the RGMII’s 125MHz clock signal. Experimental results indicate that SSC reduces EMI by spreading power contained in each clock harmonic over a widerbandwidth. On the other hand, reducing the slew rate by shunting the clock trace to the ground via a 10pF capacitor is also effective in suppressing clock signal’s EMI. Although both techniques can be used to suppress EMI, they have to be constrained not to causing any violation in timing specification.

Contents

………i ………ii ………iii ………iv ………v ………vii ... 1 1.1 ... 1 1.2 ... 2 ... 3 2.1 ... 3 2.2 ... 19 2.3 Slew rate ... 23 ... 25 3.1 PCB ... 29 3.2 ... 32 3.3 ... 33 3.4 EMI ……….……….………35 3.5 Clock ………..……….41

3.6 Clock slew rate ………..……….50

1-1 L2/L3 ... 1

2-1 SOCMII PHYORSWITCH MAC ... 6

2-2 SOCRMII PHYORSWITCH MAC ... 9

2-3 SOCSMII PHYORSWITCH MA ... 12

2-4 GMIIMAC PHY ... 14

2-5 RGMIIMAC PHY ... 17

2-6 ... 19 2-7 ... 20 2-8 ... 20 2-9 [13] ... 21 2-10 [13] ... 22 2-11 [13] ... 22

2-12 SLEW RATE CLOCK ... 24

3-1 ... 25 3-2 ... 27 3-3 ... 30 3-4 ... 30 3-5 LAYOUT PLACEMENT ... 31 3-6 LAYOUT PLACEMENT ... 31 3-7 ... 32 3-8 ... 33 3-9 EMI ... 34 3-10 EMI ... 35 3-11 CLOCK 1 OHM ... 36 3-12 CLOCK ... 36 3-13 CLOCK ... 37 3-14 125MHZ ... 38 3-15 250MHZ ... 38 3-16 375MHZ ... 39 3-17 500MHZ ... 39 3-18 625MHZ ... 40 3-19 750MHZ ... 40 3-20 875MHZ ... 41 3-21 DISABLE SSC 125MHZ ... 42 3-22 ENABLE SSC 125MHZ ... 42 3-23 SSCEMI ... 43

3-24 SSCEMI ... 44 3-25 125MHZ ... 46 3-26 250MHZ ... 46 3-27 375MHZ ... 47 3-28 500MHZ ... 47 3-29 625MHZ ... 48 3-30 750MHZ ... 48 3-31 875MHZ ... 49 3-32 OVERSHOOT [7] ... 49 3-33 OVERSHOOT ... 50 3-34 CLOCK 10P GND [1] ... 51 3-35 CLOCK 10P GND PCBA [1] ... 51 3-36 125MHZ CLOCK ... 52 3-37 10P 125MHZ CLOCK ... 52 3-38 125MHZ ... 53 3-39 250MHZ ... 54 3-40 375MHZ ... 54 3-41 500MHZ ... 55 3-42 625MHZ ... 55 3-43 750MHZ ... 56 3-44 875MHZ ... 56 3-45 SLEW RATE 125MHZ ... 57 3-46 SLEW RATE 250MHZ ... 57 3-47 SLEW RATE 375MHZ ... 58 3-48 SLEW RATE 500MHZ ... 58 3-49 SLEW RATE 625MHZ ... 59 3-50 SLEW RATE 750MHZ ... 59 3-51 SLEW RATE 875MHZ ... 60

3-52 SLEW RATE EMI ... 61

2-1 MII ... 6 2-2 RMII ... 9 2-3 SMII ... 12 2-4 GMII ... 14 2-5 RGMII ... 18 3-1 SSC ... 44 3-2 SSC ... 45 3-3 SLEW RATE ... 53 3-4 SSC SLEW RATE ... 62 3-5 SSC SLEW RATE ... 63

1.1

VDSL 3G 4G 1-1 : L2/L3 EMC EMC EMI

PCB stack 4-Layer 2-Layer PCB 2-Layer PCB GND layout EMI HW R&D EMI EMI EMI EMI EMI RGMII

IEEE IEEE 802.3-2000 RGMII 125MHz

1000Mbps MII 10/100Mbps

10M/100M/1000Mbps Clock

2.5MHz/25MHz/125MHz

2.1

(MII) PHY(Physical layer)

MAC layer 1995

IEEE802.3U MII MII

SMI (Serial Management Interface)

PHY PHY

PHY

: 10/100MHz

1. MII Media Independent Interface

2. RMII(Reduced Media Independent Interface) 3. SMII Serial Media Independent Interface Gigabit

4. GMII Gigabit Media Independent Interface

2.1.1 MII

MII( MAC PHY

MII

16 TX_ER TXD TX_EN TX_CLK COL RXD RX_EX RX_CLK CRS RX_DV

MII 4bit 25MHz

100Mbps

PHY SMI Serial Management Interface PHY

PHY IEEE PHY

MAC SMI PHY PHY

SMI PHY

MII SMI PHY

IEEE MAC PHY

PHY MAC 4bit 1bit

PHY CSMA/CD

Auto Negotiation NWAY PHY differential signal

100Mbps RJ-45

PHY AUTO MDI-X RJ-45

2-1 SOC MII PHY or Switch MAC Symbol Type Signal Description TXD0

TXD1 TXD2 TXD3

Output Transmit Data

TX_ER Output Transmit Error TX_CLK Transmit Clock TX_EN Output Transmit Enable RXD0

RXD1 RXD2 RXD3

Input Receive Data

RX_DV Input Receive Data Valid RX_ER Input Receive Error RX_CLK Input Receive Clock COL Input Collision Detected CRS Input Carrier Sense

MDC Input Management Data Input/output MDIO I/O Management Data Clock

2-1 MII : TX_CLK Physical layer TXD TX_EN TX_ER 10 Mbps TX_CLK 2.5MHZ 100Mbps TX_CLK 25MHZ TXD <3:0> 4-bit TX_CLK TX_EN TX_D Physical medium TX_D

TX_EN Nibbles MII Physical medium

TX_EN TX_EN TX_CLK

COL TX_CLK RX_CLK Physical medium COL CRS TX_CLK RX_CLK Physical medium CRS RX_CLK Physical layer RXD RX_DV RX_ER 10 Mbps RX_CLK 2.5MHz 100 Mbps RX_CLK 25MHz RXD <3:0> 4-bit RX_CLK RX_DV

MAC Physical medium

RX_DV Physical medium RX_CLK RX_D

SFD Frame

RX_ER RX_ER RX_CLK RX_CLK RX_DV RX_ER

2.1.2 RMII

RMII Reduced MII MII MAC

PHY RMII REF_CLK

Crystal 50MHz MII MII

MAC

Crystal IC

PLL FIFO

FIFO

MII RMII mac

mac +padding(optional)+32bitCRC

vlan vlan tag 12bit

2-2 SOC RMII PHY or Switch MAC

Symbol Type Signal Description TXD0

Output Transmit Data TXD1

CLK_REF Input Reference Clock TX_EN Input Transmit Enable RXD0

Input Receive Data RXD1

CRS_DV Input Collision and Data Valid RX_ER Input Receive Error

MDC Output Management Clock MDIO I/O Management Data I/O

2-2 RMII

:

TXD[1:0] MII

RXD[1:0] MII

TX_EN(Transmit Enable) MII

RX_ER(Receive Error) MII

CLK_REF Crystal 50MHz MII

MII PHY MAC Crystal PHY FIFO CRS_DV MII RX_DV CRS busy CRS_DV REF_CLK CRS RX_DV CRS_DV 25MHz/2.5MHz MAC CRS_DV RX_DV CRS

100Mbps TX/RX 10Mbps

TX/RX 10 TX/RX 10

10

PHY CRS_DV

FIFO MAC FIFO

“101010---” “01” MAC CRS_DV FIFO CRS_DV FIFO RX_ER

2.1.3 SMII

SMII Serial MII MII TXD RXD SYNC Clock Clock 125MHz 125MHz

TXD RXD

10 SYNC

2-3 SMII RMII (7

MII (14 2-3 SMII PHY

2-3 SOC SMII PHY or Switch MAC Symbol Type Signal Description TXD0 Output Transmit Data CLK_REF Input Reference Clock RXD0 Input Receive Data

SYNC Input Synchronous Signal MDC Output Management Clock MDIO I/O Management Data I/O

2-3 SMII

: TXD[0] RMII RXD[0] RMII SYNC 10 CLK_REF 125MHz 100Mbps 125MHz TXD/RXD 10 SYNC SYNC 10 TXD TXD[7:0]

TX_EN TX_ER MII RXD

RXD[7:0] RX_DV CRS RXD[7:0] RX_DV RX_DV RXD[7:0] RX_DV RXD[7:0] 10Mbps 10 MAC/PHY 10 MAC/PHY

2.1.4 GMII

Gigabit MII GMII RGMII SGMII TBI RTBI

GMII RGMII

GMII TX_ER TX_EN RX_ER RX_DV CRS

COL MII GTX_CLK RX

_CLK 125MHz(1000Mbps/8=125MHz)

GTX_CLK MII TX_CLK M

II TX_CLK PHY MAC GMII GTX_CLK

MAC PHY GMII

MII GMII TX

_CLK GTX_CLK MII TX_C

LK 2-4 GMII MAC PHY

Symbol Type Signal Description

GTX_CLK Output Transmit Clock_125MHz TXD[0:7] Output Transmit Data

TX_ER Output Transmit Coding Error TX_EN Output Transmit Enable

RX_CLK Input Receive Clock_125MHz RXD[0:7] Input Receive Data

RX_ER Input Receive Error RX_DV Input Receive Data Valid COL Input Collision Detected CRS Input Carrier Sense

MDC Output Management Clock MDIO I/O Management Data I/O

2-4 GMII GMII 8bit

125MHz 1000Mbps MII 10/100 Mbps

GMII IEEE IEEE

802.3-2000 2.4 GMII

: TXD[7..0]

RXD[7..0]

RX_ER RX_CLK RX_CLK RX_DV RX_ER RX_CLK GTX_CLK RX_DV Physical medium RX_CLK RX_D SFD Frame RX_ER RX_CLK RX_CLK RX_DV RX_ER

COL TX_CLK RX_CLK Physical medium COL

MDC/MDIC PHY 32

16 16 “IEEE 802.3,2000-22.2.4 Management Functions”

1000Mbps MAC PHY GTX_CLK TXD TXEN TXER 10/100M PHY TXCLK

MII MII 25MHz

2.1.5 RGMII

RGMII Reduced GMII GMII 24

14 125MHz TX/RX 1000Mbps RGMII GMII G MII TXD[3:0]/RXD[3:0] TXD[7:4]/RXD[7:4] 2-5 RGMII MAC PHY 2-5 RGMIIMAC PHY

Symbol Type Signal Description

GTX_CLK Output Transmit Clock_125MHz TXD[0:3] Output Transmit Data

TX_EN Output Transmit Enable

RX_CLK Input Receive Clock_125MHz RXD[0:3] Input Receive Data

RX_DV Input Receive Data Valid COL Input Collision Detected CRS Input Carrier Sense

MDC Output Management Clock MDIO I/O Management Data I/O

2-5 RGMII

RGMII 100Mbps 10Mbps

25MHz 2.5MHz TX_EN TX_EN TX_ER TX_C

LK TX_EN TX_ER RX_DV

RX_DV RX_ER RX_CLK RX_DV

RX_ER GMII GMII

2.2

(Spread Spectrum Clock, SSC)

(Frequency Modulation, FM)

S

ssc (t)

m

f(t) (t)

S

ssc (t) =

A

c cos( c t) (2-1)

m

f (t) = Vf cos( m t) (2-2) fi (t) =( F /Vf ) mf (t)+ fc (2-3)

A

c 2-6 2-7

m

f(t) fi (t)

f

d( t ) =

f

i( t ) -

f

c= F *cos( m t ) = [d /dt]

(2-4)

2-7 2-8 2-8 2-5 Sssc(t) = Ac cos ( ) (2-5) = Ac cos[( c+2 Fcos mt) t]

2-9) 2-10) 2-11) fc fc fc·(1+ fc·(1+ /2)~ fc·(1- /2) fc·(1- fc [13] 2-9

2-10 2-11 IC (Jitter) EMI Multipath interference

(EMI) Clock generator

Clock signal jitter

2.3 Slew rate

Slew rate Clock Clock

2-12 slew rate clock clock low high undershoot overshoot ringing

2-12 clock slew rate

/ undershoot overshoot ringing [2] slew rate clock

2-12 slew rate clock

Clock undershoot overshoot ringing EMI clock

clock

Realtek RTL8696 SOC RTL8211E Giga PHY Gigabit Ethernet Port PCBA ; Ethernet Port 1000Base-T IEEE 802.3ab, 100Base-TX IEEE802.3u, 10Base-T

IEEE 802.3 SOC Giga PHY RGMII

slew rate EMI RTL8696 25MHz Crystal SOC 1000Base-T,100Base-T 10Base-T

PLL 125MHz,25MHz 2.5MHz RGMII Clock 125MHz EMI

3-1 3-2

3-2 )

3.1 PCB

PCB 1.2mm PCB

152X128mm;PCB FR4

4.3 0.7mils Layout Placement SOC (RTL8696) Giga PHY(RTL8211E) PCB Clock trace

GND PCB 2 Layer

Clock GND

EMI Fail 3-3 3-4 3-5 Layout placement 3-6 Layout placement

3-3

3-5 Layout placement

3.2

7m(L)x4m(W)x3m(H) 3-7 3-8 3m ; 1m 1.5m ; 360 ; EN 55022 Class B 30MHz~1GHz Agilent E7405A 3-7

3-8

3.3

Slew rate EMI

FFT slew

rate EMI

slew rate PCBA EMI 3-9 3-10 EMI Fail

3-10 EMI

3.4 EMI

EMI 125MHz EMI Fail 3-11 1 ohm (R52) 125MHz Clock 3-12

3-11 Clock 1 ohm

3-12 clock

3-13 IC CMOS (+Vp-Vp) (-Vp-Vp) FFT 125MHz ( 3-14 ~3-20) EMI 3-13 clock

3-14 125MHz

3-18 625MHz

3-20 875MHz

3.5 Clock

PCBA 125MHz clock 3-21 3-22 SSC SSC 125MHz -29.78 dBm -45.57dBm 125MHz 122~125MHz

3-21 Disable SSC 125MHz

3-23 3-24 SSC EMI ( SSC

disabled) 3-1 3-2

3-24 SSC EMI Horizontal(dB) Condition 125MHz 250MHz 375MHz 500MHz 625MHz 750MHz 875MHz Original -10.35 -5.44 1.18 -2.21 -0.56 -10.20 -8.77 Enable SSC -12.09 -13.89 -4.19 -8.9 -8.74 -11.76 -9.02 3-1 SSC

Vertical(dB) Condition 125MHz 250MHz 375MHz 500MHz 625MHz 750MHz 875MHz Original 3.18 -5.97 0.59 -6.2 -3.96 -9.59 -9.1 Enable SSC -10 -11.67 -6.18 -10.02 -8.76 -17.71 -12.52 3-2 SSC 3-1 3-2 SSC EMI SSC FFT 3-25~3-31 3-30 3-31 750MHz 875MHz

spike Spike Noise

spike 3-12 clock

noise Clock

SSC

3-32 3-33 overshoot 825MHz noise noise

clock overshoot EMI

3-25 125MHz

3-27 375MHz

3-29 625MHz

3-31 875MHz

3-33 overshoot

3.6 Clock slew rate

Clock slew rate

Clock / 125MHz EMI

3.6.1

… 125MHz Clock 10pF GND Clock 10pF GND slew rate 3-34 3-35 [1][8]

3-34 Clock 10pF GND [1]

3-35 Clock 10pF GND PCBA [1]

3.6.2 Clock slew rate

125MHz clock 3-36 3-37 10pF clock Clock

3-36 125MHz clock

Rise Time Fall Time Clock 610.9598ps 600.1048ps Clock 10pF to GND 2.62005ns 2.10578ns 3-3 slew rate 3-36 3-37 FFT clock 10pF 125MHz Power 3-36 FFT 3-38~3-44 3-37 FFT 3-45~3-51 3-38 125MHz

3-39 250MHz

3-41 500MHz

3-43 750MHz

3-47 slew rate 375MHz

3-51 slew rate 875MHz

Slew rate EMI 3-52 3-53

3-53 slew rate EMI

Horizontal(dB) Condition 125MHz 250MHz 375MHz 500MHz 625MHz 750MHz 875MHz Original -10.35 -5.44 1.18 -2.21 -0.56 -10.20 -8.77 SSC -12.09 -13.89 -4.19 -8.9 -8.74 -11.76 -9.02 Slew rate -22.51 -16.00 -6.94 -15.81 -9.66 -14.30 -11.97 3-4 SSC Slew rate

Vertical(dB) Condition 125MHz 250MHz 375MHz 500MHz 625MHz 750MHz 875MHz Original 3.18 -5.97 0.59 -6.2 -3.96 -9.59 -9.1 SSC -10.00 -11.67 -6.18 -10.02 -8.76 -17.71 -12.52 Slew rate -11.27 -13.38 -5.51 -13.71 -11.44 -19.75 -14.07 3-5 SSC Slew rate

3.6.3

Clock 125MHz 750MHz 875MHz Noise ( ) Noise spike clock

125MHz slew

rate

clock slew rate

3-37 10pF clock loading timing spec

IC

IC

EMI

(1) Clock

(2) Clock ( ) GND slew rate Noise

1. Gigabit Ethernet 2011

2.

2009

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2012

8. IC

2006

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Spread Spectrum Clock Generator 2008