Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation

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Improvement on performance and reliability of TaN/HfO

2

LTPS-TFTs with ﬂuorine implantation

Ming-Wen Ma

a

, Chih-Yang Chen

a

, Chun-Jung Su

a

, Woei-Cherng Wu

b

,

Tsung-YuYang

b

Kuo-Hsing Kao

b

, Tien-Sheng Chao

b,*

, Tan-Fu Lei

a

a_{Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30010, Taiwan} b_{Institute and Department of Electrophysics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30010, Taiwan}

Available online 30 August 2007

The review of this paper was arranged by Guglielmo Fortunato

Abstract

In this paper, we demonstrate the low-temperature polycrystalline silicon thin-ﬁlm transistors (LTPS-TFTs) with TaN metal-gate and

HfO2gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V,

excel-lent subthreshold swing 0.15 V/decade and high Ion/Imincurrent ratio 1.9· 106

are derived without any hydrogen treatment. In addition, we also introduce the ﬂuorine implantation prior to the Si thin-ﬁlm crystallization to passivate the defects in grain-boundaries of the

channel ﬁlm and HfO2/polysilicon interface. Signiﬁcant improvements on subthreshold swing and Iminare observed. In addition, the

transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we

derive a high reliability and performance LTPS-TFT with low threshold voltage1.38 V, ultra-low subthreshold swing 0.132 V/decade

and high Ion/Imincurrent ratio 1.21· 107

Keywords: LTPS-TFTs; Metal-gate; High-j; Fluorine implantation

1. Introduction

High performance low-temperature polycrystalline-sili-con thin-film transistors (LTPS-TFTs) have been attracted much attention in many applications in recent years, espe-cially for the integrated circuit of the active matrix liquid phase-crystal displays (AMLCD)[1,2]and the most impor-tant elements for SRAM’s [3]. This is because the field effect mobility lEFin polycrystalline-silicon is significantly

higher (by two orders of magnitude) than that in amor-phous silicon[4]. However, there are many defects at the grain-boundary of polycrystalline silicon thin-ﬁlm, result-ing in the degradation of LTPS-TFTs’ performance [5]. In order to ﬁll the traps with enough charges to make the

channel more conductive, a large operation voltage was needed for the conventional LTPS-TFTs without any defects passivation[6–8]. These defects would result in very poor subthreshold swing and large threshold voltage.

The increase of gate capacitance is one eﬀective way to improve the performance of LTPS-TFTs. A large gate capacitance can attract more carriers with a smaller voltage to make the LTPS-TFTs turn on. However, a higher gate leakage current would be introduced when the thickness of gate oxide becomes thinner to make large gate capaci-tance. In order to overcome this drawback, many high-j dielectrics have been used to reduce the gate leakage cur-rent and to increase the transconductance[9–14]. Among these dielectric materials, HfO2is the most promising

can-didate of future high-j gate dielectric material due to its high permittivity (20) and thermal stability with poly-Si

[12–14].

*

Corresponding author. Tel.: +886 3 5131367; fax: +886 3 5725230. E-mail address:[email protected](T.-S. Chao).

www.elsevier.com/locate/sse Solid-State Electronics 52 (2008) 342–347

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In spite of using the high-j gate dielectrics, the defects of channel ﬁlm still exist that aﬀect the leakage current [5]. Therefore, defects passivation is necessary to improve leak-age current and Ion/Imincurrent ratio. Hydrogen plasma is

the most popular species employed to passivate defects and reduce the leakage current[15–17]. However, the introduc-tion of hydrogen passivaintroduc-tion method would degrade the reliability due to the weak Si–H bond[18,19]. In this paper, we replace the weak Si–H bond with the strong Si–F bond by using the fluorine implantation method[20–22]instead of hydrogen passivation. Finally, the metal-gate/high-j LTPS-TFTs with fluorine implantation is demonstrated for the first time.

2. Experimental procedure

The fabrication of devices started by depositing a 50 nm undoped amorphous Si (a-Si) layer at 550C in a low-pres-sure chemical vapor deposition (LPCVD) system on Si wafers capped with a 500 nm thick thermal oxide layer. Then, the ﬂuorine atoms were implanted with 11 keV implant energy and dose 5· 1014cm2 as shown in

Fig. 1a. After the ﬂuorine implantation, the a-Si layer was re-crystallized by solid-phase-crystallization (SPC) process by furnace at 600C for 24 h in a N2 ambient.

Then 500 nm thick plasma-enhanced chemical vapor depo-sition (PECVD) oxide was deposited at 300C for device isolation as shown in Fig. 1b. The device active region was formed by patterning and etching the isolation oxide. The source and drain regions in the active device region was implanted with phosphorus (20 keV at 5· 1015cm2) and activated at 600C for 24 h annealing in a N2ambient

as shown asFig. 1c. After the active region was patterning, a 75 nm HfO2was deposited by electron-beam evaporation

system as shown in Fig. 1d. An O2 treatment in furnace

was applied to improve the gate oxide quality at 400C for 30 min. Then, the gate electrode was patterning by reac-tive ion etching after TaN deposition. After the patterning of contact holes, the TFT devices were completed by probe pads formation etching after aluminum deposition by ther-mal evaporation system as shown inFig. 1e. The measure-ment of device has gate length and width of 10 and 100 lm, respectively. The threshold voltage is deﬁned as the gate voltage at which the drain-current reaches 100 nA· W/L and VDS= 0.1 V. Field eﬀect mobility lFE is extracted

from the maximum transconductance (Gm).

3. Results and discussion

The transfer characteristics IDS–VGS of the TaN/HfO2

gate stack structure LTPS-TFTs with and without ﬂuorine implantation were shown inFig. 2. It indicates a signiﬁcant

Si-Substrate SiO2 amorphous-Si F19+ Si-Substrate SiO2 SiO2 Poly-Si SiO2

SiO2 SiO2 SiO2

Si-Substrate Poly-Si P31+ SiO2 N+ N+ HfO2 SiO2 Si-Substrate Si SiO2 N+ N+ HfO2 TaN Al Al SiO2

Fig. 1. Process ﬂow of high-j HfO2gate dielectric and TaN gate LTSP-TFT structure with ﬂuorine implantation.

0 1 2 3 4 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 V DS = 1V

Drain Current (A)

Gate Voltage (V)

Solid: without Fluorine implant Hollow: with Fluorine implant W/L = 100μm/10μm

V

DS = 0.1V

Fig. 2. The transfer characteristics IDS VGSof the TaN/HfO2gate stack structure LTPS-TFTs with and without ﬂuorine implantation.

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Imin-current reduction from 11.1 to 1.71 pA, subthreshold

swing improvement from 0.150 to 0.132 V/decade, and a positive 0.48 V threshold voltage shift after the ﬂuorine ion implantation. The Imincurrent and subthreshold swing

are related to grain defects and interface density of states

[5]. By neglecting the depletion capacitance in the channel layer, the eﬀective interface-trap-state density (Dit) near

the HfO2/poly-Si interface can be evaluated from the

sub-threshold swing (S.S.) as equation[23]

Dit¼ S:S: ln 10 _q KT 1 _C ox q : ð1Þ

The eﬀective interface-trap-state density (Dit) was

im-proved from 1.7· 1012cm2 to 1.37· 10 12cm2. It indi-cates a 19.41% reduction of Dit due to the ﬂuorine

passivation. In addition, a positive 0.48 V threshold voltage indicates that ﬂuorine would introduce negative ﬁxed oxide charges in HfO2, and the result of the introduction of

neg-ative ﬁxed charge by ﬂuorine is consistence with the work by Maegawa et al.[24].Fig. 3shows the transconductance Gmof the TaN/HfO2gate stack structure LTPS-TFTs with

and without ﬂuorine implantation. A slightly improvement of transconductance Gmis observed. It is due to the

passiv-ation of the eﬀective interface-trap-state density (Dit) after

the fluorine ion implantation. In addition, the ion implan-tation would also result in some amorphization of the channel film, and the channel film may have the chance to form larger grains after re-crystallizing annealing. How-ever, the grain size effect due to the fluorine ion implanta-tion would not be significant under a thin channel film and low implantation energy. Yang et al. [25] have demon-strated that the grain size effect would not be obvious if the channel film was thin enough and fluorine ion implan-tation energy was low, even with 60-nm channel thin-film, which is thicker than our case, and higher ion implantation energy (15 keV)[25]. This unobvious grain size effect is also consistence with the result of Tu et al.[6].

The grain-boundary trap-state densities (Ntrap) with and

without ﬂuorine implantation were also estimated by Levinson and Proano method [26,27]. Fig. 4 exhibits the plots of ln[IDS/(VGS VFB)] versus 1/(VGS VFB)2curves

at VDS= 1 V and high VGS, where the ﬂat-band voltage

(VFB) is deﬁned as the gate voltage that yields the minimum

drain-current from the transfer characteristic. The grain-boundary trap-state densities (Ntrap) can be determined

from the square root of the slope Ntrap¼ Cox q ffiffiffiffiffiffiffiffiffiffiffiffiffiffi jSlopej p : ð2Þ

FromFig. 4, it is apparent that the grain-boundary trap-state densities decrease from 2.89· 1012cm2 to 2.15· 1012cm2 after fluorine passivation. It indicates an improvement about 25.6% on the grain-boundary trap-state densities. The important parameters of LTPS-TFTs are listed inTable 1. A significant performance improve-ment was observed by the fluorine ion implantation to achieve low threshold voltage1.38 V, excellent subthresh-old swing0.132 V/decade, and high Ion/Imincurrent ratio

1.21 · 107

. These improvement results can be attributed to the traps passivation of Dit and Nit for 19.41% and

25.6% improvement, respectively.

The reliability of LTPS-TFTs is also another important issue. Because the operation voltage of LTPS-TFTs with TaN/HfO2 gate stack structure was within 3 V, we

employee the hot carrier stress with VGS VTH=

VDS= 5 V for 1000 s instead of VGS= VDS= 5 V because

that diﬀerent hot carrier stability is observed under diﬀerent VGSand constant VDS[28]. The threshold voltage

stability (DVTH= VTHf VTHi) was improved from 1.6 V

to 1.22 V of the threshold voltage shift after 1000 s hot carrier stress as shown inFig. 5. Positive voltage shifts of threshold voltage indicate that the electrons were trapped by the gate dielectric HfO2 under hot carrier stress. The

ﬂuorine implanted device shows a smaller threshold voltage shift indicates that fewer electrons were trapped in HfO2

0 1 2 3 4 0 2 4 6 8 10 12 14 16 18 20 V DS = 0.1V W/L(μm) = 100/10 Transconductance G (m μ S) Gate Voltage (V)

without Fluorine implant with Fluorine implant

Fig. 3. The transconductance Gmof the TaN/HfO2gate stack structure LTPS-TFTs with and without ﬂuorine implantation.

0.0 0.2 0.4 0.6 0.8 1.0 -16 -15 -14 -13 -12 -11 -10 -9 -8 N trap = 2.15 x 10 12 cm-2 N trap = 2.89 x 10 12 cm-2 ln [I DS /(V GS - V FB )] 1/(V_GS - V_FB)2 (V-2)

without Fluorine implant with Fluorine implant

Fig. 4. The plots of ln [IDS/(VGS VFB)] versus 1/(VGS VFB) 2

curves at VDS= 1 V and high VGS.

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after fluorine passivation. Fig. 6 shows the gate leakage current of LTPS-TFT with and without fluorine ion implantation. A smaller reduction rate of gate leakage cur-rent of the fluorine-implanted device under hot carrier stress was observed, which shows a smaller electron trap-ping rate than the device without fluorine ion implantation.

Fig. 7 shows the transconductance Gm degradation of

the LTPS-TFT with and without ﬂuorine ion implanta-tion. For the device without ﬂuorine ion implantation, a suddenly high degradation rate of transconductance Gm

was happened within 50 s of hot carrier stress, and then a saturation behavior was observed. For the

ﬂuorine-implanted device, the suddenly high degradation rate region of transconductance Gm was within 20 s. In

addi-tion, the degradation of transconductance Gm after

1000 s of hot carrier stress was more serious for the LTPS-TFT with ﬂuorine ion implantation. In the short stress time regime, the degradation of Gm for the

fluo-rine-implanted device is smaller than that of the device without fluorine implantation. Because the grain-bound-aries and the high-j/poly-Si interface of the fluorine-implanted device were passivated by the strong Si–F bonds, the device was less degraded as the stress was ini-tially performed. As stress time increases, the fluorine-implanted device shows a larger degradation rate in Gm

than the one without ﬂuorine implantation. We attributed the severe degradation of the ﬂuorine-implanted device to the more strict stress current, and this can be further explained from Fig. 8, which shows the time dependence of the driving current under hot carrier stress.

It is worth noting that the fluorine-implanted device shows a larger driving current through all the stress time. The degradation improvement of driving current is attrib-uted to the defects passivation by fluorine. Chern et al. have proposed that the fluorine can passivate uniformly the band tail-states, which are produced due to strain bond, and midgap deep-states, which are produced due to dan-gling bond, within the poly-Si channel film [29]. Fluorine can break the strain bond of channel film, like Si–Si and Si–O–Si bond, to relax the local strain and also passivate the dangling bonds in grain-boundaries and HfO2

/polysil-icon interface [20–22]. Therefore, hot carrier immunity is enhanced due to the strong Si–F bond.

0 200 400 600 800 1000 0.0 0.3 0.6 0.9 1.2 1.5 1.8

Hot Carrier Stress: V

GS - Vth0 = 5V

without Fluorine implant with Fluorine implant W/L = 100μm/10μm

Threshold Voltage Shift

Δ

VTH

(V)

Stress Time (Second)

Fig. 5. The threshold voltage shift DVTof TaN/HfO2LTPS-TFTs with and without ﬂuorine implantation after 1000-s hot carrier stress.

100 101 102 103

10-10 10-9 10-8

GS - Vth0 = 5V

Gate Current (A)

without Fluorine implant with Fluorine implant W/L = 100μm/10μm V

GS = 4V, VDS = 0.1V

Fig. 6. The gate leakage current of TaN/HfO2 LTPS-TFTs with and without ﬂuorine implantation during the hot carrier stress.

0 200 400 600 800 1000 0 5 10 15 20 25

without Fluorine implant with Fluorine implant W/L = 100_μm/10μm Hot Carrier Stress: V

GS - Vth0 = 5V

Gm

Degradation (%

)

Fig. 7. The transconductance Gmdegradation of TaN/HfO2LTPS-TFTs with and without ﬂuorine implantation during 1000 s hot carrier stress. Table 1

Device parameters of TaN/HfO2gate stack TFTs with and without Fluorine implantation

VTH(V) Swing (V/decade) Gm(lS) Imin(pA) Ion(lA) Ion/Imin(106) Dit(1012cm2) Ntrap(1012cm2)

Control 0.9 0.15 15.9 11.1 21.1 1.9 1.7 2.89

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Finally, a high performance LTPS-TFT with low thresh-old voltage1.38 V, ultra-low subthreshold swing 0.132 V/ decade, high Ion/Imin current ratio 1.21· 107, and strong

hot carrier immunity is derived. Consequently, the metal-gate/high-j LTPS-TFTs with ﬂuorine implantation is dem-onstrated for the ﬁrst time.

4. Conclusions

The high performance LTPS-TFTs using TaN/HfO2

gate stack structure and fluorine implantation prior the Si thin-film crystallization to passivate the defects in grain-boundaries and interface of thin-film is proposed for the first time. Improvements on higher Ion/Imin current ratio

and excellent subthreshold swing are derived due to the ﬂuorine implantation. These devices exhibit excellent elec-trical characteristics even without hydrogen passivation or excimer laser crystallization process steps. These results suggest that the ﬂuorine implantation is one of the simple methods to improve the characteristics of low-temperature polycrystalline-silicon TFTs.

Acknowledgements

This work was supported by the National Science Coun-cil, Taiwan, under contract No: NSC-95-2221-E-009-272. Authors would like to thank the processes support from National Nano Device Labs and the Nano Facility Center of the National Chiao Tung University.

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