The impact of high-frequency characteristics induced by intrinsic parameter fluctuations in nano-MOSFET device and circuit

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The impact of high-frequency characteristics induced by intrinsic parameter

ﬂuctuations in nano-MOSFET device and circuit

Ming-Hung Han

a

_{, Yiming Li}

_a,b,*

_{, Chih-Hong Hwang}

a a

Department of Electrical Engineering and Institute of Communications Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan b

National Nano Device Laboratories, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history:

Received 30 November 2009

Received in revised form 2 January 2010 Available online 25 March 2010

a b s t r a c t

This work estimates the influences of the intrinsic parameter fluctuations consisting of metal gate work-function fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal–oxide–semiconductor field effect transistors (MOSFETs) and circuits by using an experimentally validated three-dimensional device and coupled device–circuit simulations. The domi-nance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, high-frequency gain, 3 dB bandwidth, unity-gain bandwidth, power, and the power-added efficiency has been found. Similar to the trend of the cut-off frequency, the PVE and RDF dominate both the device and circuits character-istic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario.

1. Introduction

Variabilities of performance and yield in nanoscale complemen-tary metal oxide semiconductor (CMOS) devices are great of inter-est and become crucial for circuit design. The intrinsic device parameter ﬂuctuations that result from process variation effect (PVE)[1], random discrete dopants ﬂuctuation (RDF) [2–8], and other causes substantially impact device and circuit characteristics

[9]. Although high-

j

/metal-gate technology[10]is the key to re-duce the intrinsic parameter fluctuations, the use of metal as a gate material introduces a new source of random variation, the work-function fluctuation (WKF) [11,12]. The WKF-induced threshold voltage (Vth) fluctuation has been reported and the scope is limited

to the transistors[13]. Additionally, the device and circuit perfor-mance may depend on different device characteristics. The identi-fication of the dominant fluctuation source in the device and circuit characteristic fluctuations is urgent for the development of ad-vanced nanoscale CMOS technologies. The impact of intrinsic parameter fluctuations on the high-frequency characteristics and power-efficiency is lacked. A comprehensive understanding of these fluctuations’ effect on nanoscale CMOS transistors and cir-cuits is urgent.

In this study, we extensively estimate the inﬂuences of the intrinsic parameter ﬂuctuations (PVE, WKF, and RDF) on 16-nm-gate planar bulk MOSFETs’ DC/AC and circuits’ high-frequency characteristics. The results of our study show that for the device AC characteristics including gate capacitance and cut-off frequency

fluctuations, the WKF is found to bring less impact on these two characteristics due to the screening effect of the inversion layer. Similar to the trend of the cut-off frequency, the PVE and RDF dom-inate the high-frequency property and the power-added efficiency of a common-source amplifier. The major fluctuation sources in nanoscale transistors and circuits have been presented herein and then verified by the related devices and circuits characteristics.

2. Simulation technique

The devices we investigated is the 16-nm-gate planar bulk MOSFETs (width: 16 nm) with amorphous-based TiN/HfSiON gate stacks and an EOT of 1.2 nm. The nominal channel doping concen-trations are 1.48 1018_cm3_{and the V}

this calibrated.Fig. 1a–d

illustrates the RDF-induced ﬂuctuation, the simulation mainly fol-lows our recent work[7–9], 758 dopants are randomly generated in a large cube of (80 nm)3_{, in which the equivalent doping}

concen-tration is 1.48 1018_cm3_{, as shown in}_{Fig. 1}_{a. Then the large cube}

is partitioned into 125 (16 nm)3_sub-cubes.

The numbers of dopants vary from 0 to 14, and the average number is 6. These sub-cubes are mapped into the device channel for the 3D device simulation with discrete dopants, as shown in

Fig. 1h. The PVE includes gate length deviation and line edge roughness, and we use Vth roll-off characteristics to estimate

PVE-induced ﬂuctuations, as shown inFig. 1e[9]. For WKF, the de-vice gate area is composed of a small number of grains, as shown in

Fig. 1e. A Monte-Carlo approach is proposed for examining such ef-fect, the gate area is ﬁrst partitioned into several parts. Then, the workfunction of each partitioned area is randomly generated based on the properties of metal; the TiN is used in our work, as shown in

* Corresponding author. Tel.: +886 35712121x52974. E-mail address:ymli@faculty.nctu.edu.tw(Y. Li).

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Fig. 1g. The effective device workfunction is the average of all parts and used for estimation of WKF-induced ﬂuctuations.Fig. 1i is the explored common-source ampliﬁer, in which a coupled device–cir-cuit simulation approach[10]is employed to ensure the best accu-racy. The physical models and accuracy of such large-scale simulation approach have been quantitatively calibrated by exper-imentally measured results[9].

3. Results and discussion

Fig. 2indicates the components of threshold voltage ﬂuctuation (

r

Vth) for the examined planar bulk NMOSFETs. The total

r

Vth,

r

Vth,total, are obtained from the statistical addition shown in below:

r

2 Vth;total

r

2 Vth;PVEþ

r

2 Vth;WKFþ

r

2 Vth;RDF ð1Þ

The Vth,PVE, Vth,WKF, and Vth,RDFare the PVE-, WKF-, and

RDF-in-duced

r

Vth, respectively. The results show that the RDF dominates

the Vthﬂuctuation in NMOSFETs. Notably, the statistical addition of

individual fluctuation sources herein, Eq.(1), simplifies the vari-ability analysis of nano-devices and circuits, significantly [13]. The dominant source of fluctuation will not be significantly altered.

Fig. 3summarizes the gate capacitance ﬂuctuations (

r

Cg) with 0,

0.5 V and 1.0 V gate bias. Different to the results of Vthﬂuctuation,

the WKF brought less impact on gate capacitance ﬂuctuation. At zero gate bias or negative gate bias, the accumulation layer screens the impact of WKF. Additionally, at low gate bias, the total capac-itance decreases because of the increased depletion region. The associated value of Cgﬂuctuation is small. The capacitive response

is then dominated by increment of inversion in the moderate

L

_g

(nm)

10 20 30 40

V

th

(V)

0.05 0.10 0.15 0.20 0.25 0.30

σ

V

_th,Lg 2.4 1.9 45 16 Technology node (nm) 0.8 LER, 3σ (nm) 0.7 Lg, 3σ (nm) 2.4 1.9 45 16 Technology node (nm) 0.8 LER, 3σ (nm) 0.7 Lg, 3σ (nm)

σ

L

_g

V

_th

L

_g 0.8 2.4 LER, 3σ (nm) 0.7 1.9 Lg, 3σ (nm) 16 45 Technology node (nm) 0.8 2.4 LER, 3σ (nm) 0.7 1.9 Lg, 3σ (nm) 16 45 Technology node (nm)

V

DD

V

IN

Planar

MOSFET

V

OUT

C

R

2

R

1 Common Source Amplifier

V

DD

V

IN

Planar

MOSFET

V

OUT

C

R

2

R

1 Common Source Amplifier

(f)

(g)

(e)

(h)

Silicon

Source _Gate _Drain

16 nm

16 nm 16 nm

Silicon

Source _Gate _Drain

16 nm 16 nm 16 nm σLg/σPVE

(i)

(a)

1.48 1018 _cm-3 _{758 dopants} in (80x80x80 nm3_{) cube} 16nm 16n_m 1 6 n m zero dopants in 16 nm3_cube 16nm 16n_m 1 6 n m zero dopants in 16 nm3_cube 14 dopants in 16 nm3_cube 16nm 1 6 n m 14 dopants in 16 nm3_cube 16nm 1 6 n m zero dopant in (16 nm)3 _cube 14 dopants in (16 nm)3 _cube

(c)

(b)

Dopants in (16nm)3 Cube 0 5 10 15 F re quency 0 5 10 15 20 25 -3σ +3σ 0 14 Mean = 6 -3σ +3σ 0 14 Mean = 6

(d)

NMOS Device 4.4 4.6 WK (eV) 40% <111> 60% <200> TiN Prob. Orientation Material NMOS Device 4.4 4.6 WK (eV) 40% <111> 60% <200> TiN Prob. Orientation Material WK1 WK2 WK3 … … WK1 WK2 … WK1 WK2 WK3 … … WK1 WK2 … 1

φ

2 3

φ

1

φ

2 3

φ

Fig. 1. (a) 758 Dopants are randomly generated in a large cube of (80 nm)3_{. The number of channel dopants in device may vary from 0 to 14, and the average number is 6 (b–} d). (e) The Vthroll-off characteristics for estimating PVE. (f) The gate area is composed of a small number of grains, and the estimation of WKF according to the probability in (g). (h) The explored 16 nm planar MOSFETs for 3D simulation. (i) The tested common-source ampliﬁer.

0 20 40 60 80 18.1 24.3 61

PVE

WKF RDF

Total

σ

V

th

(mV)

69 NMOS

Fig. 2. TherVthinduced by PVE, WKF, and RDF for n-type planar NMOSFETs.

0.00 0.05 0.10 0.15 0.20 0.25 0.30 VG = 0.0 V VG = 0.5 V VG = 1.0 V

PVE

0.102 0.082 0.165 0.159 0.019 0.044 0.103 0.019 0.055 σ Cg (x10 -3 fF) σ Cg (x10 -3 fF) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 VG = 0.0 V VG = 0.5 V VG = 1.0 V

PVE

WKF

RDF

0.102 0.082 0.165 0.159 0.019 0.044 0.103 0.019 0.055

Fig. 3. TherCgat VG= 0, 0.5, and 1 V for n-type planar MOSFETs with PVE, WKF, and RDF.

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inversion. The device characteristics are then impacted by intrinsic parameter induced electrostatic potentials. If the high VG is

achieved, the inversion layer is formed below the surface of the gate oxide and the total gate capacitance is mostly contributed by the gate oxide capacitance (Cox). Therefore, the variation of

capacitance now again becomes the variation of capacitance of gate oxide (Cox). Under strong inversion, the gate capacitance is

dominated by the inversion layer and a small change resulting from the WKF in the voltage across the MOS structure will induce a differential change in the inversion layer charge density.

The WKF is therefore bringing less impact on the gate capaci-tance fluctuation because the inversion charge responds to the change in capacitor voltage (i.e., the WKF is now screened by the inversion layer). Similarly, in RDF, the impact of the individual do-pants induced electrostatic potential variation is screened by the inversion layer itself. However, the screening effect of inversion layer is weakened by discrete dopants positioned near the channel surface. Therefore, the gate capacitance fluctuation is still obvi-ously fluctuated at high gate bias. Our preliminary results show that the PVE and RDF dominate the gate capacitance fluctuations at all gate bias conditions, respectively. The impact of the WKF on Cgis reduced significantly due to the screening effect. Notably,

the PVE brings direct impact on gate length and therefore inﬂu-ences the gate capacitance. The PVE induced gate capacitance ﬂuc-tuation is independent of screening effect and should be noticed when the transistor operated in high gate bias.

Fig. 4a–c shows the cut-off frequency (FT=

v

sat/2

p

Lg= gm/2

p

Cg)

and its ﬂuctuation versus VG, in which the solid line shows the

nominal case with 1.48 1018_cm3_{channel doping, the dashed}

lines are ﬂuctuated cases, and the symbol line shows averaged re-sult. The gmand

v

satare the transconductance and the saturation

velocity of the transistors, respectively. WKF-induced FT

fluctua-tion diminished as the saturafluctua-tion of the carrier velocity occurs. However, the PVE-induced FTfluctuation is still significant owing

to the direct inﬂuence of gate length (Lg) on gate capacitance. As

for RDF, the carrier-impurity scattering alters the saturation

veloc-ity, and therefore FTﬂuctuation does not diminish in high-ﬁeld

re-gion. Note that the nominal and the averaged values of FT are

similar to the results of WKF and PVE. However, in RDF, the devi-ation between the nominal and the averaged FTincreases as VG

in-creases due to the randomness of carrier-impurity scattering events and carrier velocity variations[14]. The intrinsic parameter induced FTﬂuctuations are summarized inFig. 4d, where the RDF

and PVE are the two major factors. The RDF and PVE play the dom-inating factor in the FTﬂuctuation. Notably, the impacts of RDF and

WKF on FTﬂuctuation are suppressed at higher VG(>0.6 V) due to

the screening effect. The obtained results are similar to the results as shown inFig. 3, in which the WKF bring insigniﬁcant impact on Cgand FT.

Fig. 5presents the characteristics of the employed common-source power amplifier circuits. The nominal output power, the cir-cuit gain, and the power-added-efficiency of the common-source power amplifier as a function of the input power are plotted, where Poutand Pinare output and input power, respectively. A sinusoid

in-put wave with 0.5 V offset voltage is used as inin-put signal. The

de-V_G (V) 0.0 0.2 0.4 0.6 0.8 1.0 FT Fluctuation (GHz) 0 10 20 30 40 50 60 70 WKF PVE RDF 0.0 0.2 0.4 0.6 0.8 1.0 0 100 200 300 400 500 RDF Fluctuated cases Nominal case Averaged

RDF

V_G (V) V_G (V) 0.0 0.2 0.4 0.6 0.8 1.0 FT ( GHz) FT ( GHz) 0 100 200 300 400 500 RDF Fluctuated cases Nominal case Averaged

RDF

0.0 0.2 0.4 0.6 0.8 1.0 0 100 200 300 400 500 WKF Fluctuated case Nominal case Averaged

WKF

V_G (V) V_G (V) 0.0 0.2 0.4 0.6 0.8 1.0 FT (H z) FT (H z) 0 100 200 300 400 500 WKF Fluctuated case Nominal case Averaged

WKF

0.0 0.2 0.4 0.6 0.8 1.0 0 100 200 300 400 500

PVE Fluctuated case Nominal case Averaged

PVE

V_G (V) V_G (V) 0.0 0.2 0.4 0.6 0.8 1.0 FT (Hz) FT (Hz) 0 100 200 300 400 500

PVE Fluctuated case Nominal case Averaged

PVE

(a)

(b)

(c)

(d)

Fig. 4. TherFTinduced by: (a) PVE, (b) WKF, and (c) RDF. (d) The summarizedrFTfor the studied planar MOSFETs.

P_in (dBm) -30 -20 -10 0 10 20 Pout (dBm)/Gain (dB) -20 -10 0 10 20 30 40 P_out Gain Power-Added-Efficiency (%) 0 5 10 15 20 25 PAE

P

_out Gain PAE PAE (%) = ((P_out-P_in) /P_DC)x100%

Fig. 5. Output power, circuit gain, and power-added-efﬁciency of the explored common-source power ampliﬁer as a function of input power. The calculation of PAE follows the formula as shown in the inset.

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vice channel is continuously doped and the operation frequency is 108_{Hz. Owing to the limitation of output signal swing, the nominal}

value of Poutis saturated after 10 dB m input power, which in turn

decreases the gain of circuit. The gain ﬂuctuations of the planar MOSFETs resulted from PVE, WKF, and RDF are then explored in

Fig. 6a–c. Since the PVE and RDF dominate gate capacitance fluctu-ations due to significant affected the channel length and depletion region, the PVE and RDF play important roles in high-frequency characteristic fluctuation, as shown inFig. 6d. Effects of WKF in high-frequency characteristics are negligible in this scenario.

Addi-P_in (dBm) Gain (dB) 0 2 4 6 8 10

RDF

P

_in

(dBm)

Gain Fluctuation (dBm)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 RDF PVE WKF

(c)

(a)

(b)

(d)

P_in (dBm) -30 -20 -10 0 10 20 -30 -20 -10 0 10 20 -30 -20 -10 0 10 20 -30 -20 -10 0 10 20 Gain (dB) 0 2 4 6 8 10

PVE

P

_in

(dBm)

Gain (dB)

0 2 4 6 8 10

WKF

Fig. 6. The circuit gain characteristics of the planar MOSFETs power amplifier with: (a) PVE, (b) WKF, and (c) RDF fluctuations, respectively. (d) The summarized circuit fluctuations.

Gain Fluctuation (%)

0 1 2 3 4 5 6 7

PVE

WKF

RDF

3.8

0.7

5.7 3dB BW Fluctuation (%)

0 2 4 6 8 10 12 14 16

PVE

WKF

RDF

11.1

2.4

14.1 Unity-Gain BW Fluctuation (%)

0 2 4 6 8 10 12

PVE

WKF

RDF

4.7

0.72

10.4 Frequency (Hz)

108 ₁₀9 ₁₀10 ₁₀11

Gain (dB)

0 2 4 6 8 10 12 14

Intrinsic Parameter Fluctuated Nominal Case Gain fluctuation Unity-Gain BW fluctuation 3db BW fluctuation

(a)

(c)

(d)

(b)

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tionally, the input signal is a sinusoid wave; therefore, the device may operate in different operational region if the amplitude of the sinusoid wave is large enough. The enlarged gain fluctuation with increasing input power is resulted from the larger portion of device operation in linear region. While the magnitude of input signal swing increases larger than 0.178 V (the input power is lar-ger than 15 dB m), a part of device operation enters the cut-off re-gion and therefore decreases the gain fluctuation. The high-frequency characteristic fluctuations are then investigated in

Fig. 7a, where the ﬂuctuation of the high-frequency circuit gain, the 3 dB bandwidth, and the unity-gain bandwidth are extracted, as shown inFig. 7b–d, respectively. Similar to the result ofFigs. 3 and 4, the RDF and PVE dominates the high-frequency characteris-tic ﬂuctuations and WKF become marginal in this analyzing skeleton.

4. Conclusions

In this study, we have estimated the influences of the intrinsic parameter fluctuations in 16-nm planar MOSFETs and circuits. Our results have shown that the RDF dominates the device thresh-old voltage fluctuation. For gate capacitance and cut-off frequency fluctuation, due to the screen effect of the device inversion layer, the WKF can be neglected. For the high-frequency characteristics, the circuit gain, the power, and the power-added efficiency were explored. Similar to the trend of the device cut-off frequency, the PVE and RDF are dominated and the WKF shows less impact. We are currently working on studying the possible correlations be-tween each fluctuation sources. The interaction of Vthchange due

to different sources may be important and need to be properly incorporated.

Acknowledgement

This work was supported in part by National Science Council (NSC), Taiwan under Contract NSC-97-2221-E-009-154-MY2 and by the TSMC, Hsinchu, Taiwan under a 2008-2010 grant.

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