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The effect of pulsed laser annealing on the nickel silicide formation

Hou-Yu Chen

a,*

, Chia-Yi Lin

b

, Chien-Chao Huang

b

, Chao-Hsin Chien

a,b

a

Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan b

National Nano Device Laboratory, Hsinchu, Taiwan

a r t i c l e

i n f o

Article history:

Received 9 February 2010 Accepted 13 June 2010 Available online 17 June 2010

Keywords: NiSix

Pulsed laser annealing (PLA) Schottky barrier height (SBH) Rapid thermal annealing (RTA)

a b s t r a c t

The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSixinterfacial layer on (1 0 0) sili-con. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore, PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA sili-cide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices per-formance enhancement.

Ó 2010 Elsevier B.V. All rights reserved.

1. Introduction

Nickel silicide is a common silicide material for advanced MOS transistors due to its low formation temperature, low Si consump-tion, and low line width sheet resistance dependence as compared to cobalt or titanium silicide. However, Fermi-level pining at the NiSi/Si interface sets the work function of NiSi to a mid-gap value of around 4.7 eV, leading to a high source/drain resistance. For this reason, techniques that can potentially reduce the NiSi Schottky barrier height (SBH) are of interest, as they will allow the contin-ued use of nickel silicide in future transistors. A previous study showed that the single crystalline and uniform NiSi2 phase can

effectively reduce the SBH by approximately 0.3 eV[1]. However, NiSi2phase transformation need high temperature and is generally

much less stable on the (1 0 0) Si surface than on the (1 1 1) surface

[2]. This study report that the advantage of using PLA for NiSix

for-mation on (1 0 0) Si. The PLA application is attractive for ultra-scaled semiconductor devices dopant activation due to its high effective temperature with diffusion-less junction profile. By using PLA during silicidation, the Schottky barrier height modulation is observed due to the silicide phase change at silicon interface. The morphology of silicide/silicon interface is smooth when a two-steps annealing process with optimized laser power is adopted. In addition, the strain application for carrier mobility enhancement is more challenge when the technology node is continue shrinking. The aggressive scaling design rules limit the strength of the strain

developed in the process due to shrinking device dimensions and issues of proximity[4]. For this reason, process strain enhancement approached from either a type of material aspect or other process that leads to device process optimization become an indispensable procedure for maintaining the strain benefit of ultra-scaled devices

[5,6]. The tensile stress enhancement of NiSixsilicide formation by

using PLA is also observed and discussed in this report.

2. Experimental

For experimental study, 6 inch (1 0 0) n and p-type wafers were used as substrates. Before Ni deposition, the wafers were cleaned in HF acid and rinsed with de-ionized water. Inductively-coupled plasma (ICP) pre-sputter was performed for 10 s for native oxide removal, the 20 nm Ni and 15 nm Ti were then deposited sequen-tially by physical vapor deposition (PVD). The Ti was used as a cap-ping layer to avoid oxygen contamination during silicidation[7]. Wafers then underwent different two-step annealing processes for silicidation and the process flow is shown inFig. 1. The flow-1 sample employed a two-step rapid thermal anneal (RTA) at 300 °C for 15 s and 400 °C for 30 s in ambient N2as a baseline

con-dition. The flow-2 sample was prepared by replacing the first RTA with PLA, and the flow-3 sample was prepared by replacing the second RTA with PLA. The RTA was conducted with Heat Pulse 610 and the PLA was conducted with a pulsed Nd:YAG laser with a 355 nm wavelength and 10 ns pulse period. After the first anneal-ing process, un-reacted Ni and Ti was removed by a wet etchant consisting of H2SO4 and H2O2 with a ratio of 4:1. The sheet

resistance of the sample was measured using a 4-point probe.

0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.06.009

*Corresponding author. Tel.: +886 3 5726100; fax: +886 3 5735670. E-mail address:[email protected](H.-Y. Chen).

Microelectronic Engineering 87 (2010) 2540–2543

Contents lists available atScienceDirect

Microelectronic Engineering

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The blank wafer stress was measured using a Tencor FLX-2320, which measures the change in the radius of curvature of the sub-strate. The Schottky diode fabrication was initiated with LOCOS isolation and followed by 35 nm thermal oxide growth. The active area was implanted with BF2at 70 keV and a dose of 2  1013cm 2

for p-type substrate and phosphorus at 120 keV and a dose of 7.5  1012cm 2for n-type substrate. After implantation, samples were annealed in a 1100 °C furnace for 10 min to activate the dop-ant. Finally, different Ni silicide formation processes were evalu-ated and electrical testing was performed using a HP4156.

3. Result and discussion

The correlations of sheet resistance and blanket wafer stress capacities for different annealing conditions and PLA energy densi-ties are shown inFig. 2. Increased sheet resistance and significant tensile stress enhancement of laser annealed samples are observed compare to the RTA samples. Glancing-incidence XRD was used for silicide phase characterization and result is shown inFig. 3. The spectrum of the two-step RTA sample reveals inhomogeneous phases of Ni silicide, including Ni-rich silicide and NiSi formed with two-step RTA. By replacing the second RTA with PLA, the rising peak intensity of the Si-rich NiSixphase is observed in the

spec-trum. Increasing the PLA energy density above 1.5 J/cm2 causes

the Ni silicide phase to mostly transfer to NiSi2and induce

signif-icant sheet resistance increasing. Fig. 4 shows transmission

electron microscopy (TEM) images of different silicidation condi-tions. Fig. 4a shows that the sample using two-step RTA which exhibits a rough silicide to silicon interface due to the coexistence of inhomogeneous phases.Fig. 4b shows that the sample using PLA first which exhibits an ultra-thin NiSi2formation. The composition

of the thin silicide is verified by an energy dispersive X-ray spec-trometer (EDS), revealing that 0.6 J/cm2of PLA energy is sufficient

to incite the Ni to react with Si to form NiSi2. The resulting thin

sil-icide is favorable for ultra shallow junction, however, a NiSi2

{1 1 1} facet appears which would induce junction spiking issue for devices with shallow junction profile. Compared to the PLA-first sample with the same laser energy, the sample replacing the sec-ond RTA with PLA exhibits a flat silicide to silicon interface which is shown inFig. 4c. The PLA energy induces the melting of nickel silicide, and this melt front propagates down to the silicide and sil-icon interface. The mixing of silicide and silsil-icon occurs via a liquid phase diffusion, which leads to a flat interface and silicon-rich sil-icide melt near the interface[8]. The silicide thickness and stress difference correlation is further investigated to exclude the volume change effect, results are shown in Fig. 5. The different silicide thickness are obtained by increasing the RTA temperature and PLA energy density for flow-1 and flow-3, respectively and the sil-icide layer thickness are investigated by TEM. Based on the result, the combined effect of an increased effective temperature of PLA with different silicide phases formed after PLA can lead to thermal stress differences and result in higher tensile stress. Although the strain benefit decreases as the silicide thickness decreases, the im-proved silicide morphology using pulsed laser annealing is benefi-cial for process control with an aggressive reduction in silicide to channel proximity, as it obtains higher channel strain with resis-tance reduction for future extremely scaled transistors.

Fig. 6a shows the comparison of two favorable Schottky diode I–V characteristics. The area of the measured diode is 4  10 6cm2and the zero bias SBH of each sample is deduced by linear fitting of the forward-bias I–V characteristics based on the thermionic emission model at room temperature, using an effec-tive Richardson constant of 32 A/cm2K2 in the calculation [9].

The diode with the PLA shows approximately 0.2 eV SBH increase for hole from a highly rectifying diode with improved ideality fac-tor (n = 1.28) and the obtained SBH (Ubo= 0.68 eV) is close to the

reported value for NiSi2on a (1 0 0) p-type substrate[10,11]. The

result is also examined by using the slope of the Arrhenius plot in the reverse-bias region and the result is in good agreement with the value deduced from forward bias current which is shown in

Fig. 6b. At the same time,Fig. 6c shows an ohmic-like characteristic

Flow-1

Flow-2

Flow-3

RTA1 RTA2 RTA1

PLA

Non-reacted metal removal

PLA

RTA2 Ni/Ti deposition Native oxide removal

Non-reacted metal removal Non-reacted

metal removal

Fig. 1. Three different annealing process flow chart for silicidation evaluation.

100 101 102 103 10-2 10-1 100 101 102 Flow-1 Flow-2(0.6J/cm2) Flow-3(0.6J/cm2 ) Flow-3(1.5J/cm2) Stress (Gpa ) Rsh(Ohm/sq)

Fig. 2. The stress and sheet resistance correlations of different annealing sequences. The PLA energy density of the flow-3 samples were 0.6 J/cm2

and 1.5 J/cm2 . 25 30 35 40 45 50 55 60 65 70 75 100 150 200 250 300 350 400 1 3 4 NiSi: 2:Flow-2; 0.6 J/cm2 4:Flow-3; 1.5 J/cm2 3:Flow-3; 0.6 J/cm2 Ni2Si: NiSi2: Intensity (a.u.) Position (2

θ

) 1:Flow-1; 2

Fig. 3. GIXRD spectrums results for different silicidation sequences. H.-Y. Chen et al. / Microelectronic Engineering 87 (2010) 2540–2543 2541

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of laser irradiated sample which was fabricated on n-type sub-strate, also proves SBH modulation effect. Fine tuning the energy density of PLA within the adequate range improves the diode ide-ality factor, which is shown in Fig. 7, due to the formation of smooth NiSi2 morphology at the silicon interface. However,

increasing the laser energy density above a critical range causes a significant increase of leakage current and a drop in the ideality

factor due to degraded interface morphology. From TEM investiga-tion, a Si-rich (Ni0.23Si0.77) Ni silicide forms and leads to

deteriora-tion in the interface flatness which cause the diode characteristics degradation. For further improvement of the diode ideality factor, while maintaining a reasonable sheet resistance under sufficient laser energy, special consideration should be made of the silicide with uniform composition at the equilibrium phase before the

10 20 30 40 50 60 70 80 10-2 10-1 100 101 Flow-1 Flow-3 Silicide thickness (nm) Stress (Gpa )

Fig. 5. The stress and silicide thickness correlations. Different 1st RTA conditions (300 °C, 350 °C and 400 °C, all for 15 s) were used to obtain different silicide thickness for the flow-1 and different PLA energy density (0.6 J/cm2

,1.5 J/cm2 and 2.3 J/cm2

) were used to obtain different silicide thickness for the flow-3.

-2 -1 0 1 2 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 n=1.28 Φbo=0.68 eV

Diode current (A)

Vd (V) Vd (V) Flow-3 Flow-1 n=1.6 Φbo=0.52 eV

(a)

2.0 2.5 3.0 3.5 4.0 -40 -32 -24 -16

(b)

Φbo =0.72 eV Φbo =0.54 eV ln ( Irev /T 2 )( A/K 2 ) 1000/T (K-1) Flow-3 Flow-1 -2 -1 0 1 2 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2

Diode current (A)

Flow-3 Flow-1 () ( ) ( )

(c)

Fig. 6. (a) The highly rectifying p-Si substrate diode of flow-3 with laser energy density equal to 1.5 J/cm2

indicates SBH increased for hole. (b) The Arrhenius plot of reverse-biased (Vd= 0.5 V) diode current for SBH extraction. (c) A ohmic-like I–V characteristic of flow-3 with n-Si substrate which indicate the SBH reduced for electron.

-1 0 1 2 3 10-10 10-9 10-8 10-7 10-6 10-5 10-4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Ideality factor Irev Irev (A) Laser power (J/cm2) Ideality factor I

Fig. 7. The reverse-biased (Vd= 0.5 V) diode current and the diode ideality factor of different laser energy densities. The different energy densities are obtained by changing the laser power from 0.7 W to 2.6 W. Inset shows the TEM cross-section view of sample with laser energy density increase to 2.3 J/cm.

10nm Si NiSi

(a)

(a)

10nm Si 50nm

(c)

NiSi NiSi

(b)

100nm 2 50nm

(a)

NiSi NiSi2

Fig. 4. Cross-sectional TEM images of (a) the flow-1 (two-step RTA) sample. (b) Flow-2 sample with 0.6 J/cm2

laser annealing. (c) Flow-3 sample with 0.6 J/cm2 laser annealing.

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PLA to improve the microstructure of both the interface and the bulk region of silicide.

4. Conclusion

In summary, this study demonstrates an enhancement of the nickel silicide tensile strain model and a new approach to SBH modulation by replacing the conventional second RTA of a two-step annealing process with pulsed laser annealing. The improved silicide interface morphology, combined with SBH modulation, re-duces the interfacial resistance without sacrificing junction leakage and makes this approach attractive for improving ultra-scaled de-vice performance.

Acknowledgement

This work was performed by NDL facilities and supported by the National Science Council, Taiwan.

Reference

[1] R.T. Tung, A.F.J. Levi, J.P. Sullivan, F. Schrey, Phys. Rev. Lett. 66 (1991) 72. [2] K.C.R. Chiu, J.M. Poate, J.E. Rowe, T.T. Sheng, A.G. Cull, Appl. Phys. Lett. 38

(1981) 988.

[4] G. Eneman, P. Verheyen, A. De Keersgieter, M. Jurczak, K. De Meyer, IEEE Trans. Elect. Devices 54 (2007) 1446.

[5] D.W. Lin, M. Wang, M.L. Cheng, Y.M. Sheu, B. Tarng, C.M. Chu, C.W. Nieh, C.P. Lo, W.C. Tsai, R. Lin, S.W. Wang, K.L. Cheng, C.M. Wu, M.T. Lei, C.C. Wu, C.H. Diaz, M.J. Chen, IEEE Elect. Device Lett. 29 (2008) 998.

[6] H. Fukutome, K. Kawamura, H. Ohta, K. Hosaka, T. Sakoda, Y. Morisaki, Y. Momiyama, IEEE VLSI Technol. Symp. Tech. Digest (2008) 150.

[7] W.L. Tan, K.L. Pey, S.Y.M. Chooi, J.H. Ye, T. Osipowicz, J. Appl. Phys. 91 (2002) 2901.

[8] M.G. Grimaldi, F. Priolo, P. Baeri, E. Rimini, Phys. Rev. B 35 (1987) 5117. [9] R.T. Tung, Mater. Sci. Eng. R 35 (2001) 1.

[10] J.P. Sullivan, R.T. Tung, F. Schrey, W.R. Graham, J. Vac. Sci. Technol. A 10 (1992) 1959.

[11] W.Y. Loh, P.Y. Hung, B.E. Coss, P. Kalra, I. Ok, G. Smith, C.Y. Kang, S.H. Lee, J. Oh, B. Sassman, P. Majhi, P. Kirsch, H.H. Tseng, R. Jammy, IEEE VLSI Technol. Symp. Tech. Digest (2009) 100.

數據

Fig. 1. Three different annealing process flow chart for silicidation evaluation.
Fig. 4. Cross-sectional TEM images of (a) the flow-1 (two-step RTA) sample. (b) Flow-2 sample with 0.6 J/cm 2

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