High-Performance RSD Poly-Si TFTs With
a New ONO Gate Dielectric
Kow-Ming Chang, Member, IEEE, Wen-Chih Yang, and Bing-Fang Hung
Abstract—This paper developed a novel polycrystalline silicon
(poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide–nitride–oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger BD, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabri-cated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm2 V s, and an on/off current ratio exceeding108.
Index Terms—Gate dielectric, N2O-plasma oxynitride, oxide–ni-tride–oxide (ONO), raised source/drain (RSD), thin-film transis-tors (TFTs).
I. INTRODUCTION
L
OW-TEMPERATURE poly-Si thin-film transistors (LTPS TFTs) offer potential for fabricating flat panel display (FPD) with integrated system on glass [1]. In realizing large-area active matrix liquid crystal displays with integrated peripheral poly-Si TFT driving circuits on the glass substrate, gate insulator quality, and field-effect mobility are two of the most important determinants of LTPS TFTs performance and reliability [2]. However, traditional TFTs use single-layer, plasma-enhanced chemical vapor deposition (PECVD), SiO or Si N as the gate insulator and so suffer from the high interface trap density, low breakdown strength, and high gate leakage current [3], [4]. In 1984, Watanabe et al. first reported silicon oxide–nitride–oxide (ONO) films as alternative dielectrics for DRAM cell capacitors [5]. In 1995, C. K. Yanget al. used ONO film as a gate insulator in high-temperature
TFTs [6]. In ONO multilayer structures, the bottom oxide provides a device-quality electrical SiO Si interface. The nitride layer increases the effective dielectric constant of the ONO sandwich in such a way that a film twice as thick as SiO -based dielectric shows equal capacitance, and therefore decreased threshold voltage, decreased subthreshold swing, and increased drive current of the poly-Si TFTs. Finally, the
Manuscript received August 26, 2003; revised December 8, 2003. This work was supported by the the National Science Council of Taiwan, R.O.C., under Contract NSC-90-2215-E-009-014. The review of this paper was arranged by Editor T. Skotnicki.
The authors are with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: kmchang@cc.nctu.edu.tw; wzyang.ee89g@nctu.edu.tw).
Digital Object Identifier 10.1109/TED.2004.827382
top oxide provides the electrical contact to the poly-Si gate electrode [7]. Although ONO structures exploit concomitantly the advantages of oxide and nitride films, ONO films are prepared by thermal growth in an low-pressure chemical vapor deposition (LPCVD) reactor at high temperature C ; this method is not appropriate for fabricating LTPS TFTs at a temperature much higher than a strain point of the glass substrate. Hence, this study presents a new low-temperature C PECVD oxide–nitride–N O-plasma-oxynitride multilayer gate dielectric for fabricating high performance LTPS TFTs. PECVD SiO Si N stack dielectric has been found to have lower leakage current and much longer (by 2–3 orders of magnitude) time dependent dielectric breakdown (TDDB) life time than single-layer PECVD tetraethooxysilane (TEOS) oxide or Si N dielectrics [8], [9]. Furthermore, our previous works reported that N O-plasma oxide shows strong Si N bonds, excellent breakdown characteristic, and a smooth surface at the oxynitride/poly-Si interface [10]. Therefore, the proposed new PECVD ONO gate dielectric was expected to provide high quality interface properties, increased electric breakdown voltage, and improved reliability for LTPS TFTs.
Besides being a high-quality gate insulator, high field-effect mobility also significantly influences device performance. The excimer laser annealing (ELA) method has been widely used to obtained high field effect mobility of low temperature polycrys-talline TFTs [11]. However, large off-state leakage current, poor poly-Si uniformity, and poor electrical stability of ELA poly-Si TFTs due to trap states in poly-Si grain boundaries and at the SiO /poly-Si interface are still serious problems. One method of alleviating these problems is to adopt a recessed channel structure [12], [13]. However, the polysilicon gate in recessed channel structure is not self-aligned to the recessed region, and the devices may have asymmetric characteristics. Therefore, it has been experimentally demonstrated that self-aligned raised source/drain (RSD) structure can provide a significantly im-provement in current drive, low series resistance, and a steeper subthreshold slope [14]–[16]. The thick source/drain (S/D) re-gion is the most promising method of decreasing the series resis-tance effectively and further improving the device performance. Previously, some researchers described RSD structures using local oxidation of silicon (LOCOS), selective epitaxy growth (SEG), in situ-doped LPCVD polycrystalline silicon, or poly de-position [12], [17]–[21]. LOCOS introduces large bird’s beak, furthermore, the S/D is not self-aligned to the gate in that struc-ture. Selective epitaxy in the source and drain regions is an at-tractive solution to solve this problem. However, the concerns of SEG are poor selectivity between silicon and oxide, facet forma-tion at the gate edge, and defects caused by in situ dopant. The
Fig. 1. Schematic cross-sectional view of key process steps for self-aligned RSD poly-Si TFT device with ONO stack gate dielectric.
advantage of in situ doped poly-Si and poly RSD is their in-dependence of the original poly-Si layer, which makes it more flexible in the process integration. Therefore, this investigation uses a different process to form poly-Si RSD structure that was achieved by using RIE to etch poly-Si to form thick S/D regions without additional polysilicon deposition or selective epitaxial growth process. The experimental data show that the LTPS TFT with RSD structure has a higher on current and larger on/off current ratio than conventional TFT. Therefore, the motivation of this work has two aims. First, this paper developed a new low-temperature Oxide/Nitride/N O-plasma Oxynitride (ONO) gate dielectric for LTPS TFT to promote breakdown voltage, re-duce leakage current, and enhance reliability. Second, the drive current and on/off current ratio of LTPS TFTs could be further promoted by using RSD structure.
II. DEVICEFABRICATION
The schematics of key processes for fabricating the RSD-TFT devices with ONO gate dielectric are illustrated in Fig. 1. At first, amorphous silicon (a-Si) films with a thickness of 150 nm were deposited on thermally oxidized Si wafers by LPCVD at 550 C with as the gaseous source. The experimental con-ditions are given in [22]–[24]. The amorphous silicon layer then was defined as the active islands. After active islands formation, the S/D region of amorphous silicon active islands were pat-terned and then anisotropically etched using reactive ion etching (RIE) to form a thin 50-nm active channel region and a thick
performed at 300 C substrate heating, plasma pressure 100 mtorr, and 200 W of RF power for 1 min to grow a 3-nm-thick oxynitride. Thereafter, a 40-nm-thick PECVD Si N and 7-nm-thick TEOS oxide was continuously deposited in situ on the thin oxynitride film. Then, polysilicon gate was formed on the thin active channel region. Subsequently, a 200-nm-thick poly-Si was deposited and patterned to form the gate electrode. Also, the gate electrode and S/D regions were implanted by phospho-rous ions at a dose of cm , and energy of 40 keV. In order to reduce the extra parasitic capacitance between gate and S/D, the sidewall ONO gate dielectric in Fig. 1(c) was re-moved by wet etching. Post-implantation ELA then was applied to activate the dopant and anneal the amorphized S/D region sil-icon layer. After depositing a 400-nm PECVD TEOS interlayer oxide, contact holes were defined and opened by photolithog-raphy and wet etching. Finally, 500 nm Al was deposited and patterned to provide an electrode pad. Al sintering was then car-ried out at 400 C for 30 min. The RSD-TFT with ONO gate dielectrics devices were fabricated without any hydrogenation plasma passivation treatment.
III. RESULTSAND DISCUSSION
A. Electrical Characteristics of ONO Gate Dielectric
First, stacked type n poly/dielectric/poly-Si capacitors were prepared to examine the electrical characteristics of ONO, TEOS oxide, and Si N dielectrics. For comparing ONO gate dielectric quality, the control samples were comprised of physical thickness 50-nm-thick PECVD TEOS oxide or Si N were not treated with N O-plasma [3], [8]. Fig. 2. shows the current density versus electric field ( – ) characteristics of TEOS oxide, Si N , and ONO gate dielectric films. The – characteristics of TEOS, Si N , and ONO dielectrics were measured by grounding the source and drain of the TFTs and applying a gate bias that swept from 0 to 50 V. Obviously, The breakdown field of ONO stack gate dielectric is larger than that of PECVD TEOS oxide to the value of about 3 MV/cm. The ONO dielectric film had a very high electric breakdown field of 9.4 MV/cm and a much lower leakage current than PECVD TEOS oxide and Si N films. This phenomenon is attributed to two reasons: First, the thin bottom-layer of N O-plasma oxyni-tride with high interface quality resulting in a smooth surface and strong Si bonds at the oxynitride/poly-Si interface [25], [26]. Second, in the nitride film, electrons are trapped and drift toward the top oxide by the Poole–Frenkel conduction
Fig. 2. Current density versus electric field (J–E) characteristics of the gate dielectric films for the conventional TEOS oxide, PECVD Si N and proposed ONO stack gate dielectric.
Fig. 3. Weibull plot of time-to-breakdown distribution obtained from constant voltage stress test for MOS devices with 500-nm gate dielectric thickness. Dielectric breakdown characteristics of the ONO film is dramatically improved, compared with those of PECVD TEOS and Si N films.
[27]. The electrons reaching the top oxide may tunnel though it to be collected by the gate. Tunneling though the oxide depends on the oxide thickness and the applied electric field or voltage. The as-fabricated top-layer 7-nm-thick TEOS oxide has a sufficient barrier height to suppress the Poole–Frenkel leakage current. Therefore, the top and bottom oxides of the ONO gate dielectric play very important roles in the reduction of a leakage current. Fig. 3. presents the Weibull plot of TDDB distribution of the TEOS, Si N , and ONO films under constant voltage stress test. It is worth mentioning that the TDDB lifetime of the ONO film is about 1–2 orders of magnitude remarkably im-proved compared with those of the TEOS oxide and the Si N dielectrics. The improvement of the electrical reliability of the ONO film is believed to be related to the PECVD N O-plasma effectively repairs defects in the oxynitride and poly-Si film, such as Si dangling bonds. Moreover, it is also considered that the accumulation of nitrogen at the oxynitride/poly-Si interface
Fig. 4. Weibull plots of charge-to-breakdown for TEOS, Si N , and ONO stack gate dielectric under positive constant current stress of 100A/cm . The capacitor area was1 2 10 cm .
Fig. 5. Measured gate–voltage shift,1V , of MOS capacitors for the TEOS, Si N , and ONO films under the constant-current stress condition with current density of 100A/cm . 1V for the ONO film by carrier-trapping is smaller compared with that for TEOS oxide or Si N film.
is one reason for the high electrical reliability [10], [26]. Fig. 4. shows charge-to-breakdown cumulative distributions of TEOS, Si N , and ONO films under positive constant current stress of A/cm . The physical thickness 50-nm-thick ONO stack gate dielectric has up to 0.91 C/cm . The value is much larger than that of PECVD TEOS and Si N to the values of 0.021 and 0.068 C/cm . Fig. 5. shows the charge-trapping characteristics of TEOS, Si N , and ONO films under a constant current stress. The gate voltage shifts, , is smaller for the ONO film than for TEOS and Si N . The lower electron-trapping rate of ONO dielectric implies that the N O-plasma formed a smooth surface at oxynitride/poly-Si interface, which provides fewer trap sites and a lower current density with a lower electron-trapping rate [28].
To examine the roughness of the interface between N O-plasma oxynitride and poly-Si layer, the surface
rough-Fig. 6. AFM images of KrF laser annealed poly-Si films. (a) Poly-Si surface before oxidation. The rms roughness of the surface was measured to 4.53 nm. (b) Poly-Si surface after ONO dielectric deposition. The rms roughness was measured to 3.69 nm. (c) Poly-Si surface after PECVD TEOS oxide and Si N deposition. The rms roughness was measured to 4.47 and 4.51 nm, respectively.
ness was measured using atomic force microscopy (AFM). Fig. 6. shows the AFM images of the KrF laser annealed poly-Si films. Before AFM measurements, grown dielectrics were completely removed in 50:1 HF solution. The root mean square (rms) roughness of poly-Si surface before oxidation was measured as being 4.53 nm. The rms roughness of poly-Si surface after ONO dielectric deposition then was reduced to 3.69 nm and the rms roughness of poly-Si surface after PECVD TEOS or Si N deposition were almost the same as the original poly-Si surface, namely 4.47 and 4.51 nm, respectively. The poly-Si surface of ONO gate dielectric was significantly smoother than that of PECVD TEOS oxide and Si N . Apparently, the roughness existing at TEOS or Si N -poly-Si interface thus provides various trap sites and lead to a higher current density with higher electron-trapping rate, thus causing smaller values. These analytical results confirm that larger electron conduction and electron trapping characteristics of PECVD TEOS oxide and Si N compared to ONO gate dielectric are due to larger polysilicon surface roughness and poor quality dielectric film.
B. Electrical Characteristics of RSD-TFT With ONO Gate Dielectric
Conventional poly-Si TFTs with channel thickness of 50-nm-thick and TEOS, Si N or ONO gate dielectrics were fabricated for comparing device performance. Typical transfer characteristics of conventional poly-Si TFTs with TEOS, Si N or ONO gate dielectrics are shown in Fig. 7. Conventional poly-Si TFTs with TEOS oxide have maximum field effect mobility of 84.5 cm V s, a minimal leakage current of 5.1 pA, and an on/off current ratio of . The poly-Si TFTs with new ONO gate dielectric (ONO-TFT) have greatly improved field-effect mobility and on/off current ratio: the electron mo-bility increased from 84.5 to 213.8 cm V s, minimal leakage current decreased from 5.1 pA to 1.7 pA, and the current ratio
increased from to . The improvement of
ONO-TFT was attributed to the reduction of interface traps and the formation of a smooth surface at the oxynitride/poly-Si interface by N O-plasma oxide. Therefore, the combination of PECVD N O-plasma oxynitride, Si N and TEOS oxide successfully promoted the breakdown field of gate dielectric
Fig. 7. Transfer characteristics of conventional poly-Si TFTs with ONO multilayer gate dielectrics were measured atV = 1 V for drain current I andV = 0:1 V for field-effect mobility .
Fig. 8. Transfer characteristic of RSD-TFT and conventional TFT with ONO gate dielectric.
and improved the electrical characteristics of LTPS TFTs, because N O-plasma oxidation incorporates nitrogen atoms at the SiO /poly-Si interface, forming a nitrogen-rich layer with Si N bonds. Additionally, high dielectric constant Si N film in the middle layer offers high capacitance to increase drive current, and the top-oxide constitutes an electrical contact to the poly-Si gate electrode and suppresses the Poole–Frenkel leakage current from the Si N film.
Fig. 8 shows the transfer characteristics of RSD-TFT and con-ventional TFT (ONO-TFT) with ONO stack gate dielectric. The RSD-TFT with ONO stack gate dielectric with channel thick-ness of 50 nm, and an RSD region thickthick-ness of 150 nm, showed a 120% increase in on-current, a 50% increase in peak mobility (320 cm V s), and a 62% decrease in off-current at
V, compared with conventional TFT devices with the same channel thickness and ONO gate dielectric. Table I summa-rizes the performance parameters of fabricated RSD-TFT and ONO-TFT devices. The RSD-TFT exhibited better electrical characteristics than the conventional ONO-TFT. Because lat-eral thermal gradient could arise because of the heat generated
TABLE I
SUMMARY OF THEELECTRICALCHARACTERISTICSPARAMETERS OF
FABRICATEDRSD-TFTS ANDONO-TFTSWITHHIGH-QUALITY
ONO GATEDIELECTRIC
Fig. 9. I –V output characteristics of RSD-TFT and conventional TFT with ONO gate dielectric.
at the moving solid-melt interface during ELA crystallization process, resulting large longitudinal grains could be grown in the thin channel regions accompanied with thick S/D region for reducing series resistance [29]. Fig. 9 shows the – output characteristics for both RSD-TFT and conventional TFT with ONO stack gate dielectric. Better drive current and steeper linear region revealed that the RSD-TFT had less S/D series resistance than conventional TFT. The current drivability is improved due to the formation of low-resistivity RSD structure in RSD-TFT. The RSD-TFT device had a measured low S/D sheet resistance of 620 sq was smaller than that of 1.6 k sq of conventional TFT with same channel thickness and without RSD structure. It also can be seen that for the conventional ONO-TFT, the cur-rent–voltage curves behave more like resistance with increasing gate voltage. This phenomenon occurs because for larger gate bias, the channel resistance becomes smaller, hence, the dom-inant resistance comes from the source and drain region. The output current is subject to be limited by the source and drain resistance. Therefore, the output current of RSD-TFT is much larger than that of the conventional ONO-TFT because of its thick S/D region.
Finally, the drive current of TFT devices is known to be af-fected by:
1) presence of grain boundaries in the channel region; 2) series resistance in the S/D regions;
3) thick gate dielectric;
4) defect states in the channel and at the SiO Si interface [30], [31].
a self-aligned RSD structure and high-quality ONO gate di-electric. The proposed ONO gate dielectric has superior dielec-tric properties to the conventional PECVD oxide and nitride films. Furthermore, this study applied this ONO gate dielec-tric to RSD-TFT to promote device performance. The RSD-TFT with ONO gate dielectric exhibits excellent electrical character-istics, with a field effect mobility of up to 320 cm V s, and high current drivability. These improvements are related to the high interface quality of the bottom N O-plasma oxynitride film, the leakage current reduction by the combined effect of the TEOS oxide/Si N films, and the low-resistivity thick source/drain re-gion.
REFERENCES
[1] K. Chung, M. P. Hong, C. W. Kim, and I. Kang, “Needs and solutions of future flat panel display for information technology industry,” in IEDM
Tech. Dig., 2002, pp. 385–388.
[2] K. C. Moon, J.-H. Lee, and M.-K. Han, “Improvement of polycrys-talline silicon thin film transistor using oxygen plasma pretreatment be-fore laser crystallizarion,” IEEE Trans. Electron Devices, vol. 49, pp. 1319–1322, July 2002.
[3] Y. Ikeda, K. Kishimoto, K. Hirose, and Y. Numasawa, “TOP-PECVD: Anew conformal plasma enhanced CVD technology using TEOS, ozone and pulse-modulated RF plasma,” in IEDM Tech. Dig., 1992, pp. 289–292.
[4] S. Lim, S. J. Kim, J. H. Jung, B. K. Ju, M. H. Oh, and J. F. Wager, “High quality silicon-nitride thin films grown by helium plasma-en-hanced chemical vapor deposition,” in Proc. Vacuum Microelectronics
Conf., 1996, pp. 406–410.
[5] T. Watanabe, A. Menjoh, M. Ishikawa, and J. Kumagai, “Stacked SiO =Si N =SiO dielectric layer for reliable memory capacitor,” in
IEDM Tech. Dig., 1984, pp. 173–176.
[6] C. K. Yang, C. L. Lee, and T. F. Lei, “EnhancedH -plasma effects on polysilicon thin-film transistors with thin ONO gate dielectrics,” IEEE
Electron Device Lett., vol. 16, pp. 228–229, Mar. 1999.
[7] W. Ting, S. N. Lin, and D. L. Kwong, “Thin stacked oxide/nitride/oxide dielectrics formation by in situ multiple reactive rapid thermal pro-cessing,” Appl. Phys. Lett., vol. 55, pp. 2313–2315, 1989.
[8] N. Ibaraki, T. Shimano, K. Fukuda, and K. Matsumura, “A new a-Si TFT with SiO =SiNx gate insulator for 10.4-inch LCDs,” in IEDM Tech.
Dig., 1990, pp. 97–100.
[9] L. Pichon, F. Raoult, and O. Bonnaud, “Comparison of the low-tempera-ture( 600 C) polysilicon thin-film transistors (TFTs) with two kinds of gate dielectrics,” Mater. Chem. Phys., vol. 39, pp. 313–316, 1995. [10] K.-M. Chang, W.-C. Yang, and C.-P. Tsai, “Electrical characteristics of
low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric,” IEEE Electron Device Lett., vol. 24, pp. 512–514, Aug. 2003.
[11] D. H. Choi, E. Sadayuki, O. Sugiura, and M. Matsumura, “Excimer-laser crystallized poly-Si TFTs with mobility of more than 600 cm =V 1 s,”
IEEE Trans. Electron Devices, vol. 40, pp. 2129–2130, Nov. 1993.
Chang, and P.-T. Liu, “Polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain,” Appl. Phys. Lett., vol. 81, pp. 4763–4765, Dec. 2002.
[17] J. M. Hwang, R. Wise, E. Yee, T. Houston, and G. P. Pollack, “Ultra-thin film SOI/CMOS with selective-epi source/drain for low series re-sistance, high drive current,” in Symp. VLSI Tech. Dig., 1994, pp. 33–34. [18] A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima, and Y. Toyoshima, “Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique,” in IEDM Tech. Dig., 2000, pp. 243–246.
[19] L. Pichon, F. Raoult, O. Bonnaud, H. Sehil, and D. Briand, “Conduction behavior of low-temperature( 600 C) polysilicon TFTs with an in
situ drain doping level,” Solid State Electron., vol. 38, pp. 1515–1521,
1995.
[20] L. Pichon, F. Raoult, K. Mourgues, K. Kis-Sion, T. Mohammed-Brahim, and O. Bonnaud, “Low temperature( 600 C) unhydrogenated in situ doped polysilicon thin film transistors: toward a technology for flat panel displays,” Thin Solid Films, vol. 296, pp. 133–136, 1997.
[21] C. Yin, V. W. C. Chan, and P. C. H. Chan, “Low S/D resistance FDSOI MOSFETs using polysilicon and CMP,” in IEDM Tech. Dig., 2001, pp. 89–92.
[22] G. Harbeke, L. Krausbauer, E. F. Steigmeier, A. E. Widmer, H. F. Kappert, and G. Neugebauer, “High quality polysilicon by amorphous low pressure chemical vapor deposition,” Appl. Phys. Lett., vol. 42, pp. 249–251, 1983.
[23] P. Joubert, B. Loisel, Y. Chouan, and L. Haji, “The effect of low pres-sure on the structure of LPCVD polycrystalline silicon films,” J.
Elec-trochem. Soc., vol. 134, pp. 2541–2544, 1987.
[24] M. Sarret, A. Liba, B. Fortin, F. Le Bihan, L. Pichon, and O. Bonnaud, “In situ phosphorous doped VLPCVD poly-Si layers for polysilicon thin film transistors,” in Proc. Int. Elec. Eng., Poly-Si Devices and
Applica-tions Conf., 1993, pp. 10/1–10/4.
[25] E. Ibok, K. Ahmed, M.-Y. Hao, B. Ogle, J. J. Wortman, and J. R. Hauser, “Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics,” IEEE Electron Device Lett., vol. 20, pp. 442–444, June 1999.
[26] J. W. Lee, N. I. Lee, S. H. Hur, and C. H. Han, “Oxidation of silicon using electron cyclotron resonance nitrous oxide plasma and its application to polycrystalline silicon thin film transistors,” J. Electrochem. Soc., vol. 144, pp. 3228–3232, 1997.
[27] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1985.
[28] S. Han and H. Shin, “Ultrathin oxide grown on polysilicon by ECR (electron cyclotron resonance) N O plasma,” in Proc. IEEE Plasma
Process-Induced Damage Conf., 2000, pp. 133–136.
[29] M. Lee, S.Seungjae Moon, M. Hatano, K. Suzuki, and C. P. Grig-oropoulos, “Relationship between fluence gradient and lateral grain growth in spatially controlled excimer laser crystallization of amor-phous silicon films,” J. Appl. Phys., vol. 88, pp. 4994–4999, Nov. 2000. [30] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K.Yang-Kyu Choi, K. Asano, V. Subra-manian, T.-J.Tsu-Jae King, J. Bokor, and C.Chenming Hu, “Sub 50-nm FinFET: PMOS,” in IEDM Tech. Dig., 1999, pp. 67–70.
[31] V. Subramanian and K. C. Saraswat, “High-performance germanium-seeded laterally crystallized TFTs for vertical device integration,” IEEE
Kow-Ming Chang (M’00) was born in Taiwan,
R.O.C., on July 1, 1954. He received the B.S. degree (with highest honors) from the National Central University, Chungli, Taiwan, in 1977 and the M.S. and Ph.D. degrees from the University of Florida, Gainesville, in 1981 and 1985, respectively, where his doctoral research concerned the processing technologies of compound semiconductors.
From 1985 to 1989, he was an Associate Professor, and in 1989, became a Professor in the Department of Electronics Engineering, National Chiao-Tung Uni-versity (NCTU), Hsinchu, Taiwan. From 1989 to 1990, he was a Visiting Pro-fessor with the Electrical Engineer Department, University of California, Los Angeles, where he was engaged in research on the system design of electron cyclotron resonance chemical vapor deposition (ECR-CVD) for developing the low-temperature processing technology. He was in charge of a 500-KeV ion im-planter, a selective tungsten LPCVD system, and two UHV-ECR-CVD systems. His research interests are in the physics, technologies and modeling of hetero-junction devices and optoelectronics devices, ULSI key technologies, CMOS devices, and MEMS technologies. He has published over 150 articles in these fields and served as Reviewer for international journals such as the Journal of
Electrochemical Society.
Dr. Chang is a member of the American Institute of Chemical Engineering, Electrochemical Society, IEEE Electron Devices Society, Chinese Society for Electrical Engineering, and Phi Tau Phi. He has served as a Reviewer for the IEEE ELECTRONDEVICELETTERS.
Wen-Chih Yang was born in Chunghua, Taiwan,
R.O.C., in 1975. He received the B.S. degree in electrical engineering from National Central University, Chungli, Taiwan, in 1998 and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 2000, where he is currently pursuing the Ph.D. degree.
His current research interests are in the fabrication of the low-temperature polysilicon thin-film tran-sistors, low-temperature polyoxide, ultrathin gate-oxide, and ULSI key technologies.
Bing-Fang Hung was born in Kaohsiung, Taiwan, R.O.C., in 1978. He
re-ceived the B.S. degree in electrical engineering, National Tsing Hua University, Hsinchu, Taiwan, in 2001 and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, in 2003, where he is currently pur-suing the Ph.D. degree.
His current research interest is in the low-temperature polysilicon thin-film transistors and low-temperature polyoxide.
