CMOS low dropout linear regulator with
single Miller capacitor
W.-J. Huang, S.-H. Lu and S.-I. Liu
A 2–5 V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4 pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 mm CMOS process and the active chip area is 485 586 mm. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.
Introduction: Integrated low dropout (LDO) linear regulators[1–4]are widely used in portable battery-operated electronic devices such as mobile phones and PDAs. The required regulator has to have low static power and low noise, a small active area, a small dip at the output voltage and a fast transient response. To have the appropriate open-loop gain in deep submicron-metre CMOS process, the LDO linear regulator is realised by a multi-stage amplifier which needs complex frequency compensation[3, 5]. In general, there are two or three Miller capacitors in an LDO linear regulator, which is a three-stage amplifier. To guarantee the stability for the heavy and light current loads, tens-pF Miller capacitors have to be used. However, dips of the output voltage and the transient response time of an LDO linear regulator are dependent on the bandwidth. In this Letter, a bandwidth extension method using only a single Miller frequency compensation capacitor of 4 pF is presented and the dips of the output voltage are also reduced.
Fig. 1 Proposed LDO regulator
Circuit description: Fig. 1shows the proposed LDO linear regulator (the bandgap voltage reference is not shown). This regulator is composed of three gain stages and a current follower (CF). The CF is composed of Mc1–Mc5 and Ma1–Ma3, which is inserted between the output of the first stage and the Miller compensation capacitor, Cm. This technique is similar to the common-gate frequency compen-sation method[6]. To analyse the stability of the proposed LDO linear regulator, the loop-gain frequency responses should be investigated. gm1, gm2and gmpare the transconductance of the first, second and the output stage, respectively. gmais the transconductance of the transistor Ma1. 1=go1and 1=go2are the output parasitic resistance of the first and second stage, respectively. Cp1and Cgare the lumped output parasitic capacitance of the first and second stage. Resr is the equivalent series resistance (ESR) of Coutand gmfis the transconduc-tance of the transistor Mf. 1=gout( ¼ RL==Ropass==(RF1þRF2)) is the equivalent open-loop output resistance of the LDO linear regulator where RLis the load resistance, Ropassis the output resistance of the power transistor, Mp, and RF1and RF2are the feedback resistors.
Assume Cout(Cm, Caand Cg) Cp1, gmp(gm1, gmf, gm2), and gm1=go11 and gm2=go21. The small-signal transfer function of the LDO linear regulator in the heavy load (Iloadis large) is given as
LhlðsÞ ¼ Ao½1 þ sðCm=gmaÞ ½1 þ sðgmfCp1=gm2gm1Þ ½1 þ ðs=jp3 dB heavy loadjÞ ½1 þ sðCgCp1=Cmgm2gmpResrÞ þs2ðC gCp1=gm2gmpgmaResrÞ ð1Þ
where Ao¼(RF1=(RF1þRF2))gm1gm2gmp=(go1go2gout) is the DC loop gain and p3 dB_heavy_load¼ go1go2gout=Cmgm2gmp is the dominant pole of the LDO linear regulator in the heavy load. The second non-dominant pole is much larger than the first one, which is in the order of MHz. The second-order polynomial in the denominator is decomposed into [1 þ s(CgCp1=Cmgm2gmpResr)][1 þ s(Cm=gma)]. Then, (1) is rewritten as
LhlðsÞ ’
Ao½1 þ sðgmfCp1=gm2gm1Þ
½1 þ ðs=jp3 dB heavy loadjÞ½1 þ sðCgCp1=Cmgm2gmpResrÞ ð2Þ Therefore, a smaller Miller compensation capacitor is used to extend the bandwidth in the heavy load.
Two cases are considered for the LDO operating in the light load (Iloadis small) with small and large ESRs, respectively. As a small ESR is used, the transfer function for the light load is given as
LllðsÞ ¼
Aoð1 þ sCoutResrÞ½1 þ sðCm=gmaÞ ½1 þ sðgmfCp1=gm2gm1Þ f1 þ s½ðCmgm2gmp=goutgo1go2Þ þ ðCout=goutÞg
f1 þ s½½ðCg=CmÞðgo1=go2Þ þ ðCp1=CmÞ Coutgo2=½ gm2gmpþ ðCout=CmÞgo1go2Þ þs2½C outCgCp1=ðCmgm2gmpþCoutgo1go2Þ þs3½C mCoutCgCp1=gmaðCmgm2gmpþCoutgo1go2Þg ð3Þ From (3), if the second dominant pole is apart from the first non-dominant pole, they are given as
Pnd1 ll lowESR’ gm2gmpþ ðCout=CmÞgo1go2 ½ðCg=CmÞðgo1=go2Þ þ ðCp1=CmÞCoutgo2 and Pnd2 lowESR’ go1 Cp1 þgo2 Cg ð4Þ
However, as Cmis decreased, the dominant pole increases and the first non-dominant pole decreases, and then the phase margin is decreased. Therefore, the minimum Miller compensation capacitor is needed to have an appropriate phase margin in the light load with a small ESR.
If a higher ESR output capacitor is used, the first and second non-dominant poles are given as
Pnd1 ll highESR’ gm2gmpþ ðCout=CmÞgo1go2 ½ðCg=CmÞðgo1=go2Þ þ ðCp1=CmÞ þðgm2gmp=go2ÞResrCoutgo2 and Pnd2 ll highESR’ go1 Cp1 þgo2 Cg þCmgm2gmpResr Cp1Cg ð5Þ
The first non-dominant pole is slightly decreased to a lower frequency and the second non-dominant pole is slightly increased to a higher frequency. Thus the complex poles are avoided for the light load with a large ESR, meaning the LDO regulator for the light load has a large ESR. In general, only a Miller capacitor of 4 pF is used to achieve stability for all the above analyses in our design.
Experimental results: This LDO regulator has been fabricated in a 0.35 mm CMOS process. The die photo is shown inFig. 2; the active area is 485 586 mm2. The maximum output current is 150 mA with a dropout voltage of 220 mV. RF1and RF2are 56 and 187 kO, respectively. The proposed LDO regulator with 1.8 Voutput operates from 2 to 5 V and its static power is 0.265 mW with 53 mA quiescent current (where the bandgap voltage reference consumes 26 mA) in a 5 V supply voltage. The measured line regulations at the load current Iload¼0 and Iload¼150 mA are 0.045 and 0.143%=V, respectively. The measured load regulation is 92.8 ppm=mA at 3.3 V.Fig. 3shows the measured transient responses of the LDO regulator at 3.3 V and the load current switching from 0 and 150 mA for the output capacitor of (Fig. 3a) Cout¼10 mF with ESR ¼ 0.8 O, (Fig. 3b) Cout¼1 mF with ESR ¼ 0.3 O and (Fig. 3c) Cout¼1 mF with ESR ¼ 1 O, respectively. The experimental results show that the proposed LDO can recover to the preset output voltage within 3.2 ms under Cout¼1 mF with ESR ¼ 0.3 O. In addition, the dips of the output voltage are reduced to 130 mVowing to the wide bandwidth of the proposed LDO linear regulator.
bandgap reference
Cm
1st stage, 2nd stage and current follower RF1, RF2
output stage
Fig. 2 Die photo
Fig. 3 Transient response of LDO regulator for Cout¼10 mF and ESR ¼ 0.8 O (Fig. 3a), Cout¼1 mF and ESR ¼ 0.3 O (Fig. 3b), Cout¼1 mF and ESR ¼ 1 O (Fig. 3c)
Vout: 50 mV=div., 1 ms=div.
Conclusion: A CMOS LDO linear regulator with a single Miller capacitor is presented. Experimental results confirmed that the dips and peaks of the output voltage are reduced simultaneously owing to the larger bandwidth. Moreover, the settling time is also reduced significantly.
Acknowledgment: The authors thank the National Chip Implementa-tion Center (CIC), Hsinchu, Taiwan, for chip implementaImplementa-tion.
#IEE 2006 20 November 2005
Electronics Letters online no: 20064062 doi: 10.1049/el:20064062
W.-J. Huang, S.-H. Lu and S.-I. Liu (Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, Republic of China) E-mail: lsi@cc.ee.ntu.edu.tw
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