Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

along the channel. An analytical flicker noise model to account

for a pocket doping effect is proposed. In our model, the local

threshold voltage and the width of the pocket implant region are

extracted from the measured reverse short-channel effect, and

the oxide trap density is extracted from a long-channel device.

Good agreement between our model and the measurement result

is obtained without other fitting parameters.

Index Terms—Flicker noise, modeling, nonuniform threshold

voltage, pocket implant.

I. I

T

HE CMOS technology, which possesses the advantage of

low cost, high integration, and low power, is finding more

and more important applications in the area of mixed mode

and RF ICs. As compared with bipolar transistors, CMOS

de-vices exhibit large noise, especially in the low-frequency region

where flicker noise is dominant [1]. Flicker noise will affect the

signal-to-noise ratio in operational amplifiers and in

analog/dig-ital and diganalog/dig-ital/analog converters. Phase noise of

voltage-trolled oscillators originating from flicker noise is another

con-cern for RF applications [2]. In order to reduce low-frequency

noise in analog devices, the physical origin of flicker noise in

today’s CMOS devices should be further explored.

Pocket implantation is necessary in CMOS process to reduce

the subthreshold leakage in logic devices. However, it has some

drawbacks in analog circuits, such as the increase of

drain-sub-strate coupling, poor Early voltage, lower high-frequency

output resistance [3] and increased nonlinearity [4]. Recent

study has shown that pocket implantation will also degrade

drain current flicker noise [3]–[7]. New MOSFET structures,

such as single pocket, asymmetric channel structure, [3], [5]

Manuscript received October 15, 2003; revised March 2, 2004. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contract NSC92-2215-E009-024 and in part by Taiwan Semiconductor Manu-facturing Company. The review of this paper was arranged by Editor M. J. Deen. J.-W. Wu, C.-C. Cheng, J.-C. Guo, and T. Wang are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

K.-L. Chiu is with United Microelectronics Corporation, Hsinchu 300, Taiwan, R.O.C.

W.-Y. Lien and C.-S. Chang are with the Taiwan Semiconductor Manufac-turing Company, Hsinchu 300, Taiwan, R.O.C.

G.-W. Huang is with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TED.2004.831369

additional oxide trap creation by pocket implantation [7], the

real cause of pocket implantation induced noise degradation

is still not clear. The purpose of this paper is to investigate

pocket implantation effect on flicker noise in nMOSFETs with

various pocket doses and device dimensions. An analytical

flicker noise model taking into account a pocket doping effect

will be proposed.

The input/output nMOSFETs of a 0.13- m CMOS

tech-nology is used in this work. The I/O devices have a 5.8-nm gate

oxide, a gate length from 0.22 to 10 m, and a gate width of 10

m. Two pocket implant doses were used. Due to the statistical

nature of the flicker noise, devices with too small an area may

exhibit a large fluctuation range in noise [8]. In this paper, each

noise measurement data point represents an average of three

to ten devices. The normalized noise power spectrum density

is chosen as a monitor of drain current noise, which

is considered to be a fair index because of the normalization

to the drain current. In addition, charge pumping measurement

is performed to characterize oxide (interface) trap density for

different pocket implant splits.

According to the unified flicker noise model [9], the

normal-ized noise power spectrum density

has the following

simple analytic form at very low drain voltages:

(1)

where

cm

is the attenuation coefficient of the

elec-tron wave function in the oxide [10],

is the scattering

coeffi-cient [11],

is the number of channel carriers per unit area,

and

is the oxide trap density at the Fermi level

.

The

term in the bracket represents charge number

fluc-tuation and the

term is from mobility fluctuation. For

nMOS-FETs at a low gate overdrive bias,

is smaller than

,

which means that the number fluctuation mechanism dominates

noise behavior.

II. M

R

D

Fig. 1 shows the diagram of an nMOSFET with pocket

implantation. Pocket implantation will cause nonuniform

threshold voltage distribution along the channel and may create

additional oxide traps

near the source/drain edge. According

Fig. 1. Diagram of pocket implant-induced nonuniform threshold voltage distribution along the channel. Regions 1 and 3 are the pocket implant-affected region and possess a higher threshold voltage. Region 2 represents the rest of the channel.

Fig. 2. Reverse SCE for low/high pocket doses.

to (1), both nonuniform

distribution and oxide trap creation

affect drain current flicker noise. Two pocket implant doses

are compared in this study. The higher pocket dose is about

2.2 times larger than the lower one. Fig. 2 shows the reverse

short-channel effect (RSCE) of nMOSFETs of the two doses.

As expected, the higher pocket implant dose shows a larger

RSCE. The short-channel effect (SCE) becomes dominant for a

gate length below 0.3 m. The measured noise behavior of these

two pocket implant splits is shown in Fig. 3. The comparison is

made at the same gate overdrive voltage (

–

). To avoid the

complication resulting from the SCE in the analysis of noise,

two gate lengths

and 10 m) in the RSCE regime

are used for study. The noise is measured in linear operation

regime

V) that the inversion charge is not affected by

the drain bias. The noise data point shown in Fig. 3 is obtained

at

Hz. For a long-channel device [

m,

Fig. 3(a)], the noise of the two different pocket split devices

is almost the same without regard to a considerably different

pocket dosage. Fig. 3(b) shows the noise in two shorter gate

length

m devices with the same pocket split.

The higher pocket dose device apparently exhibits much worse

noise behavior in the entire range of gate bias. Fig. 4 shows the

measured flicker noise versus gate length for the two pocket

dosages. The pocket implant-induced noise degradation is more

significant in a shorter gate length device because the pocket

implant region occupies a larger portion of the channel.

Fig. 3. Normalized noise power spectrum density versus gate overdrive voltage(V –V ) for low/high pocket doses. The noise is measured in the linear regime. (a) nMOS(W=L = 10=10 m), and all data points are averaged from three devices. (b) nMOS(W=L = 10=0:32 m), and all data points are averaged from ten devices.

Fig. 4. Normalized noise power spectrum density versus gate length for low/high pocket doses. The noise is measured at the same gate overdrive voltage.

Previous work attributed the severe noise degradation in a

pocket-implanted device to more oxide trap creation due to

pocket implant [12]. In order to clarify this point, we measured

the charge pumping current for the two pocket splits. Nearly

the same result is obtained in Fig. 5 with extracted interface

trap density about

cm . This implies that the

two implant splits yield almost the same trap density in gate

oxide. Thus, the more severe noise degradation in the higher

pocket dose device in Fig. 3(b) cannot be explained simply

by implant caused oxide trap creation. Rather, a nonuniform

threshold voltage distribution along the channel resulting from

pocket implant should be responsible for the observed noise

degradation. A simple analytic model is proposed to explain a

nonuniform threshold voltage effect on noise degradation.

III. N

M

I

P

I

In our model, the channel of an nMOSFET is divided into

three regions, as suggested in [13], [14]. Regions 1 and 3 in

Fig. 1 represent a pocket region, where the local threshold

voltage (

) is increased due to pocket implantation. Region 2

represents the rest of the channel and possesses a lower

. In

our model, the

is divided into three terms by introducing

the nonuniform

distribution into the

term. At a

rela-tively low gate overdrive bias, the mobility fluctuation term in

(1) can be neglected. In addition, since the oxide (interface)

trap density is not affected by pocket implantation process, a

uniform distribution of oxide trap density along the channel is

assumed. Based on these assumptions, (1) can be reduced to

(2)

where

and

represent conducting charge density in region

1 and region 3, which are modulated by pocket implant dosage.

In the long-channel devices

m , the noise

compo-nent arising from the pocket implantation regions is relatively

small. This argument is evident from Fig. 3(a) that the noise

is nearly the same for different pocket splits in long-channel

devices. In other words, the second term in (2), i.e.,

re-gion, is dominant in a long-channel device. From the measured

noise and threshold voltage in a long-channel device, the oxide

trap density

can be extracted. The result is shown in

Table I. The measured and calculated results of noise level in a

long-channel device are shown in Fig. 6. Good agreement

be-tween our model and measurement result is achieved in a low

Fig. 6. Comparison of calculated and measured noise results for nMOS with W=L = 10=10 m. (a) Low pocket dose. (b) High pocket dose.

gate overdrive voltage regime where the number fluctuation is

dominant.

For noise calculation in short-channel devices, the respective

parameters in the pocket region must be extracted first. The

ef-fective channel length is about

m, which

is evaluated from the shift and ratio method [15]. The width and

the local

of the pocket regions can be extracted from the

mea-sured RSCE by using the method in [16] and [17]. The extracted

parameters used in our model are given in Table I. The measured

and calculated results in 0.32 m devices are shown in Fig. 7.

No other fitting parameters are used.

It should be remarked that a small difference between

mod-eled and measured results is noticed in Figs. 6 and 7 at a higher

gate overdrive bias. The reason is that the mobility fluctuation

mechanism

plays a part in drain current noise at a high

gate overdrive bias.

Fig. 7. Comparison of calculated and measured noise results for nMOS with W=L = 10 m=0:32 m. (a) Low pocket dose. (b) High pocket dose.

IV. C

Pocket implantation effect on drain current flicker noise in

nMOSFETs is investigated. The result shows that nonuniform

threshold voltage distribution along the channel caused by

pocket implantation is responsible for flicker noise degradation

in a short-channel device. This effect will become more

signif-icant as channel length is further reduced. A simple analytical

noise model including pocket implantation effect for various

gate length devices has been developed and can be easily

implemented into a circuit simulator.

R

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Jun-Wei Wu (S’02) was born in Tao-Yuan, Taiwan,

R.O.C. He received the B.S. degree in electronics en-gineering, in 1998, from National Chiao-Tung Uni-versity, Hsinchu, Taiwan, where he is currently pur-suing the Ph.D. degree in electronics engineering.

His research interest includes RF CMOS device modeling, flicker noise characterization and mod-eling, and LDMOS power device modeling and reliability analysis.

Chih-Chang Cheng received the B.S. degree in

physics from National Central University, Taoyuan, Taiwan, R.O.C., in 2002. He is currently pursuing the Ph.D. degree in electronics engineering at the National Chiao-Tung University, Hsinchu, Taiwan.

His research interest includes high-voltage power devices and flicker noise.

Kai-Lin Chiu was born in Kaohsiung, Taiwan,

R.O.C. in 1978. He received the B.S. and M.S. degree, in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2001 and 2003, respectively.

In 2004, he joined United Microelectronics Cor-poration, Hsinchu, where he was engaged in the de-velopment and characterization of mixed-mode tech-nology. His research interests includes the reliability issues and analog performance of CMOS.

in ERSO/ITRI and working on the process simulation and device design for high-speed SRAM technology. From 1994 to 1998, she was with Macronix International Corporation where she was engaged in the high-density and low-power Flash memory technology development and led a team responsible for Flash memory device design and reliability analysis. In 1998, she joined Vanguard International Semiconductor Corporation, where she served as a De-partment Manager responsible for advanced DRAM device design with a major focus on 0.18–m 64-M DRAM development. In 2000, she joined Taiwan Semiconductor Manufacturing Company, where she served as a Program Man-ager in charge of 0.1-m logic CMOS FEOL technology development. Since 2001, she has been engaged in HPA and RF CMOS technology development, and led a team focusing on 0.13-m CMOS-based mixed-signal and RF device design. She has authored or coauthored around 30 technical papers and has been granted about ten international patents in her professional field. Her current research interests are RF CMOS and HPA device design and modeling, novel nonvolatile memory technology, and circuit technology for SoC.

Wai–Yi Lien was born in Taiwan, in 1963. He

received the Ph.D. degree in power mechanical engineering from National Tsing-Hua University, Hsinchu, Taiwan, R.O.C., in 1995.

He joined the Logic Technology Division, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, in 1995. He has done extensive research in DRAM, mixed signal and RF processes of CMOS technology, and 3-D electromagnetic simulation on RF passive components.

Gou-Wei Huang was born in Taipei, Taiwan,

R.O.C., in 1969. He received the B.S. degree in electronics engineering and the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1991 and 1997, respectively.

He joined National Nano Device Laboratories, Hsinchu, in 1997 as an Associate Researcher. His current research interests focus on microwave device design, characterization, and modeling.

Tahui Wang (M’86–SM’94) was born in Taoyuan,

Taiwan, R.O.C., on May 3, 1958. He received the B.S.E.E. degree from National Taiwan University, Taipei, in 1980 and the Ph.D. degree in electrical engineering from the University of Illinois, Ur-bana-Champaign, in 1985.

From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, where he is currently a Professor. His research inter-ests include hot-carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices and nonvolatile semiconduct or devices.

Dr. Wang was given the Best Teacher Award by Taiwan’s Ministry of Ed-ucation. He has served as technical committee member of many international conferences, among them IEDM, IRPS, and VLSI-TSA.